hw/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3 /* PC-style peripherals (also used by other machines).  */
   4
   5 /* serial.c */
   6
   7 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
   8                          CharDriverState *chr);
   9 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
  10                              qemu_irq irq, int baudbase,
  11                              CharDriverState *chr, int ioregister);
  12 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
  13 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
  14 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
  15 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
  16 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
  17 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
  18
  19 /* parallel.c */
  20
  21 typedef struct ParallelState ParallelState;
  22 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
  23 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
  24
  25 /* i8259.c */
  26
  27 typedef struct PicState2 PicState2;
  28 extern PicState2 *isa_pic;
  29 void pic_set_irq(int irq, int level);
  30 void pic_set_irq_new(void *opaque, int irq, int level);
  31 qemu_irq *i8259_init(qemu_irq parent_irq);
  32 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
  33                           void *alt_irq_opaque);
  34 int pic_read_irq(PicState2 *s);
  35 void pic_update_irq(PicState2 *s);
  36 uint32_t pic_intack_read(PicState2 *s);
  37 void pic_info(void);
  38 void irq_info(void);
  39
  40 /* APIC */
  41 typedef struct IOAPICState IOAPICState;
  42
  43 int apic_init(CPUState *env);
  44 int apic_accept_pic_intr(CPUState *env);
  45 void apic_deliver_pic_intr(CPUState *env, int level);
  46 int apic_get_interrupt(CPUState *env);
  47 IOAPICState *ioapic_init(void);
  48 void ioapic_set_irq(void *opaque, int vector, int level);
  49
  50 /* i8254.c */
  51
  52 #define PIT_FREQ 1193182
  53
  54 typedef struct PITState PITState;
  55
  56 PITState *pit_init(int base, qemu_irq irq);
  57 void pit_set_gate(PITState *pit, int channel, int val);
  58 int pit_get_gate(PITState *pit, int channel);
  59 int pit_get_initial_count(PITState *pit, int channel);
  60 int pit_get_mode(PITState *pit, int channel);
  61 int pit_get_out(PITState *pit, int channel, int64_t current_time);
  62
  63 /* i8254-kvm.c */
  64
  65 PITState *kvm_pit_init(int base, qemu_irq irq);
  66
  67 void hpet_pit_disable(void);
  68 void hpet_pit_enable(void);
  69
  70 /* vmport.c */
  71 void vmport_init(void);
  72 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
  73
  74 /* vmmouse.c */
  75 void *vmmouse_init(void *m);
  76
  77 /* pckbd.c */
  78
  79 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
  80 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  81                    target_phys_addr_t base, ram_addr_t size,
  82                    target_phys_addr_t mask);
  83
  84 /* mc146818rtc.c */
  85
  86 typedef struct RTCState RTCState;
  87
  88 RTCState *rtc_init(int base, qemu_irq irq);
  89 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
  90 void rtc_set_memory(RTCState *s, int addr, int val);
  91 void rtc_set_date(RTCState *s, const struct tm *tm);
  92 void cmos_set_s3_resume(void);
  93
  94 /* pc.c */
  95 extern int fd_bootchk;
  96
  97 void ioport_set_a20(int enable);
  98 int ioport_get_a20(void);
  99 CPUState *pc_new_cpu(int cpu, const char *cpu_model, int pci_enabled);
 100
 101 /* acpi.c */
 102 extern int acpi_enabled;
 103 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 104                        qemu_irq sci_irq);
 105 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 106 void acpi_bios_init(void);
 107
 108 /* hpet.c */
 109 extern int no_hpet;
 110
 111 /* pcspk.c */
 112 void pcspk_init(PITState *);
 113 int pcspk_audio_init(AudioState *, qemu_irq *pic);
 114
 115 /* piix_pci.c */
 116 /* config space register for IRQ routing */
 117 #define PIIX_CONFIG_IRQ_ROUTE 0x60
 118
 119 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
 120 void i440fx_set_smm(PCIDevice *d, int val);
 121 int piix3_init(PCIBus *bus, int devfn);
 122 void i440fx_init_memory_mappings(PCIDevice *d);
 123
 124 extern PCIDevice *piix4_dev;
 125 int piix4_init(PCIBus *bus, int devfn);
 126
 127 int piix_get_irq(int pin);
 128
 129 int ipf_map_irq(PCIDevice *pci_dev, int irq_num);
 130
 131 /* vga.c */
 132 enum vga_retrace_method {
 133     VGA_RETRACE_DUMB,
 134     VGA_RETRACE_PRECISE
 135 };
 136
 137 extern enum vga_retrace_method vga_retrace_method;
 138
 139 #ifndef TARGET_SPARC
 140 #define VGA_RAM_SIZE (16 * 1024 * 1024)
 141 #else
 142 #define VGA_RAM_SIZE (17 * 1024 * 1024)
 143 #endif
 144
 145 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 146                  unsigned long vga_ram_offset, int vga_ram_size);
 147 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 148                  unsigned long vga_ram_offset, int vga_ram_size,
 149                  unsigned long vga_bios_offset, int vga_bios_size);
 150 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
 151                     unsigned long vga_ram_offset, int vga_ram_size,
 152                     target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
 153                     int it_shift);
 154
 155 /* cirrus_vga.c */
 156 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 157                          ram_addr_t vga_ram_offset, int vga_ram_size);
 158 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 159                          ram_addr_t vga_ram_offset, int vga_ram_size);
 160
 161 /* ide.c */
 162 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
 163                   BlockDriverState *hd0, BlockDriverState *hd1);
 164 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
 165                          int secondary_ide_enabled);
 166 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 167                         qemu_irq *pic);
 168 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 169                         qemu_irq *pic);
 170
 171 /* ne2000.c */
 172
 173 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
 174
 175 /* extboot.c */
 176
 177 void extboot_init(BlockDriverState *bs, int cmd);
 178
 179 #endif