gdbstub.c

   1 /*
   2  * gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "config.h"
  21 #include "qemu-common.h"
  22 #ifdef CONFIG_USER_ONLY
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <stdarg.h>
  26 #include <string.h>
  27 #include <errno.h>
  28 #include <unistd.h>
  29 #include <fcntl.h>
  30
  31 #include "qemu.h"
  32 #else
  33 #include "qemu-char.h"
  34 #include "sysemu.h"
  35 #include "gdbstub.h"
  36 #include "qemu-kvm.h"
  37 #endif
  38
  39 #define MAX_PACKET_LENGTH 4096
  40
  41 #include "qemu_socket.h"
  42
  43
  44 enum {
  45     GDB_SIGNAL_0 = 0,
  46     GDB_SIGNAL_INT = 2,
  47     GDB_SIGNAL_TRAP = 5,
  48     GDB_SIGNAL_UNKNOWN = 143
  49 };
  50
  51 #ifdef CONFIG_USER_ONLY
  52
  53 /* Map target signal numbers to GDB protocol signal numbers and vice
  54  * versa.  For user emulation's currently supported systems, we can
  55  * assume most signals are defined.
  56  */
  57
  58 static int gdb_signal_table[] = {
  59     0,
  60     TARGET_SIGHUP,
  61     TARGET_SIGINT,
  62     TARGET_SIGQUIT,
  63     TARGET_SIGILL,
  64     TARGET_SIGTRAP,
  65     TARGET_SIGABRT,
  66     -1, /* SIGEMT */
  67     TARGET_SIGFPE,
  68     TARGET_SIGKILL,
  69     TARGET_SIGBUS,
  70     TARGET_SIGSEGV,
  71     TARGET_SIGSYS,
  72     TARGET_SIGPIPE,
  73     TARGET_SIGALRM,
  74     TARGET_SIGTERM,
  75     TARGET_SIGURG,
  76     TARGET_SIGSTOP,
  77     TARGET_SIGTSTP,
  78     TARGET_SIGCONT,
  79     TARGET_SIGCHLD,
  80     TARGET_SIGTTIN,
  81     TARGET_SIGTTOU,
  82     TARGET_SIGIO,
  83     TARGET_SIGXCPU,
  84     TARGET_SIGXFSZ,
  85     TARGET_SIGVTALRM,
  86     TARGET_SIGPROF,
  87     TARGET_SIGWINCH,
  88     -1, /* SIGLOST */
  89     TARGET_SIGUSR1,
  90     TARGET_SIGUSR2,
  91 #ifdef TARGET_SIGPWR
  92     TARGET_SIGPWR,
  93 #else
  94     -1,
  95 #endif
  96     -1, /* SIGPOLL */
  97     -1,
  98     -1,
  99     -1,
 100     -1,
 101     -1,
 102     -1,
 103     -1,
 104     -1,
 105     -1,
 106     -1,
 107     -1,
 108 #ifdef __SIGRTMIN
 109     __SIGRTMIN + 1,
 110     __SIGRTMIN + 2,
 111     __SIGRTMIN + 3,
 112     __SIGRTMIN + 4,
 113     __SIGRTMIN + 5,
 114     __SIGRTMIN + 6,
 115     __SIGRTMIN + 7,
 116     __SIGRTMIN + 8,
 117     __SIGRTMIN + 9,
 118     __SIGRTMIN + 10,
 119     __SIGRTMIN + 11,
 120     __SIGRTMIN + 12,
 121     __SIGRTMIN + 13,
 122     __SIGRTMIN + 14,
 123     __SIGRTMIN + 15,
 124     __SIGRTMIN + 16,
 125     __SIGRTMIN + 17,
 126     __SIGRTMIN + 18,
 127     __SIGRTMIN + 19,
 128     __SIGRTMIN + 20,
 129     __SIGRTMIN + 21,
 130     __SIGRTMIN + 22,
 131     __SIGRTMIN + 23,
 132     __SIGRTMIN + 24,
 133     __SIGRTMIN + 25,
 134     __SIGRTMIN + 26,
 135     __SIGRTMIN + 27,
 136     __SIGRTMIN + 28,
 137     __SIGRTMIN + 29,
 138     __SIGRTMIN + 30,
 139     __SIGRTMIN + 31,
 140     -1, /* SIGCANCEL */
 141     __SIGRTMIN,
 142     __SIGRTMIN + 32,
 143     __SIGRTMIN + 33,
 144     __SIGRTMIN + 34,
 145     __SIGRTMIN + 35,
 146     __SIGRTMIN + 36,
 147     __SIGRTMIN + 37,
 148     __SIGRTMIN + 38,
 149     __SIGRTMIN + 39,
 150     __SIGRTMIN + 40,
 151     __SIGRTMIN + 41,
 152     __SIGRTMIN + 42,
 153     __SIGRTMIN + 43,
 154     __SIGRTMIN + 44,
 155     __SIGRTMIN + 45,
 156     __SIGRTMIN + 46,
 157     __SIGRTMIN + 47,
 158     __SIGRTMIN + 48,
 159     __SIGRTMIN + 49,
 160     __SIGRTMIN + 50,
 161     __SIGRTMIN + 51,
 162     __SIGRTMIN + 52,
 163     __SIGRTMIN + 53,
 164     __SIGRTMIN + 54,
 165     __SIGRTMIN + 55,
 166     __SIGRTMIN + 56,
 167     __SIGRTMIN + 57,
 168     __SIGRTMIN + 58,
 169     __SIGRTMIN + 59,
 170     __SIGRTMIN + 60,
 171     __SIGRTMIN + 61,
 172     __SIGRTMIN + 62,
 173     __SIGRTMIN + 63,
 174     __SIGRTMIN + 64,
 175     __SIGRTMIN + 65,
 176     __SIGRTMIN + 66,
 177     __SIGRTMIN + 67,
 178     __SIGRTMIN + 68,
 179     __SIGRTMIN + 69,
 180     __SIGRTMIN + 70,
 181     __SIGRTMIN + 71,
 182     __SIGRTMIN + 72,
 183     __SIGRTMIN + 73,
 184     __SIGRTMIN + 74,
 185     __SIGRTMIN + 75,
 186     __SIGRTMIN + 76,
 187     __SIGRTMIN + 77,
 188     __SIGRTMIN + 78,
 189     __SIGRTMIN + 79,
 190     __SIGRTMIN + 80,
 191     __SIGRTMIN + 81,
 192     __SIGRTMIN + 82,
 193     __SIGRTMIN + 83,
 194     __SIGRTMIN + 84,
 195     __SIGRTMIN + 85,
 196     __SIGRTMIN + 86,
 197     __SIGRTMIN + 87,
 198     __SIGRTMIN + 88,
 199     __SIGRTMIN + 89,
 200     __SIGRTMIN + 90,
 201     __SIGRTMIN + 91,
 202     __SIGRTMIN + 92,
 203     __SIGRTMIN + 93,
 204     __SIGRTMIN + 94,
 205     __SIGRTMIN + 95,
 206     -1, /* SIGINFO */
 207     -1, /* UNKNOWN */
 208     -1, /* DEFAULT */
 209     -1,
 210     -1,
 211     -1,
 212     -1,
 213     -1,
 214     -1
 215 #endif
 216 };
 217 #else
 218 /* In system mode we only need SIGINT and SIGTRAP; other signals
 219    are not yet supported.  */
 220
 221 enum {
 222     TARGET_SIGINT = 2,
 223     TARGET_SIGTRAP = 5
 224 };
 225
 226 static int gdb_signal_table[] = {
 227     -1,
 228     -1,
 229     TARGET_SIGINT,
 230     -1,
 231     -1,
 232     TARGET_SIGTRAP
 233 };
 234 #endif
 235
 236 #ifdef CONFIG_USER_ONLY
 237 static int target_signal_to_gdb (int sig)
 238 {
 239     int i;
 240     for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
 241         if (gdb_signal_table[i] == sig)
 242             return i;
 243     return GDB_SIGNAL_UNKNOWN;
 244 }
 245 #endif
 246
 247 static int gdb_signal_to_target (int sig)
 248 {
 249     if (sig < ARRAY_SIZE (gdb_signal_table))
 250         return gdb_signal_table[sig];
 251     else
 252         return -1;
 253 }
 254
 255 //#define DEBUG_GDB
 256
 257 typedef struct GDBRegisterState {
 258     int base_reg;
 259     int num_regs;
 260     gdb_reg_cb get_reg;
 261     gdb_reg_cb set_reg;
 262     const char *xml;
 263     struct GDBRegisterState *next;
 264 } GDBRegisterState;
 265
 266 enum RSState {
 267     RS_IDLE,
 268     RS_GETLINE,
 269     RS_CHKSUM1,
 270     RS_CHKSUM2,
 271     RS_SYSCALL,
 272 };
 273 typedef struct GDBState {
 274     CPUState *c_cpu; /* current CPU for step/continue ops */
 275     CPUState *g_cpu; /* current CPU for other ops */
 276     CPUState *query_cpu; /* for q{f|s}ThreadInfo */
 277     enum RSState state; /* parsing state */
 278     char line_buf[MAX_PACKET_LENGTH];
 279     int line_buf_index;
 280     int line_csum;
 281     uint8_t last_packet[MAX_PACKET_LENGTH + 4];
 282     int last_packet_len;
 283     int signal;
 284 #ifdef CONFIG_USER_ONLY
 285     int fd;
 286     int running_state;
 287 #else
 288     CharDriverState *chr;
 289 #endif
 290 } GDBState;
 291
 292 /* By default use no IRQs and no timers while single stepping so as to
 293  * make single stepping like an ICE HW step.
 294  */
 295 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
 296
 297 static GDBState *gdbserver_state;
 298
 299 /* This is an ugly hack to cope with both new and old gdb.
 300    If gdb sends qXfer:features:read then assume we're talking to a newish
 301    gdb that understands target descriptions.  */
 302 static int gdb_has_xml;
 303
 304 #ifdef CONFIG_USER_ONLY
 305 /* XXX: This is not thread safe.  Do we care?  */
 306 static int gdbserver_fd = -1;
 307
 308 static int get_char(GDBState *s)
 309 {
 310     uint8_t ch;
 311     int ret;
 312
 313     for(;;) {
 314         ret = recv(s->fd, &ch, 1, 0);
 315         if (ret < 0) {
 316             if (errno == ECONNRESET)
 317                 s->fd = -1;
 318             if (errno != EINTR && errno != EAGAIN)
 319                 return -1;
 320         } else if (ret == 0) {
 321             close(s->fd);
 322             s->fd = -1;
 323             return -1;
 324         } else {
 325             break;
 326         }
 327     }
 328     return ch;
 329 }
 330 #endif
 331
 332 static gdb_syscall_complete_cb gdb_current_syscall_cb;
 333
 334 enum {
 335     GDB_SYS_UNKNOWN,
 336     GDB_SYS_ENABLED,
 337     GDB_SYS_DISABLED,
 338 } gdb_syscall_mode;
 339
 340 /* If gdb is connected when the first semihosting syscall occurs then use
 341    remote gdb syscalls.  Otherwise use native file IO.  */
 342 int use_gdb_syscalls(void)
 343 {
 344     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
 345         gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
 346                                             : GDB_SYS_DISABLED);
 347     }
 348     return gdb_syscall_mode == GDB_SYS_ENABLED;
 349 }
 350
 351 /* Resume execution.  */
 352 static inline void gdb_continue(GDBState *s)
 353 {
 354 #ifdef CONFIG_USER_ONLY
 355     s->running_state = 1;
 356 #else
 357     vm_start();
 358 #endif
 359 }
 360
 361 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
 362 {
 363 #ifdef CONFIG_USER_ONLY
 364     int ret;
 365
 366     while (len > 0) {
 367         ret = send(s->fd, buf, len, 0);
 368         if (ret < 0) {
 369             if (errno != EINTR && errno != EAGAIN)
 370                 return;
 371         } else {
 372             buf += ret;
 373             len -= ret;
 374         }
 375     }
 376 #else
 377     qemu_chr_write(s->chr, buf, len);
 378 #endif
 379 }
 380
 381 static inline int fromhex(int v)
 382 {
 383     if (v >= '0' && v <= '9')
 384         return v - '0';
 385     else if (v >= 'A' && v <= 'F')
 386         return v - 'A' + 10;
 387     else if (v >= 'a' && v <= 'f')
 388         return v - 'a' + 10;
 389     else
 390         return 0;
 391 }
 392
 393 static inline int tohex(int v)
 394 {
 395     if (v < 10)
 396         return v + '0';
 397     else
 398         return v - 10 + 'a';
 399 }
 400
 401 static void memtohex(char *buf, const uint8_t *mem, int len)
 402 {
 403     int i, c;
 404     char *q;
 405     q = buf;
 406     for(i = 0; i < len; i++) {
 407         c = mem[i];
 408         *q++ = tohex(c >> 4);
 409         *q++ = tohex(c & 0xf);
 410     }
 411     *q = '\0';
 412 }
 413
 414 static void hextomem(uint8_t *mem, const char *buf, int len)
 415 {
 416     int i;
 417
 418     for(i = 0; i < len; i++) {
 419         mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
 420         buf += 2;
 421     }
 422 }
 423
 424 /* return -1 if error, 0 if OK */
 425 static int put_packet_binary(GDBState *s, const char *buf, int len)
 426 {
 427     int csum, i;
 428     uint8_t *p;
 429
 430     for(;;) {
 431         p = s->last_packet;
 432         *(p++) = '$';
 433         memcpy(p, buf, len);
 434         p += len;
 435         csum = 0;
 436         for(i = 0; i < len; i++) {
 437             csum += buf[i];
 438         }
 439         *(p++) = '#';
 440         *(p++) = tohex((csum >> 4) & 0xf);
 441         *(p++) = tohex((csum) & 0xf);
 442
 443         s->last_packet_len = p - s->last_packet;
 444         put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
 445
 446 #ifdef CONFIG_USER_ONLY
 447         i = get_char(s);
 448         if (i < 0)
 449             return -1;
 450         if (i == '+')
 451             break;
 452 #else
 453         break;
 454 #endif
 455     }
 456     return 0;
 457 }
 458
 459 /* return -1 if error, 0 if OK */
 460 static int put_packet(GDBState *s, const char *buf)
 461 {
 462 #ifdef DEBUG_GDB
 463     printf("reply='%s'\n", buf);
 464 #endif
 465
 466     return put_packet_binary(s, buf, strlen(buf));
 467 }
 468
 469 /* The GDB remote protocol transfers values in target byte order.  This means
 470    we can use the raw memory access routines to access the value buffer.
 471    Conveniently, these also handle the case where the buffer is mis-aligned.
 472  */
 473 #define GET_REG8(val) do { \
 474     stb_p(mem_buf, val); \
 475     return 1; \
 476     } while(0)
 477 #define GET_REG16(val) do { \
 478     stw_p(mem_buf, val); \
 479     return 2; \
 480     } while(0)
 481 #define GET_REG32(val) do { \
 482     stl_p(mem_buf, val); \
 483     return 4; \
 484     } while(0)
 485 #define GET_REG64(val) do { \
 486     stq_p(mem_buf, val); \
 487     return 8; \
 488     } while(0)
 489
 490 #if TARGET_LONG_BITS == 64
 491 #define GET_REGL(val) GET_REG64(val)
 492 #define ldtul_p(addr) ldq_p(addr)
 493 #else
 494 #define GET_REGL(val) GET_REG32(val)
 495 #define ldtul_p(addr) ldl_p(addr)
 496 #endif
 497
 498 #if defined(TARGET_I386)
 499
 500 #ifdef TARGET_X86_64
 501 static const int gpr_map[16] = {
 502     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
 503     8, 9, 10, 11, 12, 13, 14, 15
 504 };
 505 #else
 506 static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
 507 #endif
 508
 509 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
 510
 511 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 512 {
 513     if (n < CPU_NB_REGS) {
 514         GET_REGL(env->regs[gpr_map[n]]);
 515     } else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) {
 516         /* FIXME: byteswap float values.  */
 517 #ifdef USE_X86LDOUBLE
 518         memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10);
 519 #else
 520         memset(mem_buf, 0, 10);
 521 #endif
 522         return 10;
 523     } else if (n >= CPU_NB_REGS + 24) {
 524         n -= CPU_NB_REGS + 24;
 525         if (n < CPU_NB_REGS) {
 526             stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
 527             stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
 528             return 16;
 529         } else if (n == CPU_NB_REGS) {
 530             GET_REG32(env->mxcsr);
 531         }
 532     } else {
 533         n -= CPU_NB_REGS;
 534         switch (n) {
 535         case 0: GET_REGL(env->eip);
 536         case 1: GET_REG32(env->eflags);
 537         case 2: GET_REG32(env->segs[R_CS].selector);
 538         case 3: GET_REG32(env->segs[R_SS].selector);
 539         case 4: GET_REG32(env->segs[R_DS].selector);
 540         case 5: GET_REG32(env->segs[R_ES].selector);
 541         case 6: GET_REG32(env->segs[R_FS].selector);
 542         case 7: GET_REG32(env->segs[R_GS].selector);
 543         /* 8...15 x87 regs.  */
 544         case 16: GET_REG32(env->fpuc);
 545         case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11);
 546         case 18: GET_REG32(0); /* ftag */
 547         case 19: GET_REG32(0); /* fiseg */
 548         case 20: GET_REG32(0); /* fioff */
 549         case 21: GET_REG32(0); /* foseg */
 550         case 22: GET_REG32(0); /* fooff */
 551         case 23: GET_REG32(0); /* fop */
 552         /* 24+ xmm regs.  */
 553         }
 554     }
 555     return 0;
 556 }
 557
 558 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)
 559 {
 560     uint32_t tmp;
 561
 562     if (i < CPU_NB_REGS) {
 563         env->regs[gpr_map[i]] = ldtul_p(mem_buf);
 564         return sizeof(target_ulong);
 565     } else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) {
 566         i -= CPU_NB_REGS + 8;
 567 #ifdef USE_X86LDOUBLE
 568         memcpy(&env->fpregs[i], mem_buf, 10);
 569 #endif
 570         return 10;
 571     } else if (i >= CPU_NB_REGS + 24) {
 572         i -= CPU_NB_REGS + 24;
 573         if (i < CPU_NB_REGS) {
 574             env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf);
 575             env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8);
 576             return 16;
 577         } else if (i == CPU_NB_REGS) {
 578             env->mxcsr = ldl_p(mem_buf);
 579             return 4;
 580         }
 581     } else {
 582         i -= CPU_NB_REGS;
 583         switch (i) {
 584         case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong);
 585         case 1: env->eflags = ldl_p(mem_buf); return 4;
 586 #if defined(CONFIG_USER_ONLY)
 587 #define LOAD_SEG(index, sreg)\
 588             tmp = ldl_p(mem_buf);\
 589             if (tmp != env->segs[sreg].selector)\
 590                 cpu_x86_load_seg(env, sreg, tmp);
 591 #else
 592 /* FIXME: Honor segment registers.  Needs to avoid raising an exception
 593    when the selector is invalid.  */
 594 #define LOAD_SEG(index, sreg) do {} while(0)
 595 #endif
 596         case 2: LOAD_SEG(10, R_CS); return 4;
 597         case 3: LOAD_SEG(11, R_SS); return 4;
 598         case 4: LOAD_SEG(12, R_DS); return 4;
 599         case 5: LOAD_SEG(13, R_ES); return 4;
 600         case 6: LOAD_SEG(14, R_FS); return 4;
 601         case 7: LOAD_SEG(15, R_GS); return 4;
 602         /* 8...15 x87 regs.  */
 603         case 16: env->fpuc = ldl_p(mem_buf); return 4;
 604         case 17:
 605                  tmp = ldl_p(mem_buf);
 606                  env->fpstt = (tmp >> 11) & 7;
 607                  env->fpus = tmp & ~0x3800;
 608                  return 4;
 609         case 18: /* ftag */ return 4;
 610         case 19: /* fiseg */ return 4;
 611         case 20: /* fioff */ return 4;
 612         case 21: /* foseg */ return 4;
 613         case 22: /* fooff */ return 4;
 614         case 23: /* fop */ return 4;
 615         /* 24+ xmm regs.  */
 616         }
 617     }
 618     /* Unrecognised register.  */
 619     return 0;
 620 }
 621
 622 #elif defined (TARGET_PPC)
 623
 624 #define NUM_CORE_REGS 71
 625
 626 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 627 {
 628     if (n < 32) {
 629         /* gprs */
 630         GET_REGL(env->gpr[n]);
 631     } else if (n < 64) {
 632         /* fprs */
 633         stfq_p(mem_buf, env->fpr[n-32]);
 634         return 8;
 635     } else {
 636         switch (n) {
 637         case 64: GET_REGL(env->nip);
 638         case 65: GET_REGL(env->msr);
 639         case 66:
 640             {
 641                 uint32_t cr = 0;
 642                 int i;
 643                 for (i = 0; i < 8; i++)
 644                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
 645                 GET_REG32(cr);
 646             }
 647         case 67: GET_REGL(env->lr);
 648         case 68: GET_REGL(env->ctr);
 649         case 69: GET_REGL(env->xer);
 650         case 70: GET_REG32(0); /* fpscr */
 651         }
 652     }
 653     return 0;
 654 }
 655
 656 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 657 {
 658     if (n < 32) {
 659         /* gprs */
 660         env->gpr[n] = ldtul_p(mem_buf);
 661         return sizeof(target_ulong);
 662     } else if (n < 64) {
 663         /* fprs */
 664         env->fpr[n-32] = ldfq_p(mem_buf);
 665         return 8;
 666     } else {
 667         switch (n) {
 668         case 64:
 669             env->nip = ldtul_p(mem_buf);
 670             return sizeof(target_ulong);
 671         case 65:
 672             ppc_store_msr(env, ldtul_p(mem_buf));
 673             return sizeof(target_ulong);
 674         case 66:
 675             {
 676                 uint32_t cr = ldl_p(mem_buf);
 677                 int i;
 678                 for (i = 0; i < 8; i++)
 679                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
 680                 return 4;
 681             }
 682         case 67:
 683             env->lr = ldtul_p(mem_buf);
 684             return sizeof(target_ulong);
 685         case 68:
 686             env->ctr = ldtul_p(mem_buf);
 687             return sizeof(target_ulong);
 688         case 69:
 689             env->xer = ldtul_p(mem_buf);
 690             return sizeof(target_ulong);
 691         case 70:
 692             /* fpscr */
 693             return 4;
 694         }
 695     }
 696     return 0;
 697 }
 698
 699 #elif defined (TARGET_SPARC)
 700
 701 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
 702 #define NUM_CORE_REGS 86
 703 #else
 704 #define NUM_CORE_REGS 72
 705 #endif
 706
 707 #ifdef TARGET_ABI32
 708 #define GET_REGA(val) GET_REG32(val)
 709 #else
 710 #define GET_REGA(val) GET_REGL(val)
 711 #endif
 712
 713 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 714 {
 715     if (n < 8) {
 716         /* g0..g7 */
 717         GET_REGA(env->gregs[n]);
 718     }
 719     if (n < 32) {
 720         /* register window */
 721         GET_REGA(env->regwptr[n - 8]);
 722     }
 723 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 724     if (n < 64) {
 725         /* fprs */
 726         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 727     }
 728     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 729     switch (n) {
 730     case 64: GET_REGA(env->y);
 731     case 65: GET_REGA(GET_PSR(env));
 732     case 66: GET_REGA(env->wim);
 733     case 67: GET_REGA(env->tbr);
 734     case 68: GET_REGA(env->pc);
 735     case 69: GET_REGA(env->npc);
 736     case 70: GET_REGA(env->fsr);
 737     case 71: GET_REGA(0); /* csr */
 738     default: GET_REGA(0);
 739     }
 740 #else
 741     if (n < 64) {
 742         /* f0-f31 */
 743         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 744     }
 745     if (n < 80) {
 746         /* f32-f62 (double width, even numbers only) */
 747         uint64_t val;
 748
 749         val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
 750         val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
 751         GET_REG64(val);
 752     }
 753     switch (n) {
 754     case 80: GET_REGL(env->pc);
 755     case 81: GET_REGL(env->npc);
 756     case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
 757                            ((env->asi & 0xff) << 24) |
 758                            ((env->pstate & 0xfff) << 8) |
 759                            GET_CWP64(env));
 760     case 83: GET_REGL(env->fsr);
 761     case 84: GET_REGL(env->fprs);
 762     case 85: GET_REGL(env->y);
 763     }
 764 #endif
 765     return 0;
 766 }
 767
 768 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 769 {
 770 #if defined(TARGET_ABI32)
 771     abi_ulong tmp;
 772
 773     tmp = ldl_p(mem_buf);
 774 #else
 775     target_ulong tmp;
 776
 777     tmp = ldtul_p(mem_buf);
 778 #endif
 779
 780     if (n < 8) {
 781         /* g0..g7 */
 782         env->gregs[n] = tmp;
 783     } else if (n < 32) {
 784         /* register window */
 785         env->regwptr[n - 8] = tmp;
 786     }
 787 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 788     else if (n < 64) {
 789         /* fprs */
 790         *((uint32_t *)&env->fpr[n - 32]) = tmp;
 791     } else {
 792         /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 793         switch (n) {
 794         case 64: env->y = tmp; break;
 795         case 65: PUT_PSR(env, tmp); break;
 796         case 66: env->wim = tmp; break;
 797         case 67: env->tbr = tmp; break;
 798         case 68: env->pc = tmp; break;
 799         case 69: env->npc = tmp; break;
 800         case 70: env->fsr = tmp; break;
 801         default: return 0;
 802         }
 803     }
 804     return 4;
 805 #else
 806     else if (n < 64) {
 807         /* f0-f31 */
 808         env->fpr[n] = ldfl_p(mem_buf);
 809         return 4;
 810     } else if (n < 80) {
 811         /* f32-f62 (double width, even numbers only) */
 812         *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
 813         *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
 814     } else {
 815         switch (n) {
 816         case 80: env->pc = tmp; break;
 817         case 81: env->npc = tmp; break;
 818         case 82:
 819             PUT_CCR(env, tmp >> 32);
 820             env->asi = (tmp >> 24) & 0xff;
 821             env->pstate = (tmp >> 8) & 0xfff;
 822             PUT_CWP64(env, tmp & 0xff);
 823             break;
 824         case 83: env->fsr = tmp; break;
 825         case 84: env->fprs = tmp; break;
 826         case 85: env->y = tmp; break;
 827         default: return 0;
 828         }
 829     }
 830     return 8;
 831 #endif
 832 }
 833 #elif defined (TARGET_ARM)
 834
 835 /* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
 836    whatever the target description contains.  Due to a historical mishap
 837    the FPA registers appear in between core integer regs and the CPSR.
 838    We hack round this by giving the FPA regs zero size when talking to a
 839    newer gdb.  */
 840 #define NUM_CORE_REGS 26
 841 #define GDB_CORE_XML "arm-core.xml"
 842
 843 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 844 {
 845     if (n < 16) {
 846         /* Core integer register.  */
 847         GET_REG32(env->regs[n]);
 848     }
 849     if (n < 24) {
 850         /* FPA registers.  */
 851         if (gdb_has_xml)
 852             return 0;
 853         memset(mem_buf, 0, 12);
 854         return 12;
 855     }
 856     switch (n) {
 857     case 24:
 858         /* FPA status register.  */
 859         if (gdb_has_xml)
 860             return 0;
 861         GET_REG32(0);
 862     case 25:
 863         /* CPSR */
 864         GET_REG32(cpsr_read(env));
 865     }
 866     /* Unknown register.  */
 867     return 0;
 868 }
 869
 870 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 871 {
 872     uint32_t tmp;
 873
 874     tmp = ldl_p(mem_buf);
 875
 876     /* Mask out low bit of PC to workaround gdb bugs.  This will probably
 877        cause problems if we ever implement the Jazelle DBX extensions.  */
 878     if (n == 15)
 879         tmp &= ~1;
 880
 881     if (n < 16) {
 882         /* Core integer register.  */
 883         env->regs[n] = tmp;
 884         return 4;
 885     }
 886     if (n < 24) { /* 16-23 */
 887         /* FPA registers (ignored).  */
 888         if (gdb_has_xml)
 889             return 0;
 890         return 12;
 891     }
 892     switch (n) {
 893     case 24:
 894         /* FPA status register (ignored).  */
 895         if (gdb_has_xml)
 896             return 0;
 897         return 4;
 898     case 25:
 899         /* CPSR */
 900         cpsr_write (env, tmp, 0xffffffff);
 901         return 4;
 902     }
 903     /* Unknown register.  */
 904     return 0;
 905 }
 906
 907 #elif defined (TARGET_M68K)
 908
 909 #define NUM_CORE_REGS 18
 910
 911 #define GDB_CORE_XML "cf-core.xml"
 912
 913 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 914 {
 915     if (n < 8) {
 916         /* D0-D7 */
 917         GET_REG32(env->dregs[n]);
 918     } else if (n < 16) {
 919         /* A0-A7 */
 920         GET_REG32(env->aregs[n - 8]);
 921     } else {
 922         switch (n) {
 923         case 16: GET_REG32(env->sr);
 924         case 17: GET_REG32(env->pc);
 925         }
 926     }
 927     /* FP registers not included here because they vary between
 928        ColdFire and m68k.  Use XML bits for these.  */
 929     return 0;
 930 }
 931
 932 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 933 {
 934     uint32_t tmp;
 935
 936     tmp = ldl_p(mem_buf);
 937
 938     if (n < 8) {
 939         /* D0-D7 */
 940         env->dregs[n] = tmp;
 941     } else if (n < 8) {
 942         /* A0-A7 */
 943         env->aregs[n - 8] = tmp;
 944     } else {
 945         switch (n) {
 946         case 16: env->sr = tmp; break;
 947         case 17: env->pc = tmp; break;
 948         default: return 0;
 949         }
 950     }
 951     return 4;
 952 }
 953 #elif defined (TARGET_MIPS)
 954
 955 #define NUM_CORE_REGS 73
 956
 957 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 958 {
 959     if (n < 32) {
 960         GET_REGL(env->active_tc.gpr[n]);
 961     }
 962     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
 963         if (n >= 38 && n < 70) {
 964             if (env->CP0_Status & (1 << CP0St_FR))
 965                 GET_REGL(env->active_fpu.fpr[n - 38].d);
 966             else
 967                 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
 968         }
 969         switch (n) {
 970         case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
 971         case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
 972         }
 973     }
 974     switch (n) {
 975     case 32: GET_REGL((int32_t)env->CP0_Status);
 976     case 33: GET_REGL(env->active_tc.LO[0]);
 977     case 34: GET_REGL(env->active_tc.HI[0]);
 978     case 35: GET_REGL(env->CP0_BadVAddr);
 979     case 36: GET_REGL((int32_t)env->CP0_Cause);
 980     case 37: GET_REGL(env->active_tc.PC);
 981     case 72: GET_REGL(0); /* fp */
 982     case 89: GET_REGL((int32_t)env->CP0_PRid);
 983     }
 984     if (n >= 73 && n <= 88) {
 985         /* 16 embedded regs.  */
 986         GET_REGL(0);
 987     }
 988
 989     return 0;
 990 }
 991
 992 /* convert MIPS rounding mode in FCR31 to IEEE library */
 993 static unsigned int ieee_rm[] =
 994   {
 995     float_round_nearest_even,
 996     float_round_to_zero,
 997     float_round_up,
 998     float_round_down
 999   };
1000 #define RESTORE_ROUNDING_MODE \
1001     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1002
1003 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1004 {
1005     target_ulong tmp;
1006
1007     tmp = ldtul_p(mem_buf);
1008
1009     if (n < 32) {
1010         env->active_tc.gpr[n] = tmp;
1011         return sizeof(target_ulong);
1012     }
1013     if (env->CP0_Config1 & (1 << CP0C1_FP)
1014             && n >= 38 && n < 73) {
1015         if (n < 70) {
1016             if (env->CP0_Status & (1 << CP0St_FR))
1017               env->active_fpu.fpr[n - 38].d = tmp;
1018             else
1019               env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1020         }
1021         switch (n) {
1022         case 70:
1023             env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1024             /* set rounding mode */
1025             RESTORE_ROUNDING_MODE;
1026 #ifndef CONFIG_SOFTFLOAT
1027             /* no floating point exception for native float */
1028             SET_FP_ENABLE(env->active_fpu.fcr31, 0);
1029 #endif
1030             break;
1031         case 71: env->active_fpu.fcr0 = tmp; break;
1032         }
1033         return sizeof(target_ulong);
1034     }
1035     switch (n) {
1036     case 32: env->CP0_Status = tmp; break;
1037     case 33: env->active_tc.LO[0] = tmp; break;
1038     case 34: env->active_tc.HI[0] = tmp; break;
1039     case 35: env->CP0_BadVAddr = tmp; break;
1040     case 36: env->CP0_Cause = tmp; break;
1041     case 37: env->active_tc.PC = tmp; break;
1042     case 72: /* fp, ignored */ break;
1043     default:
1044         if (n > 89)
1045             return 0;
1046         /* Other registers are readonly.  Ignore writes.  */
1047         break;
1048     }
1049
1050     return sizeof(target_ulong);
1051 }
1052 #elif defined (TARGET_SH4)
1053
1054 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1055 /* FIXME: We should use XML for this.  */
1056
1057 #define NUM_CORE_REGS 59
1058
1059 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1060 {
1061     if (n < 8) {
1062         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1063             GET_REGL(env->gregs[n + 16]);
1064         } else {
1065             GET_REGL(env->gregs[n]);
1066         }
1067     } else if (n < 16) {
1068         GET_REGL(env->gregs[n - 8]);
1069     } else if (n >= 25 && n < 41) {
1070         GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1071     } else if (n >= 43 && n < 51) {
1072         GET_REGL(env->gregs[n - 43]);
1073     } else if (n >= 51 && n < 59) {
1074         GET_REGL(env->gregs[n - (51 - 16)]);
1075     }
1076     switch (n) {
1077     case 16: GET_REGL(env->pc);
1078     case 17: GET_REGL(env->pr);
1079     case 18: GET_REGL(env->gbr);
1080     case 19: GET_REGL(env->vbr);
1081     case 20: GET_REGL(env->mach);
1082     case 21: GET_REGL(env->macl);
1083     case 22: GET_REGL(env->sr);
1084     case 23: GET_REGL(env->fpul);
1085     case 24: GET_REGL(env->fpscr);
1086     case 41: GET_REGL(env->ssr);
1087     case 42: GET_REGL(env->spc);
1088     }
1089
1090     return 0;
1091 }
1092
1093 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1094 {
1095     uint32_t tmp;
1096
1097     tmp = ldl_p(mem_buf);
1098
1099     if (n < 8) {
1100         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1101             env->gregs[n + 16] = tmp;
1102         } else {
1103             env->gregs[n] = tmp;
1104         }
1105         return 4;
1106     } else if (n < 16) {
1107         env->gregs[n - 8] = tmp;
1108         return 4;
1109     } else if (n >= 25 && n < 41) {
1110         env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1111     } else if (n >= 43 && n < 51) {
1112         env->gregs[n - 43] = tmp;
1113         return 4;
1114     } else if (n >= 51 && n < 59) {
1115         env->gregs[n - (51 - 16)] = tmp;
1116         return 4;
1117     }
1118     switch (n) {
1119     case 16: env->pc = tmp;
1120     case 17: env->pr = tmp;
1121     case 18: env->gbr = tmp;
1122     case 19: env->vbr = tmp;
1123     case 20: env->mach = tmp;
1124     case 21: env->macl = tmp;
1125     case 22: env->sr = tmp;
1126     case 23: env->fpul = tmp;
1127     case 24: env->fpscr = tmp;
1128     case 41: env->ssr = tmp;
1129     case 42: env->spc = tmp;
1130     default: return 0;
1131     }
1132
1133     return 4;
1134 }
1135 #elif defined (TARGET_CRIS)
1136
1137 #define NUM_CORE_REGS 49
1138
1139 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1140 {
1141     uint8_t srs;
1142
1143     srs = env->pregs[PR_SRS];
1144     if (n < 16) {
1145         GET_REG32(env->regs[n]);
1146     }
1147
1148     if (n >= 21 && n < 32) {
1149         GET_REG32(env->pregs[n - 16]);
1150     }
1151     if (n >= 33 && n < 49) {
1152         GET_REG32(env->sregs[srs][n - 33]);
1153     }
1154     switch (n) {
1155     case 16: GET_REG8(env->pregs[0]);
1156     case 17: GET_REG8(env->pregs[1]);
1157     case 18: GET_REG32(env->pregs[2]);
1158     case 19: GET_REG8(srs);
1159     case 20: GET_REG16(env->pregs[4]);
1160     case 32: GET_REG32(env->pc);
1161     }
1162
1163     return 0;
1164 }
1165
1166 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1167 {
1168     uint32_t tmp;
1169
1170     if (n > 49)
1171         return 0;
1172
1173     tmp = ldl_p(mem_buf);
1174
1175     if (n < 16) {
1176         env->regs[n] = tmp;
1177     }
1178
1179     if (n >= 21 && n < 32) {
1180         env->pregs[n - 16] = tmp;
1181     }
1182
1183     /* FIXME: Should support function regs be writable?  */
1184     switch (n) {
1185     case 16: return 1;
1186     case 17: return 1;
1187     case 18: env->pregs[PR_PID] = tmp; break;
1188     case 19: return 1;
1189     case 20: return 2;
1190     case 32: env->pc = tmp; break;
1191     }
1192
1193     return 4;
1194 }
1195 #elif defined (TARGET_ALPHA)
1196
1197 #define NUM_CORE_REGS 65
1198
1199 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1200 {
1201     if (n < 31) {
1202        GET_REGL(env->ir[n]);
1203     }
1204     else if (n == 31) {
1205        GET_REGL(0);
1206     }
1207     else if (n<63) {
1208        uint64_t val;
1209
1210        val=*((uint64_t *)&env->fir[n-32]);
1211        GET_REGL(val);
1212     }
1213     else if (n==63) {
1214        GET_REGL(env->fpcr);
1215     }
1216     else if (n==64) {
1217        GET_REGL(env->pc);
1218     }
1219     else {
1220        GET_REGL(0);
1221     }
1222
1223     return 0;
1224 }
1225
1226 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1227 {
1228     target_ulong tmp;
1229     tmp = ldtul_p(mem_buf);
1230
1231     if (n < 31) {
1232         env->ir[n] = tmp;
1233     }
1234
1235     if (n > 31 && n < 63) {
1236         env->fir[n - 32] = ldfl_p(mem_buf);
1237     }
1238
1239     if (n == 64 ) {
1240        env->pc=tmp;
1241     }
1242
1243     return 8;
1244 }
1245 #else
1246
1247 #define NUM_CORE_REGS 0
1248
1249 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1250 {
1251     return 0;
1252 }
1253
1254 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1255 {
1256     return 0;
1257 }
1258
1259 #endif
1260
1261 static int num_g_regs = NUM_CORE_REGS;
1262
1263 #ifdef GDB_CORE_XML
1264 /* Encode data using the encoding for 'x' packets.  */
1265 static int memtox(char *buf, const char *mem, int len)
1266 {
1267     char *p = buf;
1268     char c;
1269
1270     while (len--) {
1271         c = *(mem++);
1272         switch (c) {
1273         case '#': case '$': case '*': case '}':
1274             *(p++) = '}';
1275             *(p++) = c ^ 0x20;
1276             break;
1277         default:
1278             *(p++) = c;
1279             break;
1280         }
1281     }
1282     return p - buf;
1283 }
1284
1285 static const char *get_feature_xml(const char *p, const char **newp)
1286 {
1287     extern const char *const xml_builtin[][2];
1288     size_t len;
1289     int i;
1290     const char *name;
1291     static char target_xml[1024];
1292
1293     len = 0;
1294     while (p[len] && p[len] != ':')
1295         len++;
1296     *newp = p + len;
1297
1298     name = NULL;
1299     if (strncmp(p, "target.xml", len) == 0) {
1300         /* Generate the XML description for this CPU.  */
1301         if (!target_xml[0]) {
1302             GDBRegisterState *r;
1303
1304             snprintf(target_xml, sizeof(target_xml),
1305                      "<?xml version=\"1.0\"?>"
1306                      "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1307                      "<target>"
1308                      "<xi:include href=\"%s\"/>",
1309                      GDB_CORE_XML);
1310
1311             for (r = first_cpu->gdb_regs; r; r = r->next) {
1312                 strcat(target_xml, "<xi:include href=\"");
1313                 strcat(target_xml, r->xml);
1314                 strcat(target_xml, "\"/>");
1315             }
1316             strcat(target_xml, "</target>");
1317         }
1318         return target_xml;
1319     }
1320     for (i = 0; ; i++) {
1321         name = xml_builtin[i][0];
1322         if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1323             break;
1324     }
1325     return name ? xml_builtin[i][1] : NULL;
1326 }
1327 #endif
1328
1329 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1330 {
1331     GDBRegisterState *r;
1332
1333     if (reg < NUM_CORE_REGS)
1334         return cpu_gdb_read_register(env, mem_buf, reg);
1335
1336     for (r = env->gdb_regs; r; r = r->next) {
1337         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1338             return r->get_reg(env, mem_buf, reg - r->base_reg);
1339         }
1340     }
1341     return 0;
1342 }
1343
1344 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1345 {
1346     GDBRegisterState *r;
1347
1348     if (reg < NUM_CORE_REGS)
1349         return cpu_gdb_write_register(env, mem_buf, reg);
1350
1351     for (r = env->gdb_regs; r; r = r->next) {
1352         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1353             return r->set_reg(env, mem_buf, reg - r->base_reg);
1354         }
1355     }
1356     return 0;
1357 }
1358
1359 /* Register a supplemental set of CPU registers.  If g_pos is nonzero it
1360    specifies the first register number and these registers are included in
1361    a standard "g" packet.  Direction is relative to gdb, i.e. get_reg is
1362    gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1363  */
1364
1365 void gdb_register_coprocessor(CPUState * env,
1366                              gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1367                              int num_regs, const char *xml, int g_pos)
1368 {
1369     GDBRegisterState *s;
1370     GDBRegisterState **p;
1371     static int last_reg = NUM_CORE_REGS;
1372
1373     s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1374     s->base_reg = last_reg;
1375     s->num_regs = num_regs;
1376     s->get_reg = get_reg;
1377     s->set_reg = set_reg;
1378     s->xml = xml;
1379     p = &env->gdb_regs;
1380     while (*p) {
1381         /* Check for duplicates.  */
1382         if (strcmp((*p)->xml, xml) == 0)
1383             return;
1384         p = &(*p)->next;
1385     }
1386     /* Add to end of list.  */
1387     last_reg += num_regs;
1388     *p = s;
1389     if (g_pos) {
1390         if (g_pos != s->base_reg) {
1391             fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1392                     "Expected %d got %d\n", xml, g_pos, s->base_reg);
1393         } else {
1394             num_g_regs = last_reg;
1395         }
1396     }
1397 }
1398
1399 #ifndef CONFIG_USER_ONLY
1400 static const int xlat_gdb_type[] = {
1401     [GDB_WATCHPOINT_WRITE]  = BP_GDB | BP_MEM_WRITE,
1402     [GDB_WATCHPOINT_READ]   = BP_GDB | BP_MEM_READ,
1403     [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1404 };
1405 #endif
1406
1407 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1408 {
1409     CPUState *env;
1410     int err = 0;
1411
1412     if (kvm_enabled())
1413         return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1414
1415     switch (type) {
1416     case GDB_BREAKPOINT_SW:
1417     case GDB_BREAKPOINT_HW:
1418         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1419             err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1420             if (err)
1421                 break;
1422         }
1423         return err;
1424 #ifndef CONFIG_USER_ONLY
1425     case GDB_WATCHPOINT_WRITE:
1426     case GDB_WATCHPOINT_READ:
1427     case GDB_WATCHPOINT_ACCESS:
1428         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1429             err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1430                                         NULL);
1431             if (err)
1432                 break;
1433         }
1434         return err;
1435 #endif
1436     default:
1437         return -ENOSYS;
1438     }
1439 }
1440
1441 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1442 {
1443     CPUState *env;
1444     int err = 0;
1445
1446     if (kvm_enabled())
1447         return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1448
1449     switch (type) {
1450     case GDB_BREAKPOINT_SW:
1451     case GDB_BREAKPOINT_HW:
1452         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1453             err = cpu_breakpoint_remove(env, addr, BP_GDB);
1454             if (err)
1455                 break;
1456         }
1457         return err;
1458 #ifndef CONFIG_USER_ONLY
1459     case GDB_WATCHPOINT_WRITE:
1460     case GDB_WATCHPOINT_READ:
1461     case GDB_WATCHPOINT_ACCESS:
1462         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1463             err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1464             if (err)
1465                 break;
1466         }
1467         return err;
1468 #endif
1469     default:
1470         return -ENOSYS;
1471     }
1472 }
1473
1474 static void gdb_breakpoint_remove_all(void)
1475 {
1476     CPUState *env;
1477
1478     if (kvm_enabled()) {
1479         kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1480         return;
1481     }
1482
1483     for (env = first_cpu; env != NULL; env = env->next_cpu) {
1484         cpu_breakpoint_remove_all(env, BP_GDB);
1485 #ifndef CONFIG_USER_ONLY
1486         cpu_watchpoint_remove_all(env, BP_GDB);
1487 #endif
1488     }
1489 }
1490
1491 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1492 {
1493     CPUState *env;
1494     const char *p;
1495     int ch, reg_size, type, res, thread;
1496     char buf[MAX_PACKET_LENGTH];
1497     uint8_t mem_buf[MAX_PACKET_LENGTH];
1498     uint8_t *registers;
1499     target_ulong addr, len;
1500
1501 #ifdef DEBUG_GDB
1502     printf("command='%s'\n", line_buf);
1503 #endif
1504     p = line_buf;
1505     ch = *p++;
1506     switch(ch) {
1507     case '?':
1508         /* TODO: Make this return the correct value for user-mode.  */
1509         snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1510                  s->c_cpu->cpu_index+1);
1511         put_packet(s, buf);
1512         /* Remove all the breakpoints when this query is issued,
1513          * because gdb is doing and initial connect and the state
1514          * should be cleaned up.
1515          */
1516         gdb_breakpoint_remove_all();
1517         break;
1518     case 'c':
1519         if (*p != '\0') {
1520             addr = strtoull(p, (char **)&p, 16);
1521 #if defined(TARGET_I386)
1522             s->c_cpu->eip = addr;
1523             kvm_load_registers(s->c_cpu);
1524 #elif defined (TARGET_PPC)
1525             s->c_cpu->nip = addr;
1526             kvm_load_registers(s->c_cpu);
1527 #elif defined (TARGET_SPARC)
1528             s->c_cpu->pc = addr;
1529             s->c_cpu->npc = addr + 4;
1530 #elif defined (TARGET_ARM)
1531             s->c_cpu->regs[15] = addr;
1532 #elif defined (TARGET_SH4)
1533             s->c_cpu->pc = addr;
1534 #elif defined (TARGET_MIPS)
1535             s->c_cpu->active_tc.PC = addr;
1536 #elif defined (TARGET_CRIS)
1537             s->c_cpu->pc = addr;
1538 #elif defined (TARGET_ALPHA)
1539             s->c_cpu->pc = addr;
1540 #endif
1541         }
1542         s->signal = 0;
1543         gdb_continue(s);
1544         return RS_IDLE;
1545     case 'C':
1546         s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1547         if (s->signal == -1)
1548             s->signal = 0;
1549         gdb_continue(s);
1550         return RS_IDLE;
1551     case 'k':
1552         /* Kill the target */
1553         fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1554         exit(0);
1555     case 'D':
1556         /* Detach packet */
1557         gdb_breakpoint_remove_all();
1558         gdb_continue(s);
1559         put_packet(s, "OK");
1560         break;
1561     case 's':
1562         if (*p != '\0') {
1563             addr = strtoull(p, (char **)&p, 16);
1564 #if defined(TARGET_I386)
1565             s->c_cpu->eip = addr;
1566             kvm_load_registers(s->c_cpu);
1567 #elif defined (TARGET_PPC)
1568             s->c_cpu->nip = addr;
1569             kvm_load_registers(s->c_cpu);
1570 #elif defined (TARGET_SPARC)
1571             s->c_cpu->pc = addr;
1572             s->c_cpu->npc = addr + 4;
1573 #elif defined (TARGET_ARM)
1574             s->c_cpu->regs[15] = addr;
1575 #elif defined (TARGET_SH4)
1576             s->c_cpu->pc = addr;
1577 #elif defined (TARGET_MIPS)
1578             s->c_cpu->active_tc.PC = addr;
1579 #elif defined (TARGET_CRIS)
1580             s->c_cpu->pc = addr;
1581 #elif defined (TARGET_ALPHA)
1582             s->c_cpu->pc = addr;
1583 #endif
1584         }
1585         cpu_single_step(s->c_cpu, sstep_flags);
1586         gdb_continue(s);
1587         return RS_IDLE;
1588     case 'F':
1589         {
1590             target_ulong ret;
1591             target_ulong err;
1592
1593             ret = strtoull(p, (char **)&p, 16);
1594             if (*p == ',') {
1595                 p++;
1596                 err = strtoull(p, (char **)&p, 16);
1597             } else {
1598                 err = 0;
1599             }
1600             if (*p == ',')
1601                 p++;
1602             type = *p;
1603             if (gdb_current_syscall_cb)
1604                 gdb_current_syscall_cb(s->c_cpu, ret, err);
1605             if (type == 'C') {
1606                 put_packet(s, "T02");
1607             } else {
1608                 gdb_continue(s);
1609             }
1610         }
1611         break;
1612     case 'g':
1613         kvm_save_registers(s->g_cpu);
1614         len = 0;
1615         for (addr = 0; addr < num_g_regs; addr++) {
1616             reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1617             len += reg_size;
1618         }
1619         memtohex(buf, mem_buf, len);
1620         put_packet(s, buf);
1621         break;
1622     case 'G':
1623         registers = mem_buf;
1624         len = strlen(p) / 2;
1625         hextomem((uint8_t *)registers, p, len);
1626         for (addr = 0; addr < num_g_regs && len > 0; addr++) {
1627             reg_size = gdb_write_register(s->g_cpu, registers, addr);
1628             len -= reg_size;
1629             registers += reg_size;
1630         }
1631         kvm_load_registers(s->g_cpu);
1632         put_packet(s, "OK");
1633         break;
1634     case 'm':
1635         addr = strtoull(p, (char **)&p, 16);
1636         if (*p == ',')
1637             p++;
1638         len = strtoull(p, NULL, 16);
1639         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
1640             put_packet (s, "E14");
1641         } else {
1642             memtohex(buf, mem_buf, len);
1643             put_packet(s, buf);
1644         }
1645         break;
1646     case 'M':
1647         addr = strtoull(p, (char **)&p, 16);
1648         if (*p == ',')
1649             p++;
1650         len = strtoull(p, (char **)&p, 16);
1651         if (*p == ':')
1652             p++;
1653         hextomem(mem_buf, p, len);
1654         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
1655             put_packet(s, "E14");
1656         else
1657             put_packet(s, "OK");
1658         break;
1659     case 'p':
1660         /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1661            This works, but can be very slow.  Anything new enough to
1662            understand XML also knows how to use this properly.  */
1663         if (!gdb_has_xml)
1664             goto unknown_command;
1665         addr = strtoull(p, (char **)&p, 16);
1666         reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
1667         if (reg_size) {
1668             memtohex(buf, mem_buf, reg_size);
1669             put_packet(s, buf);
1670         } else {
1671             put_packet(s, "E14");
1672         }
1673         break;
1674     case 'P':
1675         if (!gdb_has_xml)
1676             goto unknown_command;
1677         addr = strtoull(p, (char **)&p, 16);
1678         if (*p == '=')
1679             p++;
1680         reg_size = strlen(p) / 2;
1681         hextomem(mem_buf, p, reg_size);
1682         gdb_write_register(s->g_cpu, mem_buf, addr);
1683         put_packet(s, "OK");
1684         break;
1685     case 'Z':
1686     case 'z':
1687         type = strtoul(p, (char **)&p, 16);
1688         if (*p == ',')
1689             p++;
1690         addr = strtoull(p, (char **)&p, 16);
1691         if (*p == ',')
1692             p++;
1693         len = strtoull(p, (char **)&p, 16);
1694         if (ch == 'Z')
1695             res = gdb_breakpoint_insert(addr, len, type);
1696         else
1697             res = gdb_breakpoint_remove(addr, len, type);
1698         if (res >= 0)
1699              put_packet(s, "OK");
1700         else if (res == -ENOSYS)
1701             put_packet(s, "");
1702         else
1703             put_packet(s, "E22");
1704         break;
1705     case 'H':
1706         type = *p++;
1707         thread = strtoull(p, (char **)&p, 16);
1708         if (thread == -1 || thread == 0) {
1709             put_packet(s, "OK");
1710             break;
1711         }
1712         for (env = first_cpu; env != NULL; env = env->next_cpu)
1713             if (env->cpu_index + 1 == thread)
1714                 break;
1715         if (env == NULL) {
1716             put_packet(s, "E22");
1717             break;
1718         }
1719         switch (type) {
1720         case 'c':
1721             s->c_cpu = env;
1722             put_packet(s, "OK");
1723             break;
1724         case 'g':
1725             s->g_cpu = env;
1726             put_packet(s, "OK");
1727             break;
1728         default:
1729              put_packet(s, "E22");
1730              break;
1731         }
1732         break;
1733     case 'T':
1734         thread = strtoull(p, (char **)&p, 16);
1735 #ifndef CONFIG_USER_ONLY
1736         if (thread > 0 && thread < smp_cpus + 1)
1737 #else
1738         if (thread == 1)
1739 #endif
1740              put_packet(s, "OK");
1741         else
1742             put_packet(s, "E22");
1743         break;
1744     case 'q':
1745     case 'Q':
1746         /* parse any 'q' packets here */
1747         if (!strcmp(p,"qemu.sstepbits")) {
1748             /* Query Breakpoint bit definitions */
1749             snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1750                      SSTEP_ENABLE,
1751                      SSTEP_NOIRQ,
1752                      SSTEP_NOTIMER);
1753             put_packet(s, buf);
1754             break;
1755         } else if (strncmp(p,"qemu.sstep",10) == 0) {
1756             /* Display or change the sstep_flags */
1757             p += 10;
1758             if (*p != '=') {
1759                 /* Display current setting */
1760                 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
1761                 put_packet(s, buf);
1762                 break;
1763             }
1764             p++;
1765             type = strtoul(p, (char **)&p, 16);
1766             sstep_flags = type;
1767             put_packet(s, "OK");
1768             break;
1769         } else if (strcmp(p,"C") == 0) {
1770             /* "Current thread" remains vague in the spec, so always return
1771              *  the first CPU (gdb returns the first thread). */
1772             put_packet(s, "QC1");
1773             break;
1774         } else if (strcmp(p,"fThreadInfo") == 0) {
1775             s->query_cpu = first_cpu;
1776             goto report_cpuinfo;
1777         } else if (strcmp(p,"sThreadInfo") == 0) {
1778         report_cpuinfo:
1779             if (s->query_cpu) {
1780                 snprintf(buf, sizeof(buf), "m%x", s->query_cpu->cpu_index+1);
1781                 put_packet(s, buf);
1782                 s->query_cpu = s->query_cpu->next_cpu;
1783             } else
1784                 put_packet(s, "l");
1785             break;
1786         } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
1787             thread = strtoull(p+16, (char **)&p, 16);
1788             for (env = first_cpu; env != NULL; env = env->next_cpu)
1789                 if (env->cpu_index + 1 == thread) {
1790                     kvm_save_registers(env);
1791                     len = snprintf((char *)mem_buf, sizeof(mem_buf),
1792                                    "CPU#%d [%s]", env->cpu_index,
1793                                    env->halted ? "halted " : "running");
1794                     memtohex(buf, mem_buf, len);
1795                     put_packet(s, buf);
1796                     break;
1797                 }
1798             break;
1799         }
1800 #ifdef CONFIG_LINUX_USER
1801         else if (strncmp(p, "Offsets", 7) == 0) {
1802             TaskState *ts = s->c_cpu->opaque;
1803
1804             snprintf(buf, sizeof(buf),
1805                      "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1806                      ";Bss=" TARGET_ABI_FMT_lx,
1807                      ts->info->code_offset,
1808                      ts->info->data_offset,
1809                      ts->info->data_offset);
1810             put_packet(s, buf);
1811             break;
1812         }
1813 #endif
1814         if (strncmp(p, "Supported", 9) == 0) {
1815             snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
1816 #ifdef GDB_CORE_XML
1817             strcat(buf, ";qXfer:features:read+");
1818 #endif
1819             put_packet(s, buf);
1820             break;
1821         }
1822 #ifdef GDB_CORE_XML
1823         if (strncmp(p, "Xfer:features:read:", 19) == 0) {
1824             const char *xml;
1825             target_ulong total_len;
1826
1827             gdb_has_xml = 1;
1828             p += 19;
1829             xml = get_feature_xml(p, &p);
1830             if (!xml) {
1831                 snprintf(buf, sizeof(buf), "E00");
1832                 put_packet(s, buf);
1833                 break;
1834             }
1835
1836             if (*p == ':')
1837                 p++;
1838             addr = strtoul(p, (char **)&p, 16);
1839             if (*p == ',')
1840                 p++;
1841             len = strtoul(p, (char **)&p, 16);
1842
1843             total_len = strlen(xml);
1844             if (addr > total_len) {
1845                 snprintf(buf, sizeof(buf), "E00");
1846                 put_packet(s, buf);
1847                 break;
1848             }
1849             if (len > (MAX_PACKET_LENGTH - 5) / 2)
1850                 len = (MAX_PACKET_LENGTH - 5) / 2;
1851             if (len < total_len - addr) {
1852                 buf[0] = 'm';
1853                 len = memtox(buf + 1, xml + addr, len);
1854             } else {
1855                 buf[0] = 'l';
1856                 len = memtox(buf + 1, xml + addr, total_len - addr);
1857             }
1858             put_packet_binary(s, buf, len + 1);
1859             break;
1860         }
1861 #endif
1862         /* Unrecognised 'q' command.  */
1863         goto unknown_command;
1864
1865     default:
1866     unknown_command:
1867         /* put empty packet */
1868         buf[0] = '\0';
1869         put_packet(s, buf);
1870         break;
1871     }
1872     return RS_IDLE;
1873 }
1874
1875 void gdb_set_stop_cpu(CPUState *env)
1876 {
1877     gdbserver_state->c_cpu = env;
1878     gdbserver_state->g_cpu = env;
1879 }
1880
1881 #ifndef CONFIG_USER_ONLY
1882 static void gdb_vm_stopped(void *opaque, int reason)
1883 {
1884     GDBState *s = gdbserver_state;
1885     CPUState *env = s->c_cpu;
1886     char buf[256];
1887     const char *type;
1888     int ret;
1889
1890     if (s->state == RS_SYSCALL)
1891         return;
1892
1893     /* disable single step if it was enable */
1894     cpu_single_step(env, 0);
1895
1896     if (reason == EXCP_DEBUG) {
1897         if (env->watchpoint_hit) {
1898             switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
1899             case BP_MEM_READ:
1900                 type = "r";
1901                 break;
1902             case BP_MEM_ACCESS:
1903                 type = "a";
1904                 break;
1905             default:
1906                 type = "";
1907                 break;
1908             }
1909             snprintf(buf, sizeof(buf),
1910                      "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
1911                      GDB_SIGNAL_TRAP, env->cpu_index+1, type,
1912                      env->watchpoint_hit->vaddr);
1913             put_packet(s, buf);
1914             env->watchpoint_hit = NULL;
1915             return;
1916         }
1917         tb_flush(env);
1918         ret = GDB_SIGNAL_TRAP;
1919     } else if (reason == EXCP_INTERRUPT) {
1920         ret = GDB_SIGNAL_INT;
1921     } else {
1922         ret = 0;
1923     }
1924     snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, env->cpu_index+1);
1925     put_packet(s, buf);
1926 }
1927 #endif
1928
1929 /* Send a gdb syscall request.
1930    This accepts limited printf-style format specifiers, specifically:
1931     %x  - target_ulong argument printed in hex.
1932     %lx - 64-bit argument printed in hex.
1933     %s  - string pointer (target_ulong) and length (int) pair.  */
1934 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
1935 {
1936     va_list va;
1937     char buf[256];
1938     char *p;
1939     target_ulong addr;
1940     uint64_t i64;
1941     GDBState *s;
1942
1943     s = gdbserver_state;
1944     if (!s)
1945         return;
1946     gdb_current_syscall_cb = cb;
1947     s->state = RS_SYSCALL;
1948 #ifndef CONFIG_USER_ONLY
1949     vm_stop(EXCP_DEBUG);
1950 #endif
1951     s->state = RS_IDLE;
1952     va_start(va, fmt);
1953     p = buf;
1954     *(p++) = 'F';
1955     while (*fmt) {
1956         if (*fmt == '%') {
1957             fmt++;
1958             switch (*fmt++) {
1959             case 'x':
1960                 addr = va_arg(va, target_ulong);
1961                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
1962                 break;
1963             case 'l':
1964                 if (*(fmt++) != 'x')
1965                     goto bad_format;
1966                 i64 = va_arg(va, uint64_t);
1967                 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
1968                 break;
1969             case 's':
1970                 addr = va_arg(va, target_ulong);
1971                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
1972                               addr, va_arg(va, int));
1973                 break;
1974             default:
1975             bad_format:
1976                 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1977                         fmt - 1);
1978                 break;
1979             }
1980         } else {
1981             *(p++) = *(fmt++);
1982         }
1983     }
1984     *p = 0;
1985     va_end(va);
1986     put_packet(s, buf);
1987 #ifdef CONFIG_USER_ONLY
1988     gdb_handlesig(s->c_cpu, 0);
1989 #else
1990     cpu_interrupt(s->c_cpu, CPU_INTERRUPT_EXIT);
1991 #endif
1992 }
1993
1994 static void gdb_read_byte(GDBState *s, int ch)
1995 {
1996     int i, csum;
1997     uint8_t reply;
1998
1999 #ifndef CONFIG_USER_ONLY
2000     if (s->last_packet_len) {
2001         /* Waiting for a response to the last packet.  If we see the start
2002            of a new command then abandon the previous response.  */
2003         if (ch == '-') {
2004 #ifdef DEBUG_GDB
2005             printf("Got NACK, retransmitting\n");
2006 #endif
2007             put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2008         }
2009 #ifdef DEBUG_GDB
2010         else if (ch == '+')
2011             printf("Got ACK\n");
2012         else
2013             printf("Got '%c' when expecting ACK/NACK\n", ch);
2014 #endif
2015         if (ch == '+' || ch == '$')
2016             s->last_packet_len = 0;
2017         if (ch != '$')
2018             return;
2019     }
2020     if (vm_running) {
2021         /* when the CPU is running, we cannot do anything except stop
2022            it when receiving a char */
2023         vm_stop(EXCP_INTERRUPT);
2024     } else
2025 #endif
2026     {
2027         switch(s->state) {
2028         case RS_IDLE:
2029             if (ch == '$') {
2030                 s->line_buf_index = 0;
2031                 s->state = RS_GETLINE;
2032             }
2033             break;
2034         case RS_GETLINE:
2035             if (ch == '#') {
2036             s->state = RS_CHKSUM1;
2037             } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2038                 s->state = RS_IDLE;
2039             } else {
2040             s->line_buf[s->line_buf_index++] = ch;
2041             }
2042             break;
2043         case RS_CHKSUM1:
2044             s->line_buf[s->line_buf_index] = '\0';
2045             s->line_csum = fromhex(ch) << 4;
2046             s->state = RS_CHKSUM2;
2047             break;
2048         case RS_CHKSUM2:
2049             s->line_csum |= fromhex(ch);
2050             csum = 0;
2051             for(i = 0; i < s->line_buf_index; i++) {
2052                 csum += s->line_buf[i];
2053             }
2054             if (s->line_csum != (csum & 0xff)) {
2055                 reply = '-';
2056                 put_buffer(s, &reply, 1);
2057                 s->state = RS_IDLE;
2058             } else {
2059                 reply = '+';
2060                 put_buffer(s, &reply, 1);
2061                 s->state = gdb_handle_packet(s, s->line_buf);
2062             }
2063             break;
2064         default:
2065             abort();
2066         }
2067     }
2068 }
2069
2070 #ifdef CONFIG_USER_ONLY
2071 int
2072 gdb_queuesig (void)
2073 {
2074     GDBState *s;
2075
2076     s = gdbserver_state;
2077
2078     if (gdbserver_fd < 0 || s->fd < 0)
2079         return 0;
2080     else
2081         return 1;
2082 }
2083
2084 int
2085 gdb_handlesig (CPUState *env, int sig)
2086 {
2087   GDBState *s;
2088   char buf[256];
2089   int n;
2090
2091   s = gdbserver_state;
2092   if (gdbserver_fd < 0 || s->fd < 0)
2093     return sig;
2094
2095   /* disable single step if it was enabled */
2096   cpu_single_step(env, 0);
2097   tb_flush(env);
2098
2099   if (sig != 0)
2100     {
2101       snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2102       put_packet(s, buf);
2103     }
2104   /* put_packet() might have detected that the peer terminated the
2105      connection.  */
2106   if (s->fd < 0)
2107       return sig;
2108
2109   sig = 0;
2110   s->state = RS_IDLE;
2111   s->running_state = 0;
2112   while (s->running_state == 0) {
2113       n = read (s->fd, buf, 256);
2114       if (n > 0)
2115         {
2116           int i;
2117
2118           for (i = 0; i < n; i++)
2119             gdb_read_byte (s, buf[i]);
2120         }
2121       else if (n == 0 || errno != EAGAIN)
2122         {
2123           /* XXX: Connection closed.  Should probably wait for annother
2124              connection before continuing.  */
2125           return sig;
2126         }
2127   }
2128   sig = s->signal;
2129   s->signal = 0;
2130   return sig;
2131 }
2132
2133 /* Tell the remote gdb that the process has exited.  */
2134 void gdb_exit(CPUState *env, int code)
2135 {
2136   GDBState *s;
2137   char buf[4];
2138
2139   s = gdbserver_state;
2140   if (gdbserver_fd < 0 || s->fd < 0)
2141     return;
2142
2143   snprintf(buf, sizeof(buf), "W%02x", code);
2144   put_packet(s, buf);
2145 }
2146
2147 /* Tell the remote gdb that the process has exited due to SIG.  */
2148 void gdb_signalled(CPUState *env, int sig)
2149 {
2150   GDBState *s;
2151   char buf[4];
2152
2153   s = gdbserver_state;
2154   if (gdbserver_fd < 0 || s->fd < 0)
2155     return;
2156
2157   snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2158   put_packet(s, buf);
2159 }
2160
2161 static void gdb_accept(void)
2162 {
2163     GDBState *s;
2164     struct sockaddr_in sockaddr;
2165     socklen_t len;
2166     int val, fd;
2167
2168     for(;;) {
2169         len = sizeof(sockaddr);
2170         fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2171         if (fd < 0 && errno != EINTR) {
2172             perror("accept");
2173             return;
2174         } else if (fd >= 0) {
2175             break;
2176         }
2177     }
2178
2179     /* set short latency */
2180     val = 1;
2181     setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2182
2183     s = qemu_mallocz(sizeof(GDBState));
2184     if (!s) {
2185         errno = ENOMEM;
2186         perror("accept");
2187         return;
2188     }
2189
2190     memset (s, 0, sizeof (GDBState));
2191     s->c_cpu = first_cpu;
2192     s->g_cpu = first_cpu;
2193     s->fd = fd;
2194     gdb_has_xml = 0;
2195
2196     gdbserver_state = s;
2197
2198     fcntl(fd, F_SETFL, O_NONBLOCK);
2199 }
2200
2201 static int gdbserver_open(int port)
2202 {
2203     struct sockaddr_in sockaddr;
2204     int fd, val, ret;
2205
2206     fd = socket(PF_INET, SOCK_STREAM, 0);
2207     if (fd < 0) {
2208         perror("socket");
2209         return -1;
2210     }
2211
2212     /* allow fast reuse */
2213     val = 1;
2214     setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2215
2216     sockaddr.sin_family = AF_INET;
2217     sockaddr.sin_port = htons(port);
2218     sockaddr.sin_addr.s_addr = 0;
2219     ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2220     if (ret < 0) {
2221         perror("bind");
2222         return -1;
2223     }
2224     ret = listen(fd, 0);
2225     if (ret < 0) {
2226         perror("listen");
2227         return -1;
2228     }
2229     return fd;
2230 }
2231
2232 int gdbserver_start(int port)
2233 {
2234     gdbserver_fd = gdbserver_open(port);
2235     if (gdbserver_fd < 0)
2236         return -1;
2237     /* accept connections */
2238     gdb_accept();
2239     return 0;
2240 }
2241
2242 /* Disable gdb stub for child processes.  */
2243 void gdbserver_fork(CPUState *env)
2244 {
2245     GDBState *s = gdbserver_state;
2246     if (gdbserver_fd < 0 || s->fd < 0)
2247       return;
2248     close(s->fd);
2249     s->fd = -1;
2250     cpu_breakpoint_remove_all(env, BP_GDB);
2251     cpu_watchpoint_remove_all(env, BP_GDB);
2252 }
2253 #else
2254 static int gdb_chr_can_receive(void *opaque)
2255 {
2256   /* We can handle an arbitrarily large amount of data.
2257    Pick the maximum packet size, which is as good as anything.  */
2258   return MAX_PACKET_LENGTH;
2259 }
2260
2261 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2262 {
2263     int i;
2264
2265     for (i = 0; i < size; i++) {
2266         gdb_read_byte(gdbserver_state, buf[i]);
2267     }
2268 }
2269
2270 static void gdb_chr_event(void *opaque, int event)
2271 {
2272     switch (event) {
2273     case CHR_EVENT_RESET:
2274         vm_stop(EXCP_INTERRUPT);
2275         gdb_has_xml = 0;
2276         break;
2277     default:
2278         break;
2279     }
2280 }
2281
2282 int gdbserver_start(const char *port)
2283 {
2284     GDBState *s;
2285     char gdbstub_port_name[128];
2286     int port_num;
2287     char *p;
2288     CharDriverState *chr;
2289
2290     if (!port || !*port)
2291       return -1;
2292
2293     port_num = strtol(port, &p, 10);
2294     if (*p == 0) {
2295         /* A numeric value is interpreted as a port number.  */
2296         snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
2297                  "tcp::%d,nowait,nodelay,server", port_num);
2298         port = gdbstub_port_name;
2299     }
2300
2301     chr = qemu_chr_open("gdb", port);
2302     if (!chr)
2303         return -1;
2304
2305     s = qemu_mallocz(sizeof(GDBState));
2306     if (!s) {
2307         return -1;
2308     }
2309     s->c_cpu = first_cpu;
2310     s->g_cpu = first_cpu;
2311     s->chr = chr;
2312     gdbserver_state = s;
2313     qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2314                           gdb_chr_event, NULL);
2315     qemu_add_vm_stop_handler(gdb_vm_stopped, NULL);
2316     return 0;
2317 }
2318 #endif