hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "hw.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "audio/audio.h"
  21 #include "i2c.h"
  22
  23 #define MP_ETH_BASE             0x80008000
  24 #define MP_ETH_SIZE             0x00001000
  25
  26 #define MP_UART1_BASE           0x8000C840
  27 #define MP_UART2_BASE           0x8000C940
  28
  29 #define MP_FLASHCFG_BASE        0x90006000
  30 #define MP_FLASHCFG_SIZE        0x00001000
  31
  32 #define MP_AUDIO_BASE           0x90007000
  33 #define MP_AUDIO_SIZE           0x00001000
  34
  35 #define MP_PIC_BASE             0x90008000
  36 #define MP_PIC_SIZE             0x00001000
  37
  38 #define MP_PIT_BASE             0x90009000
  39 #define MP_PIT_SIZE             0x00001000
  40
  41 #define MP_LCD_BASE             0x9000c000
  42 #define MP_LCD_SIZE             0x00001000
  43
  44 #define MP_SRAM_BASE            0xC0000000
  45 #define MP_SRAM_SIZE            0x00020000
  46
  47 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  48 #define MP_FLASH_SIZE_MAX       32*1024*1024
  49
  50 #define MP_TIMER1_IRQ           4
  51 /* ... */
  52 #define MP_TIMER4_IRQ           7
  53 #define MP_EHCI_IRQ             8
  54 #define MP_ETH_IRQ              9
  55 #define MP_UART1_IRQ            11
  56 #define MP_UART2_IRQ            11
  57 #define MP_GPIO_IRQ             12
  58 #define MP_RTC_IRQ              28
  59 #define MP_AUDIO_IRQ            30
  60
  61 static uint32_t gpio_in_state = 0xffffffff;
  62 static uint32_t gpio_isr;
  63 static uint32_t gpio_out_state;
  64 static ram_addr_t sram_off;
  65
  66 /* Address conversion helpers */
  67 static void *target2host_addr(uint32_t addr)
  68 {
  69     if (addr < MP_SRAM_BASE) {
  70         if (addr >= MP_RAM_DEFAULT_SIZE)
  71             return NULL;
  72         return (void *)(phys_ram_base + addr);
  73     } else {
  74         if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
  75             return NULL;
  76         return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE);
  77     }
  78 }
  79
  80 static uint32_t host2target_addr(void *addr)
  81 {
  82     if (addr < ((void *)phys_ram_base) + sram_off)
  83         return (unsigned long)addr - (unsigned long)phys_ram_base;
  84     else
  85         return (unsigned long)addr - (unsigned long)phys_ram_base -
  86             sram_off + MP_SRAM_BASE;
  87 }
  88
  89
  90 typedef enum i2c_state {
  91     STOPPED = 0,
  92     INITIALIZING,
  93     SENDING_BIT7,
  94     SENDING_BIT6,
  95     SENDING_BIT5,
  96     SENDING_BIT4,
  97     SENDING_BIT3,
  98     SENDING_BIT2,
  99     SENDING_BIT1,
 100     SENDING_BIT0,
 101     WAITING_FOR_ACK,
 102     RECEIVING_BIT7,
 103     RECEIVING_BIT6,
 104     RECEIVING_BIT5,
 105     RECEIVING_BIT4,
 106     RECEIVING_BIT3,
 107     RECEIVING_BIT2,
 108     RECEIVING_BIT1,
 109     RECEIVING_BIT0,
 110     SENDING_ACK
 111 } i2c_state;
 112
 113 typedef struct i2c_interface {
 114     i2c_bus *bus;
 115     i2c_state state;
 116     int last_data;
 117     int last_clock;
 118     uint8_t buffer;
 119     int current_addr;
 120 } i2c_interface;
 121
 122 static void i2c_enter_stop(i2c_interface *i2c)
 123 {
 124     if (i2c->current_addr >= 0)
 125         i2c_end_transfer(i2c->bus);
 126     i2c->current_addr = -1;
 127     i2c->state = STOPPED;
 128 }
 129
 130 static void i2c_state_update(i2c_interface *i2c, int data, int clock)
 131 {
 132     if (!i2c)
 133         return;
 134
 135     switch (i2c->state) {
 136     case STOPPED:
 137         if (data == 0 && i2c->last_data == 1 && clock == 1)
 138             i2c->state = INITIALIZING;
 139         break;
 140
 141     case INITIALIZING:
 142         if (clock == 0 && i2c->last_clock == 1 && data == 0)
 143             i2c->state = SENDING_BIT7;
 144         else
 145             i2c_enter_stop(i2c);
 146         break;
 147
 148     case SENDING_BIT7 ... SENDING_BIT0:
 149         if (clock == 0 && i2c->last_clock == 1) {
 150             i2c->buffer = (i2c->buffer << 1) | data;
 151             i2c->state++; /* will end up in WAITING_FOR_ACK */
 152         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 153             i2c_enter_stop(i2c);
 154         break;
 155
 156     case WAITING_FOR_ACK:
 157         if (clock == 0 && i2c->last_clock == 1) {
 158             if (i2c->current_addr < 0) {
 159                 i2c->current_addr = i2c->buffer;
 160                 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
 161                                    i2c->buffer & 1);
 162             } else
 163                 i2c_send(i2c->bus, i2c->buffer);
 164             if (i2c->current_addr & 1) {
 165                 i2c->state = RECEIVING_BIT7;
 166                 i2c->buffer = i2c_recv(i2c->bus);
 167             } else
 168                 i2c->state = SENDING_BIT7;
 169         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 170             i2c_enter_stop(i2c);
 171         break;
 172
 173     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 174         if (clock == 0 && i2c->last_clock == 1) {
 175             i2c->state++; /* will end up in SENDING_ACK */
 176             i2c->buffer <<= 1;
 177         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 178             i2c_enter_stop(i2c);
 179         break;
 180
 181     case SENDING_ACK:
 182         if (clock == 0 && i2c->last_clock == 1) {
 183             i2c->state = RECEIVING_BIT7;
 184             if (data == 0)
 185                 i2c->buffer = i2c_recv(i2c->bus);
 186             else
 187                 i2c_nack(i2c->bus);
 188         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 189             i2c_enter_stop(i2c);
 190         break;
 191     }
 192
 193     i2c->last_data = data;
 194     i2c->last_clock = clock;
 195 }
 196
 197 static int i2c_get_data(i2c_interface *i2c)
 198 {
 199     if (!i2c)
 200         return 0;
 201
 202     switch (i2c->state) {
 203     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 204         return (i2c->buffer >> 7);
 205
 206     case WAITING_FOR_ACK:
 207     default:
 208         return 0;
 209     }
 210 }
 211
 212 static i2c_interface *mixer_i2c;
 213
 214 #ifdef HAS_AUDIO
 215
 216 /* Audio register offsets */
 217 #define MP_AUDIO_PLAYBACK_MODE  0x00
 218 #define MP_AUDIO_CLOCK_DIV      0x18
 219 #define MP_AUDIO_IRQ_STATUS     0x20
 220 #define MP_AUDIO_IRQ_ENABLE     0x24
 221 #define MP_AUDIO_TX_START_LO    0x28
 222 #define MP_AUDIO_TX_THRESHOLD   0x2C
 223 #define MP_AUDIO_TX_STATUS      0x38
 224 #define MP_AUDIO_TX_START_HI    0x40
 225
 226 /* Status register and IRQ enable bits */
 227 #define MP_AUDIO_TX_HALF        (1 << 6)
 228 #define MP_AUDIO_TX_FULL        (1 << 7)
 229
 230 /* Playback mode bits */
 231 #define MP_AUDIO_16BIT_SAMPLE   (1 << 0)
 232 #define MP_AUDIO_PLAYBACK_EN    (1 << 7)
 233 #define MP_AUDIO_CLOCK_24MHZ    (1 << 9)
 234 #define MP_AUDIO_MONO           (1 << 14)
 235
 236 /* Wolfson 8750 I2C address */
 237 #define MP_WM_ADDR              0x34
 238
 239 static const char audio_name[] = "mv88w8618";
 240
 241 typedef struct musicpal_audio_state {
 242     qemu_irq irq;
 243     uint32_t playback_mode;
 244     uint32_t status;
 245     uint32_t irq_enable;
 246     unsigned long phys_buf;
 247     int8_t *target_buffer;
 248     unsigned int threshold;
 249     unsigned int play_pos;
 250     unsigned int last_free;
 251     uint32_t clock_div;
 252     i2c_slave *wm;
 253 } musicpal_audio_state;
 254
 255 static void audio_callback(void *opaque, int free_out, int free_in)
 256 {
 257     musicpal_audio_state *s = opaque;
 258     int16_t *codec_buffer;
 259     int8_t *mem_buffer;
 260     int pos, block_size;
 261
 262     if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
 263         return;
 264
 265     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
 266         free_out <<= 1;
 267
 268     if (!(s->playback_mode & MP_AUDIO_MONO))
 269         free_out <<= 1;
 270
 271     block_size = s->threshold/2;
 272     if (free_out - s->last_free < block_size)
 273         return;
 274
 275     mem_buffer = s->target_buffer + s->play_pos;
 276     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
 277         if (s->playback_mode & MP_AUDIO_MONO) {
 278             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 279             for (pos = 0; pos < block_size; pos += 2) {
 280                 *codec_buffer++ = *(int16_t *)mem_buffer;
 281                 *codec_buffer++ = *(int16_t *)mem_buffer;
 282                 mem_buffer += 2;
 283             }
 284         } else
 285             memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
 286                    (uint32_t *)mem_buffer, block_size);
 287     } else {
 288         if (s->playback_mode & MP_AUDIO_MONO) {
 289             codec_buffer = wm8750_dac_buffer(s->wm, block_size);
 290             for (pos = 0; pos < block_size; pos++) {
 291                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
 292                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 293             }
 294         } else {
 295             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 296             for (pos = 0; pos < block_size; pos += 2) {
 297                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 298                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 299             }
 300         }
 301     }
 302     wm8750_dac_commit(s->wm);
 303
 304     s->last_free = free_out - block_size;
 305
 306     if (s->play_pos == 0) {
 307         s->status |= MP_AUDIO_TX_HALF;
 308         s->play_pos = block_size;
 309     } else {
 310         s->status |= MP_AUDIO_TX_FULL;
 311         s->play_pos = 0;
 312     }
 313
 314     if (s->status & s->irq_enable)
 315         qemu_irq_raise(s->irq);
 316 }
 317
 318 static void musicpal_audio_clock_update(musicpal_audio_state *s)
 319 {
 320     int rate;
 321
 322     if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
 323         rate = 24576000 / 64; /* 24.576MHz */
 324     else
 325         rate = 11289600 / 64; /* 11.2896MHz */
 326
 327     rate /= ((s->clock_div >> 8) & 0xff) + 1;
 328
 329     wm8750_set_bclk_in(s->wm, rate);
 330 }
 331
 332 static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
 333 {
 334     musicpal_audio_state *s = opaque;
 335
 336     switch (offset) {
 337     case MP_AUDIO_PLAYBACK_MODE:
 338         return s->playback_mode;
 339
 340     case MP_AUDIO_CLOCK_DIV:
 341         return s->clock_div;
 342
 343     case MP_AUDIO_IRQ_STATUS:
 344         return s->status;
 345
 346     case MP_AUDIO_IRQ_ENABLE:
 347         return s->irq_enable;
 348
 349     case MP_AUDIO_TX_STATUS:
 350         return s->play_pos >> 2;
 351
 352     default:
 353         return 0;
 354     }
 355 }
 356
 357 static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
 358                                  uint32_t value)
 359 {
 360     musicpal_audio_state *s = opaque;
 361
 362     switch (offset) {
 363     case MP_AUDIO_PLAYBACK_MODE:
 364         if (value & MP_AUDIO_PLAYBACK_EN &&
 365             !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
 366             s->status = 0;
 367             s->last_free = 0;
 368             s->play_pos = 0;
 369         }
 370         s->playback_mode = value;
 371         musicpal_audio_clock_update(s);
 372         break;
 373
 374     case MP_AUDIO_CLOCK_DIV:
 375         s->clock_div = value;
 376         s->last_free = 0;
 377         s->play_pos = 0;
 378         musicpal_audio_clock_update(s);
 379         break;
 380
 381     case MP_AUDIO_IRQ_STATUS:
 382         s->status &= ~value;
 383         break;
 384
 385     case MP_AUDIO_IRQ_ENABLE:
 386         s->irq_enable = value;
 387         if (s->status & s->irq_enable)
 388             qemu_irq_raise(s->irq);
 389         break;
 390
 391     case MP_AUDIO_TX_START_LO:
 392         s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
 393         s->target_buffer = target2host_addr(s->phys_buf);
 394         s->play_pos = 0;
 395         s->last_free = 0;
 396         break;
 397
 398     case MP_AUDIO_TX_THRESHOLD:
 399         s->threshold = (value + 1) * 4;
 400         break;
 401
 402     case MP_AUDIO_TX_START_HI:
 403         s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
 404         s->target_buffer = target2host_addr(s->phys_buf);
 405         s->play_pos = 0;
 406         s->last_free = 0;
 407         break;
 408     }
 409 }
 410
 411 static void musicpal_audio_reset(void *opaque)
 412 {
 413     musicpal_audio_state *s = opaque;
 414
 415     s->playback_mode = 0;
 416     s->status = 0;
 417     s->irq_enable = 0;
 418 }
 419
 420 static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
 421     musicpal_audio_read,
 422     musicpal_audio_read,
 423     musicpal_audio_read
 424 };
 425
 426 static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
 427     musicpal_audio_write,
 428     musicpal_audio_write,
 429     musicpal_audio_write
 430 };
 431
 432 static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
 433 {
 434     AudioState *audio;
 435     musicpal_audio_state *s;
 436     i2c_interface *i2c;
 437     int iomemtype;
 438
 439     audio = AUD_init();
 440     if (!audio) {
 441         AUD_log(audio_name, "No audio state\n");
 442         return NULL;
 443     }
 444
 445     s = qemu_mallocz(sizeof(musicpal_audio_state));
 446     if (!s)
 447         return NULL;
 448     s->irq = irq;
 449
 450     i2c = qemu_mallocz(sizeof(i2c_interface));
 451     if (!i2c)
 452         return NULL;
 453     i2c->bus = i2c_init_bus();
 454     i2c->current_addr = -1;
 455
 456     s->wm = wm8750_init(i2c->bus, audio);
 457     if (!s->wm)
 458         return NULL;
 459     i2c_set_slave_address(s->wm, MP_WM_ADDR);
 460     wm8750_data_req_set(s->wm, audio_callback, s);
 461
 462     iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
 463                        musicpal_audio_writefn, s);
 464     cpu_register_physical_memory(base, MP_AUDIO_SIZE, iomemtype);
 465
 466     qemu_register_reset(musicpal_audio_reset, s);
 467
 468     return i2c;
 469 }
 470 #else  /* !HAS_AUDIO */
 471 static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
 472 {
 473     return NULL;
 474 }
 475 #endif /* !HAS_AUDIO */
 476
 477 /* Ethernet register offsets */
 478 #define MP_ETH_SMIR             0x010
 479 #define MP_ETH_PCXR             0x408
 480 #define MP_ETH_SDCMR            0x448
 481 #define MP_ETH_ICR              0x450
 482 #define MP_ETH_IMR              0x458
 483 #define MP_ETH_FRDP0            0x480
 484 #define MP_ETH_FRDP1            0x484
 485 #define MP_ETH_FRDP2            0x488
 486 #define MP_ETH_FRDP3            0x48C
 487 #define MP_ETH_CRDP0            0x4A0
 488 #define MP_ETH_CRDP1            0x4A4
 489 #define MP_ETH_CRDP2            0x4A8
 490 #define MP_ETH_CRDP3            0x4AC
 491 #define MP_ETH_CTDP0            0x4E0
 492 #define MP_ETH_CTDP1            0x4E4
 493 #define MP_ETH_CTDP2            0x4E8
 494 #define MP_ETH_CTDP3            0x4EC
 495
 496 /* MII PHY access */
 497 #define MP_ETH_SMIR_DATA        0x0000FFFF
 498 #define MP_ETH_SMIR_ADDR        0x03FF0000
 499 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 500 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 501
 502 /* PHY registers */
 503 #define MP_ETH_PHY1_BMSR        0x00210000
 504 #define MP_ETH_PHY1_PHYSID1     0x00410000
 505 #define MP_ETH_PHY1_PHYSID2     0x00610000
 506
 507 #define MP_PHY_BMSR_LINK        0x0004
 508 #define MP_PHY_BMSR_AUTONEG     0x0008
 509
 510 #define MP_PHY_88E3015          0x01410E20
 511
 512 /* TX descriptor status */
 513 #define MP_ETH_TX_OWN           (1 << 31)
 514
 515 /* RX descriptor status */
 516 #define MP_ETH_RX_OWN           (1 << 31)
 517
 518 /* Interrupt cause/mask bits */
 519 #define MP_ETH_IRQ_RX_BIT       0
 520 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 521 #define MP_ETH_IRQ_TXHI_BIT     2
 522 #define MP_ETH_IRQ_TXLO_BIT     3
 523
 524 /* Port config bits */
 525 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 526
 527 /* SDMA command bits */
 528 #define MP_ETH_CMD_TXHI         (1 << 23)
 529 #define MP_ETH_CMD_TXLO         (1 << 22)
 530
 531 typedef struct mv88w8618_tx_desc {
 532     uint32_t cmdstat;
 533     uint16_t res;
 534     uint16_t bytes;
 535     uint32_t buffer;
 536     uint32_t next;
 537 } mv88w8618_tx_desc;
 538
 539 typedef struct mv88w8618_rx_desc {
 540     uint32_t cmdstat;
 541     uint16_t bytes;
 542     uint16_t buffer_size;
 543     uint32_t buffer;
 544     uint32_t next;
 545 } mv88w8618_rx_desc;
 546
 547 typedef struct mv88w8618_eth_state {
 548     qemu_irq irq;
 549     uint32_t smir;
 550     uint32_t icr;
 551     uint32_t imr;
 552     int vlan_header;
 553     mv88w8618_tx_desc *tx_queue[2];
 554     mv88w8618_rx_desc *rx_queue[4];
 555     mv88w8618_rx_desc *frx_queue[4];
 556     mv88w8618_rx_desc *cur_rx[4];
 557     VLANClientState *vc;
 558 } mv88w8618_eth_state;
 559
 560 static int eth_can_receive(void *opaque)
 561 {
 562     return 1;
 563 }
 564
 565 static void eth_receive(void *opaque, const uint8_t *buf, int size)
 566 {
 567     mv88w8618_eth_state *s = opaque;
 568     mv88w8618_rx_desc *desc;
 569     int i;
 570
 571     for (i = 0; i < 4; i++) {
 572         desc = s->cur_rx[i];
 573         if (!desc)
 574             continue;
 575         do {
 576             if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
 577                 le16_to_cpu(desc->buffer_size) >= size) {
 578                 memcpy(target2host_addr(le32_to_cpu(desc->buffer) +
 579                                         s->vlan_header),
 580                        buf, size);
 581                 desc->bytes = cpu_to_le16(size + s->vlan_header);
 582                 desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN);
 583                 s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next));
 584
 585                 s->icr |= MP_ETH_IRQ_RX;
 586                 if (s->icr & s->imr)
 587                     qemu_irq_raise(s->irq);
 588                 return;
 589             }
 590             desc = target2host_addr(le32_to_cpu(desc->next));
 591         } while (desc != s->rx_queue[i]);
 592     }
 593 }
 594
 595 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 596 {
 597     mv88w8618_tx_desc *desc = s->tx_queue[queue_index];
 598
 599     do {
 600         if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
 601             qemu_send_packet(s->vc,
 602                              target2host_addr(le32_to_cpu(desc->buffer)),
 603                              le16_to_cpu(desc->bytes));
 604             desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN);
 605             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 606         }
 607         desc = target2host_addr(le32_to_cpu(desc->next));
 608     } while (desc != s->tx_queue[queue_index]);
 609 }
 610
 611 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 612 {
 613     mv88w8618_eth_state *s = opaque;
 614
 615     switch (offset) {
 616     case MP_ETH_SMIR:
 617         if (s->smir & MP_ETH_SMIR_OPCODE) {
 618             switch (s->smir & MP_ETH_SMIR_ADDR) {
 619             case MP_ETH_PHY1_BMSR:
 620                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 621                        MP_ETH_SMIR_RDVALID;
 622             case MP_ETH_PHY1_PHYSID1:
 623                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 624             case MP_ETH_PHY1_PHYSID2:
 625                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 626             default:
 627                 return MP_ETH_SMIR_RDVALID;
 628             }
 629         }
 630         return 0;
 631
 632     case MP_ETH_ICR:
 633         return s->icr;
 634
 635     case MP_ETH_IMR:
 636         return s->imr;
 637
 638     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 639         return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]);
 640
 641     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 642         return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]);
 643
 644     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 645         return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]);
 646
 647     default:
 648         return 0;
 649     }
 650 }
 651
 652 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 653                                 uint32_t value)
 654 {
 655     mv88w8618_eth_state *s = opaque;
 656
 657     switch (offset) {
 658     case MP_ETH_SMIR:
 659         s->smir = value;
 660         break;
 661
 662     case MP_ETH_PCXR:
 663         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 664         break;
 665
 666     case MP_ETH_SDCMR:
 667         if (value & MP_ETH_CMD_TXHI)
 668             eth_send(s, 1);
 669         if (value & MP_ETH_CMD_TXLO)
 670             eth_send(s, 0);
 671         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 672             qemu_irq_raise(s->irq);
 673         break;
 674
 675     case MP_ETH_ICR:
 676         s->icr &= value;
 677         break;
 678
 679     case MP_ETH_IMR:
 680         s->imr = value;
 681         if (s->icr & s->imr)
 682             qemu_irq_raise(s->irq);
 683         break;
 684
 685     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 686         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
 687         break;
 688
 689     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 690         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 691             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
 692         break;
 693
 694     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 695         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
 696         break;
 697     }
 698 }
 699
 700 static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
 701     mv88w8618_eth_read,
 702     mv88w8618_eth_read,
 703     mv88w8618_eth_read
 704 };
 705
 706 static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
 707     mv88w8618_eth_write,
 708     mv88w8618_eth_write,
 709     mv88w8618_eth_write
 710 };
 711
 712 static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 713 {
 714     mv88w8618_eth_state *s;
 715     int iomemtype;
 716
 717     qemu_check_nic_model(nd, "mv88w8618");
 718
 719     s = qemu_mallocz(sizeof(mv88w8618_eth_state));
 720     if (!s)
 721         return;
 722     s->irq = irq;
 723     s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
 724                                  eth_receive, eth_can_receive, s);
 725     iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
 726                                        mv88w8618_eth_writefn, s);
 727     cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
 728 }
 729
 730 /* LCD register offsets */
 731 #define MP_LCD_IRQCTRL          0x180
 732 #define MP_LCD_IRQSTAT          0x184
 733 #define MP_LCD_SPICTRL          0x1ac
 734 #define MP_LCD_INST             0x1bc
 735 #define MP_LCD_DATA             0x1c0
 736
 737 /* Mode magics */
 738 #define MP_LCD_SPI_DATA         0x00100011
 739 #define MP_LCD_SPI_CMD          0x00104011
 740 #define MP_LCD_SPI_INVALID      0x00000000
 741
 742 /* Commmands */
 743 #define MP_LCD_INST_SETPAGE0    0xB0
 744 /* ... */
 745 #define MP_LCD_INST_SETPAGE7    0xB7
 746
 747 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 748
 749 typedef struct musicpal_lcd_state {
 750     uint32_t mode;
 751     uint32_t irqctrl;
 752     int page;
 753     int page_off;
 754     DisplayState *ds;
 755     uint8_t video_ram[128*64/8];
 756 } musicpal_lcd_state;
 757
 758 static uint32_t lcd_brightness;
 759
 760 static uint8_t scale_lcd_color(uint8_t col)
 761 {
 762     int tmp = col;
 763
 764     switch (lcd_brightness) {
 765     case 0x00000007: /* 0 */
 766         return 0;
 767
 768     case 0x00020000: /* 1 */
 769         return (tmp * 1) / 7;
 770
 771     case 0x00020001: /* 2 */
 772         return (tmp * 2) / 7;
 773
 774     case 0x00040000: /* 3 */
 775         return (tmp * 3) / 7;
 776
 777     case 0x00010006: /* 4 */
 778         return (tmp * 4) / 7;
 779
 780     case 0x00020005: /* 5 */
 781         return (tmp * 5) / 7;
 782
 783     case 0x00040003: /* 6 */
 784         return (tmp * 6) / 7;
 785
 786     case 0x00030004: /* 7 */
 787     default:
 788         return col;
 789     }
 790 }
 791
 792 #define SET_LCD_PIXEL(depth, type) \
 793 static inline void glue(set_lcd_pixel, depth) \
 794         (musicpal_lcd_state *s, int x, int y, type col) \
 795 { \
 796     int dx, dy; \
 797     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 798 \
 799     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 800         for (dx = 0; dx < 3; dx++, pixel++) \
 801             *pixel = col; \
 802 }
 803 SET_LCD_PIXEL(8, uint8_t)
 804 SET_LCD_PIXEL(16, uint16_t)
 805 SET_LCD_PIXEL(32, uint32_t)
 806
 807 #include "pixel_ops.h"
 808
 809 static void lcd_refresh(void *opaque)
 810 {
 811     musicpal_lcd_state *s = opaque;
 812     int x, y, col;
 813
 814     switch (ds_get_bits_per_pixel(s->ds)) {
 815     case 0:
 816         return;
 817 #define LCD_REFRESH(depth, func) \
 818     case depth: \
 819         col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 820                    scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 821                    scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
 822         for (x = 0; x < 128; x++) \
 823             for (y = 0; y < 64; y++) \
 824                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 825                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 826                 else \
 827                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 828         break;
 829     LCD_REFRESH(8, rgb_to_pixel8)
 830     LCD_REFRESH(16, rgb_to_pixel16)
 831     LCD_REFRESH(32, rgb_to_pixel32)
 832     default:
 833         cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
 834                   ds_get_bits_per_pixel(s->ds));
 835     }
 836
 837     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 838 }
 839
 840 static void lcd_invalidate(void *opaque)
 841 {
 842 }
 843
 844 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 845 {
 846     musicpal_lcd_state *s = opaque;
 847
 848     switch (offset) {
 849     case MP_LCD_IRQCTRL:
 850         return s->irqctrl;
 851
 852     default:
 853         return 0;
 854     }
 855 }
 856
 857 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 858                                uint32_t value)
 859 {
 860     musicpal_lcd_state *s = opaque;
 861
 862     switch (offset) {
 863     case MP_LCD_IRQCTRL:
 864         s->irqctrl = value;
 865         break;
 866
 867     case MP_LCD_SPICTRL:
 868         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 869             s->mode = value;
 870         else
 871             s->mode = MP_LCD_SPI_INVALID;
 872         break;
 873
 874     case MP_LCD_INST:
 875         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 876             s->page = value - MP_LCD_INST_SETPAGE0;
 877             s->page_off = 0;
 878         }
 879         break;
 880
 881     case MP_LCD_DATA:
 882         if (s->mode == MP_LCD_SPI_CMD) {
 883             if (value >= MP_LCD_INST_SETPAGE0 &&
 884                 value <= MP_LCD_INST_SETPAGE7) {
 885                 s->page = value - MP_LCD_INST_SETPAGE0;
 886                 s->page_off = 0;
 887             }
 888         } else if (s->mode == MP_LCD_SPI_DATA) {
 889             s->video_ram[s->page*128 + s->page_off] = value;
 890             s->page_off = (s->page_off + 1) & 127;
 891         }
 892         break;
 893     }
 894 }
 895
 896 static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
 897     musicpal_lcd_read,
 898     musicpal_lcd_read,
 899     musicpal_lcd_read
 900 };
 901
 902 static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
 903     musicpal_lcd_write,
 904     musicpal_lcd_write,
 905     musicpal_lcd_write
 906 };
 907
 908 static void musicpal_lcd_init(uint32_t base)
 909 {
 910     musicpal_lcd_state *s;
 911     int iomemtype;
 912
 913     s = qemu_mallocz(sizeof(musicpal_lcd_state));
 914     if (!s)
 915         return;
 916     iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
 917                                        musicpal_lcd_writefn, s);
 918     cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
 919
 920     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 921                                  NULL, NULL, s);
 922     qemu_console_resize(s->ds, 128*3, 64*3);
 923 }
 924
 925 /* PIC register offsets */
 926 #define MP_PIC_STATUS           0x00
 927 #define MP_PIC_ENABLE_SET       0x08
 928 #define MP_PIC_ENABLE_CLR       0x0C
 929
 930 typedef struct mv88w8618_pic_state
 931 {
 932     uint32_t level;
 933     uint32_t enabled;
 934     qemu_irq parent_irq;
 935 } mv88w8618_pic_state;
 936
 937 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 938 {
 939     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 940 }
 941
 942 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 943 {
 944     mv88w8618_pic_state *s = opaque;
 945
 946     if (level)
 947         s->level |= 1 << irq;
 948     else
 949         s->level &= ~(1 << irq);
 950     mv88w8618_pic_update(s);
 951 }
 952
 953 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 954 {
 955     mv88w8618_pic_state *s = opaque;
 956
 957     switch (offset) {
 958     case MP_PIC_STATUS:
 959         return s->level & s->enabled;
 960
 961     default:
 962         return 0;
 963     }
 964 }
 965
 966 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 967                                 uint32_t value)
 968 {
 969     mv88w8618_pic_state *s = opaque;
 970
 971     switch (offset) {
 972     case MP_PIC_ENABLE_SET:
 973         s->enabled |= value;
 974         break;
 975
 976     case MP_PIC_ENABLE_CLR:
 977         s->enabled &= ~value;
 978         s->level &= ~value;
 979         break;
 980     }
 981     mv88w8618_pic_update(s);
 982 }
 983
 984 static void mv88w8618_pic_reset(void *opaque)
 985 {
 986     mv88w8618_pic_state *s = opaque;
 987
 988     s->level = 0;
 989     s->enabled = 0;
 990 }
 991
 992 static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
 993     mv88w8618_pic_read,
 994     mv88w8618_pic_read,
 995     mv88w8618_pic_read
 996 };
 997
 998 static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
 999     mv88w8618_pic_write,
1000     mv88w8618_pic_write,
1001     mv88w8618_pic_write
1002 };
1003
1004 static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1005 {
1006     mv88w8618_pic_state *s;
1007     int iomemtype;
1008     qemu_irq *qi;
1009
1010     s = qemu_mallocz(sizeof(mv88w8618_pic_state));
1011     if (!s)
1012         return NULL;
1013     qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
1014     s->parent_irq = parent_irq;
1015     iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1016                                        mv88w8618_pic_writefn, s);
1017     cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1018
1019     qemu_register_reset(mv88w8618_pic_reset, s);
1020
1021     return qi;
1022 }
1023
1024 /* PIT register offsets */
1025 #define MP_PIT_TIMER1_LENGTH    0x00
1026 /* ... */
1027 #define MP_PIT_TIMER4_LENGTH    0x0C
1028 #define MP_PIT_CONTROL          0x10
1029 #define MP_PIT_TIMER1_VALUE     0x14
1030 /* ... */
1031 #define MP_PIT_TIMER4_VALUE     0x20
1032 #define MP_BOARD_RESET          0x34
1033
1034 /* Magic board reset value (probably some watchdog behind it) */
1035 #define MP_BOARD_RESET_MAGIC    0x10000
1036
1037 typedef struct mv88w8618_timer_state {
1038     ptimer_state *timer;
1039     uint32_t limit;
1040     int freq;
1041     qemu_irq irq;
1042 } mv88w8618_timer_state;
1043
1044 typedef struct mv88w8618_pit_state {
1045     void *timer[4];
1046     uint32_t control;
1047 } mv88w8618_pit_state;
1048
1049 static void mv88w8618_timer_tick(void *opaque)
1050 {
1051     mv88w8618_timer_state *s = opaque;
1052
1053     qemu_irq_raise(s->irq);
1054 }
1055
1056 static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1057 {
1058     mv88w8618_timer_state *s;
1059     QEMUBH *bh;
1060
1061     s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1062     s->irq = irq;
1063     s->freq = freq;
1064
1065     bh = qemu_bh_new(mv88w8618_timer_tick, s);
1066     s->timer = ptimer_init(bh);
1067
1068     return s;
1069 }
1070
1071 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1072 {
1073     mv88w8618_pit_state *s = opaque;
1074     mv88w8618_timer_state *t;
1075
1076     switch (offset) {
1077     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1078         t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1079         return ptimer_get_count(t->timer);
1080
1081     default:
1082         return 0;
1083     }
1084 }
1085
1086 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1087                                 uint32_t value)
1088 {
1089     mv88w8618_pit_state *s = opaque;
1090     mv88w8618_timer_state *t;
1091     int i;
1092
1093     switch (offset) {
1094     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1095         t = s->timer[offset >> 2];
1096         t->limit = value;
1097         ptimer_set_limit(t->timer, t->limit, 1);
1098         break;
1099
1100     case MP_PIT_CONTROL:
1101         for (i = 0; i < 4; i++) {
1102             if (value & 0xf) {
1103                 t = s->timer[i];
1104                 ptimer_set_limit(t->timer, t->limit, 0);
1105                 ptimer_set_freq(t->timer, t->freq);
1106                 ptimer_run(t->timer, 0);
1107             }
1108             value >>= 4;
1109         }
1110         break;
1111
1112     case MP_BOARD_RESET:
1113         if (value == MP_BOARD_RESET_MAGIC)
1114             qemu_system_reset_request();
1115         break;
1116     }
1117 }
1118
1119 static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1120     mv88w8618_pit_read,
1121     mv88w8618_pit_read,
1122     mv88w8618_pit_read
1123 };
1124
1125 static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1126     mv88w8618_pit_write,
1127     mv88w8618_pit_write,
1128     mv88w8618_pit_write
1129 };
1130
1131 static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1132 {
1133     int iomemtype;
1134     mv88w8618_pit_state *s;
1135
1136     s = qemu_mallocz(sizeof(mv88w8618_pit_state));
1137     if (!s)
1138         return;
1139
1140     /* Letting them all run at 1 MHz is likely just a pragmatic
1141      * simplification. */
1142     s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1143     s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1144     s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1145     s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1146
1147     iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1148                                        mv88w8618_pit_writefn, s);
1149     cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1150 }
1151
1152 /* Flash config register offsets */
1153 #define MP_FLASHCFG_CFGR0    0x04
1154
1155 typedef struct mv88w8618_flashcfg_state {
1156     uint32_t cfgr0;
1157 } mv88w8618_flashcfg_state;
1158
1159 static uint32_t mv88w8618_flashcfg_read(void *opaque,
1160                                         target_phys_addr_t offset)
1161 {
1162     mv88w8618_flashcfg_state *s = opaque;
1163
1164     switch (offset) {
1165     case MP_FLASHCFG_CFGR0:
1166         return s->cfgr0;
1167
1168     default:
1169         return 0;
1170     }
1171 }
1172
1173 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1174                                      uint32_t value)
1175 {
1176     mv88w8618_flashcfg_state *s = opaque;
1177
1178     switch (offset) {
1179     case MP_FLASHCFG_CFGR0:
1180         s->cfgr0 = value;
1181         break;
1182     }
1183 }
1184
1185 static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1186     mv88w8618_flashcfg_read,
1187     mv88w8618_flashcfg_read,
1188     mv88w8618_flashcfg_read
1189 };
1190
1191 static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1192     mv88w8618_flashcfg_write,
1193     mv88w8618_flashcfg_write,
1194     mv88w8618_flashcfg_write
1195 };
1196
1197 static void mv88w8618_flashcfg_init(uint32_t base)
1198 {
1199     int iomemtype;
1200     mv88w8618_flashcfg_state *s;
1201
1202     s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
1203     if (!s)
1204         return;
1205
1206     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1207     iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1208                        mv88w8618_flashcfg_writefn, s);
1209     cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1210 }
1211
1212 /* Various registers in the 0x80000000 domain */
1213 #define MP_BOARD_REVISION       0x2018
1214
1215 #define MP_WLAN_MAGIC1          0xc11c
1216 #define MP_WLAN_MAGIC2          0xc124
1217
1218 #define MP_GPIO_OE_LO           0xd008
1219 #define MP_GPIO_OUT_LO          0xd00c
1220 #define MP_GPIO_IN_LO           0xd010
1221 #define MP_GPIO_ISR_LO          0xd020
1222 #define MP_GPIO_OE_HI           0xd508
1223 #define MP_GPIO_OUT_HI          0xd50c
1224 #define MP_GPIO_IN_HI           0xd510
1225 #define MP_GPIO_ISR_HI          0xd520
1226
1227 /* GPIO bits & masks */
1228 #define MP_GPIO_WHEEL_VOL       (1 << 8)
1229 #define MP_GPIO_WHEEL_VOL_INV   (1 << 9)
1230 #define MP_GPIO_WHEEL_NAV       (1 << 10)
1231 #define MP_GPIO_WHEEL_NAV_INV   (1 << 11)
1232 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1233 #define MP_GPIO_BTN_FAVORITS    (1 << 19)
1234 #define MP_GPIO_BTN_MENU        (1 << 20)
1235 #define MP_GPIO_BTN_VOLUME      (1 << 21)
1236 #define MP_GPIO_BTN_NAVIGATION  (1 << 22)
1237 #define MP_GPIO_I2C_DATA_BIT    29
1238 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
1239 #define MP_GPIO_I2C_CLOCK_BIT   30
1240
1241 /* LCD brightness bits in GPIO_OE_HI */
1242 #define MP_OE_LCD_BRIGHTNESS    0x0007
1243
1244 static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset)
1245 {
1246     switch (offset) {
1247     case MP_BOARD_REVISION:
1248         return 0x0031;
1249
1250     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1251         return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1252
1253     case MP_GPIO_OUT_LO:
1254         return gpio_out_state & 0xFFFF;
1255     case MP_GPIO_OUT_HI:
1256         return gpio_out_state >> 16;
1257
1258     case MP_GPIO_IN_LO:
1259         return gpio_in_state & 0xFFFF;
1260     case MP_GPIO_IN_HI:
1261         /* Update received I2C data */
1262         gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1263                         (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1264         return gpio_in_state >> 16;
1265
1266     case MP_GPIO_ISR_LO:
1267         return gpio_isr & 0xFFFF;
1268     case MP_GPIO_ISR_HI:
1269         return gpio_isr >> 16;
1270
1271     /* Workaround to allow loading the binary-only wlandrv.ko crap
1272      * from the original Freecom firmware. */
1273     case MP_WLAN_MAGIC1:
1274         return ~3;
1275     case MP_WLAN_MAGIC2:
1276         return -1;
1277
1278     default:
1279         return 0;
1280     }
1281 }
1282
1283 static void musicpal_write(void *opaque, target_phys_addr_t offset,
1284                            uint32_t value)
1285 {
1286     switch (offset) {
1287     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1288         lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1289                          (value & MP_OE_LCD_BRIGHTNESS);
1290         break;
1291
1292     case MP_GPIO_OUT_LO:
1293         gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1294         break;
1295     case MP_GPIO_OUT_HI:
1296         gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1297         lcd_brightness = (lcd_brightness & 0xFFFF) |
1298                          (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1299         i2c_state_update(mixer_i2c,
1300                          (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1301                          (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1302         break;
1303
1304     }
1305 }
1306
1307 /* Keyboard codes & masks */
1308 #define KEY_RELEASED            0x80
1309 #define KEY_CODE                0x7f
1310
1311 #define KEYCODE_TAB             0x0f
1312 #define KEYCODE_ENTER           0x1c
1313 #define KEYCODE_F               0x21
1314 #define KEYCODE_M               0x32
1315
1316 #define KEYCODE_EXTENDED        0xe0
1317 #define KEYCODE_UP              0x48
1318 #define KEYCODE_DOWN            0x50
1319 #define KEYCODE_LEFT            0x4b
1320 #define KEYCODE_RIGHT           0x4d
1321
1322 static void musicpal_key_event(void *opaque, int keycode)
1323 {
1324     qemu_irq irq = opaque;
1325     uint32_t event = 0;
1326     static int kbd_extended;
1327
1328     if (keycode == KEYCODE_EXTENDED) {
1329         kbd_extended = 1;
1330         return;
1331     }
1332
1333     if (kbd_extended)
1334         switch (keycode & KEY_CODE) {
1335         case KEYCODE_UP:
1336             event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1337             break;
1338
1339         case KEYCODE_DOWN:
1340             event = MP_GPIO_WHEEL_NAV;
1341             break;
1342
1343         case KEYCODE_LEFT:
1344             event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1345             break;
1346
1347         case KEYCODE_RIGHT:
1348             event = MP_GPIO_WHEEL_VOL;
1349             break;
1350         }
1351     else {
1352         switch (keycode & KEY_CODE) {
1353         case KEYCODE_F:
1354             event = MP_GPIO_BTN_FAVORITS;
1355             break;
1356
1357         case KEYCODE_TAB:
1358             event = MP_GPIO_BTN_VOLUME;
1359             break;
1360
1361         case KEYCODE_ENTER:
1362             event = MP_GPIO_BTN_NAVIGATION;
1363             break;
1364
1365         case KEYCODE_M:
1366             event = MP_GPIO_BTN_MENU;
1367             break;
1368         }
1369         /* Do not repeat already pressed buttons */
1370         if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1371             event = 0;
1372     }
1373
1374     if (event) {
1375         if (keycode & KEY_RELEASED) {
1376             gpio_in_state |= event;
1377         } else {
1378             gpio_in_state &= ~event;
1379             gpio_isr = event;
1380             qemu_irq_raise(irq);
1381         }
1382     }
1383
1384     kbd_extended = 0;
1385 }
1386
1387 static CPUReadMemoryFunc *musicpal_readfn[] = {
1388     musicpal_read,
1389     musicpal_read,
1390     musicpal_read,
1391 };
1392
1393 static CPUWriteMemoryFunc *musicpal_writefn[] = {
1394     musicpal_write,
1395     musicpal_write,
1396     musicpal_write,
1397 };
1398
1399 static struct arm_boot_info musicpal_binfo = {
1400     .loader_start = 0x0,
1401     .board_id = 0x20e,
1402 };
1403
1404 static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
1405                const char *boot_device,
1406                const char *kernel_filename, const char *kernel_cmdline,
1407                const char *initrd_filename, const char *cpu_model)
1408 {
1409     CPUState *env;
1410     qemu_irq *pic;
1411     int index;
1412     int iomemtype;
1413     unsigned long flash_size;
1414
1415     if (!cpu_model)
1416         cpu_model = "arm926";
1417
1418     env = cpu_init(cpu_model);
1419     if (!env) {
1420         fprintf(stderr, "Unable to find CPU definition\n");
1421         exit(1);
1422     }
1423     pic = arm_pic_init_cpu(env);
1424
1425     /* For now we use a fixed - the original - RAM size */
1426     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1427                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1428
1429     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1430     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1431
1432     /* Catch various stuff not handled by separate subsystems */
1433     iomemtype = cpu_register_io_memory(0, musicpal_readfn,
1434                                        musicpal_writefn, env);
1435     cpu_register_physical_memory(0x80000000, 0x10000, iomemtype);
1436
1437     pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1438     mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1439
1440     if (serial_hds[0])
1441         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1442                    serial_hds[0], 1);
1443     if (serial_hds[1])
1444         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1445                    serial_hds[1], 1);
1446
1447     /* Register flash */
1448     index = drive_get_index(IF_PFLASH, 0, 0);
1449     if (index != -1) {
1450         flash_size = bdrv_getlength(drives_table[index].bdrv);
1451         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1452             flash_size != 32*1024*1024) {
1453             fprintf(stderr, "Invalid flash image size\n");
1454             exit(1);
1455         }
1456
1457         /*
1458          * The original U-Boot accesses the flash at 0xFE000000 instead of
1459          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1460          * image is smaller than 32 MB.
1461          */
1462         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1463                               drives_table[index].bdrv, 0x10000,
1464                               (flash_size + 0xffff) >> 16,
1465                               MP_FLASH_SIZE_MAX / flash_size,
1466                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1467                               0x5555, 0x2AAA);
1468     }
1469     mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1470
1471     musicpal_lcd_init(MP_LCD_BASE);
1472
1473     qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1474
1475     mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1476
1477     mixer_i2c = musicpal_audio_init(MP_AUDIO_BASE, pic[MP_AUDIO_IRQ]);
1478
1479     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1480     musicpal_binfo.kernel_filename = kernel_filename;
1481     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1482     musicpal_binfo.initrd_filename = initrd_filename;
1483     arm_load_kernel(env, &musicpal_binfo);
1484 }
1485
1486 QEMUMachine musicpal_machine = {
1487     .name = "musicpal",
1488     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1489     .init = musicpal_init,
1490     .ram_require = MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE +
1491             MP_FLASH_SIZE_MAX + RAMSIZE_FIXED,
1492 };