2 * common defines for all CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
24 #error cpu.h included from common code
33 #include "sys-queue.h"
35 #ifndef TARGET_LONG_BITS
36 #error TARGET_LONG_BITS must be defined before including this header
39 #ifndef TARGET_PHYS_ADDR_BITS
40 #if TARGET_LONG_BITS >= HOST_LONG_BITS
41 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
43 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
47 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
49 /* target_ulong is the type of a virtual address */
50 #if TARGET_LONG_SIZE == 4
51 typedef int32_t target_long
;
52 typedef uint32_t target_ulong
;
53 #define TARGET_FMT_lx "%08x"
54 #define TARGET_FMT_ld "%d"
55 #define TARGET_FMT_lu "%u"
56 #elif TARGET_LONG_SIZE == 8
57 typedef int64_t target_long
;
58 typedef uint64_t target_ulong
;
59 #define TARGET_FMT_lx "%016" PRIx64
60 #define TARGET_FMT_ld "%" PRId64
61 #define TARGET_FMT_lu "%" PRIu64
63 #error TARGET_LONG_SIZE undefined
66 /* target_phys_addr_t is the type of a physical address (its size can
67 be different from 'target_ulong'). We have sizeof(target_phys_addr)
68 = max(sizeof(unsigned long),
69 sizeof(size_of_target_physical_address)) because we must pass a
70 host pointer to memory operations in some cases */
72 #if TARGET_PHYS_ADDR_BITS == 32
73 typedef uint32_t target_phys_addr_t
;
74 #define TARGET_FMT_plx "%08x"
75 #elif TARGET_PHYS_ADDR_BITS == 64
76 typedef uint64_t target_phys_addr_t
;
77 #define TARGET_FMT_plx "%016" PRIx64
79 #error TARGET_PHYS_ADDR_BITS undefined
82 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
84 #define EXCP_INTERRUPT 0x10000 /* async interruption */
85 #define EXCP_HLT 0x10001 /* hlt instruction reached */
86 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
87 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
89 #define TB_JMP_CACHE_BITS 12
90 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
92 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
93 addresses on the same page. The top bits are the same. This allows
94 TLB invalidation to quickly clear a subset of the hash table. */
95 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
96 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
97 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
98 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
100 #define CPU_TLB_BITS 8
101 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
103 #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
104 #define CPU_TLB_ENTRY_BITS 4
106 #define CPU_TLB_ENTRY_BITS 5
109 typedef struct CPUTLBEntry
{
110 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
111 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
113 bit 3 : indicates that the entry is invalid
116 target_ulong addr_read
;
117 target_ulong addr_write
;
118 target_ulong addr_code
;
119 /* Addend to virtual address to get physical address. IO accesses
120 use the corresponding iotlb value. */
121 #if TARGET_PHYS_ADDR_BITS == 64
122 /* on i386 Linux make sure it is aligned */
123 target_phys_addr_t addend
__attribute__((aligned(8)));
125 target_phys_addr_t addend
;
127 /* padding to get a power of two size */
128 uint8_t dummy
[(1 << CPU_TLB_ENTRY_BITS
) -
129 (sizeof(target_ulong
) * 3 +
130 ((-sizeof(target_ulong
) * 3) & (sizeof(target_phys_addr_t
) - 1)) +
131 sizeof(target_phys_addr_t
))];
134 #ifdef WORDS_BIGENDIAN
135 typedef struct icount_decr_u16
{
140 typedef struct icount_decr_u16
{
149 typedef struct CPUBreakpoint
{
151 int flags
; /* BP_* */
152 TAILQ_ENTRY(CPUBreakpoint
) entry
;
155 typedef struct CPUWatchpoint
{
157 target_ulong len_mask
;
158 int flags
; /* BP_* */
159 TAILQ_ENTRY(CPUWatchpoint
) entry
;
162 /* forward decleration */
163 struct qemu_work_item
;
173 struct qemu_work_item
*queued_work_first
, *queued_work_last
;
176 #define CPU_TEMP_BUF_NLONGS 128
178 struct TranslationBlock *current_tb; /* currently executing TB */ \
179 /* soft mmu support */ \
180 /* in order to avoid passing too many arguments to the MMIO \
181 helpers, we store some rarely used information in the CPU \
183 unsigned long mem_io_pc; /* host pc at which the memory was \
185 target_ulong mem_io_vaddr; /* target virtual addr at which the \
186 memory was accessed */ \
187 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
188 uint32_t interrupt_request; \
189 volatile sig_atomic_t exit_request; \
190 /* The meaning of the MMU modes is defined in the target code. */ \
191 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
192 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
193 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
194 /* buffer for temporaries in the code generator */ \
195 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
197 int64_t icount_extra; /* Instructions until next timer event. */ \
198 /* Number of cycles left, with interrupt flag in high bit. \
199 This allows a single read-compare-cbranch-write sequence to test \
200 for both decrementer underflow and exceptions. */ \
203 icount_decr_u16 u16; \
205 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
207 /* from this point: preserved by CPU reset */ \
208 /* ice debug support */ \
209 TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
210 int singlestep_enabled; \
212 TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
213 CPUWatchpoint *watchpoint_hit; \
215 struct GDBRegisterState *gdb_regs; \
217 /* Core interrupt code */ \
219 int exception_index; \
221 void *next_cpu; /* next CPU sharing TB cache */ \
222 int cpu_index; /* CPU index (informative) */ \
223 int running; /* Nonzero if cpu is currently running(usermode). */ \
228 const char *cpu_model_str; \
229 struct KVMState *kvm_state; \
230 struct kvm_run *kvm_run; \
232 struct KVMCPUState kvm_cpu_state;