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Fix 32-bit overflow in parallels image support
[qemu-kvm/fedora.git] / qemu-kvm-x86.c
blob300e6c253f4c7c788e596caddd2f9a2413b39dde
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/pc.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = kvm_vm_ioctl(kvm_state, KVM_SET_TSS_ADDR, addr);
44 if (r < 0) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return r;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfffbd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_set_identity_map_addr(kvm_context_t kvm, unsigned long addr)
77 {
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
79 int r;
80
81 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
82 if (r > 0) {
83 r = kvm_vm_ioctl(kvm_state, KVM_SET_IDENTITY_MAP_ADDR, &addr);
84 if (r == -1) {
85 fprintf(stderr, "kvm_set_identity_map_addr: %m\n");
86 return -errno;
87 }
88 return 0;
89 }
90 #endif
91 return -ENOSYS;
92 }
93
94 static int kvm_init_identity_map_page(kvm_context_t kvm)
95 {
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
97 int r;
98
99 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
100 if (r > 0) {
101 /*
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
104 */
105 r = kvm_set_identity_map_addr(kvm, 0xfffbc000);
106 if (r < 0) {
107 fprintf(stderr, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
109 return r;
110 }
111
112 }
113 #endif
114 return 0;
115 }
116
117 static int kvm_create_pit(kvm_context_t kvm)
118 {
119 #ifdef KVM_CAP_PIT
120 int r;
121
122 kvm->pit_in_kernel = 0;
123 if (!kvm->no_pit_creation) {
124 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
125 if (r > 0) {
126 r = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT);
127 if (r >= 0)
128 kvm->pit_in_kernel = 1;
129 else {
130 fprintf(stderr, "Create kernel PIC irqchip failed\n");
131 return r;
132 }
133 }
134 }
135 #endif
136 return 0;
137 }
138
139 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
140 void **vm_mem)
141 {
142 int r = 0;
143
144 r = kvm_init_tss(kvm);
145 if (r < 0)
146 return r;
147
148 r = kvm_init_identity_map_page(kvm);
149 if (r < 0)
150 return r;
151
152 r = kvm_create_pit(kvm);
153 if (r < 0)
154 return r;
155
156 r = kvm_init_coalesced_mmio(kvm);
157 if (r < 0)
158 return r;
159
160 return 0;
161 }
162
163 #ifdef KVM_EXIT_TPR_ACCESS
164
165 static int kvm_handle_tpr_access(kvm_vcpu_context_t vcpu)
166 {
167 struct kvm_run *run = vcpu->run;
168 kvm_tpr_access_report(cpu_single_env,
169 run->tpr_access.rip,
170 run->tpr_access.is_write);
171 return 0;
172 }
173
174
175 int kvm_enable_vapic(kvm_vcpu_context_t vcpu, uint64_t vapic)
176 {
177 int r;
178 struct kvm_vapic_addr va = {
179 .vapic_addr = vapic,
180 };
181
182 r = ioctl(vcpu->fd, KVM_SET_VAPIC_ADDR, &va);
183 if (r == -1) {
184 r = -errno;
185 perror("kvm_enable_vapic");
186 return r;
187 }
188 return 0;
189 }
190
191 #endif
192
193 int kvm_arch_run(kvm_vcpu_context_t vcpu)
194 {
195 int r = 0;
196 struct kvm_run *run = vcpu->run;
197
198
199 switch (run->exit_reason) {
200 #ifdef KVM_EXIT_SET_TPR
201 case KVM_EXIT_SET_TPR:
202 break;
203 #endif
204 #ifdef KVM_EXIT_TPR_ACCESS
205 case KVM_EXIT_TPR_ACCESS:
206 r = kvm_handle_tpr_access(vcpu);
207 break;
208 #endif
209 default:
210 r = 1;
211 break;
212 }
213
214 return r;
215 }
216
217 #define MAX_ALIAS_SLOTS 4
218 static struct {
219 uint64_t start;
220 uint64_t len;
221 } kvm_aliases[MAX_ALIAS_SLOTS];
222
223 static int get_alias_slot(uint64_t start)
224 {
225 int i;
226
227 for (i=0; i<MAX_ALIAS_SLOTS; i++)
228 if (kvm_aliases[i].start == start)
229 return i;
230 return -1;
231 }
232 static int get_free_alias_slot(void)
233 {
234 int i;
235
236 for (i=0; i<MAX_ALIAS_SLOTS; i++)
237 if (kvm_aliases[i].len == 0)
238 return i;
239 return -1;
240 }
241
242 static void register_alias(int slot, uint64_t start, uint64_t len)
243 {
244 kvm_aliases[slot].start = start;
245 kvm_aliases[slot].len = len;
246 }
247
248 int kvm_create_memory_alias(kvm_context_t kvm,
249 uint64_t phys_start,
250 uint64_t len,
251 uint64_t target_phys)
252 {
253 struct kvm_memory_alias alias = {
254 .flags = 0,
255 .guest_phys_addr = phys_start,
256 .memory_size = len,
257 .target_phys_addr = target_phys,
258 };
259 int r;
260 int slot;
261
262 slot = get_alias_slot(phys_start);
263 if (slot < 0)
264 slot = get_free_alias_slot();
265 if (slot < 0)
266 return -EBUSY;
267 alias.slot = slot;
268
269 r = kvm_vm_ioctl(kvm_state, KVM_SET_MEMORY_ALIAS, &alias);
270 if (r == -1)
271 return -errno;
272
273 register_alias(slot, phys_start, len);
274 return 0;
275 }
276
277 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
278 {
279 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
280 }
281
282 #ifdef KVM_CAP_IRQCHIP
283
284 int kvm_get_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
285 {
286 int r;
287 if (!kvm_irqchip_in_kernel(vcpu->kvm))
288 return 0;
289 r = ioctl(vcpu->fd, KVM_GET_LAPIC, s);
290 if (r == -1) {
291 r = -errno;
292 perror("kvm_get_lapic");
293 }
294 return r;
295 }
296
297 int kvm_set_lapic(kvm_vcpu_context_t vcpu, struct kvm_lapic_state *s)
298 {
299 int r;
300 if (!kvm_irqchip_in_kernel(vcpu->kvm))
301 return 0;
302 r = ioctl(vcpu->fd, KVM_SET_LAPIC, s);
303 if (r == -1) {
304 r = -errno;
305 perror("kvm_set_lapic");
306 }
307 return r;
308 }
309
310 #endif
311
312 #ifdef KVM_CAP_PIT
313
314 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
315 {
316 if (!kvm->pit_in_kernel)
317 return 0;
318 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT, s);
319 }
320
321 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
322 {
323 if (!kvm->pit_in_kernel)
324 return 0;
325 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT, s);
326 }
327
328 #ifdef KVM_CAP_PIT_STATE2
329 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
330 {
331 if (!kvm->pit_in_kernel)
332 return 0;
333 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT2, ps2);
334 }
335
336 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
337 {
338 if (!kvm->pit_in_kernel)
339 return 0;
340 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT2, ps2);
341 }
342
343 #endif
344 #endif
345
346 int kvm_has_pit_state2(kvm_context_t kvm)
347 {
348 int r = 0;
349
350 #ifdef KVM_CAP_PIT_STATE2
351 r = kvm_check_extension(kvm_state, KVM_CAP_PIT_STATE2);
352 #endif
353 return r;
354 }
355
356 void kvm_show_code(kvm_vcpu_context_t vcpu)
357 {
358 #define SHOW_CODE_LEN 50
359 int fd = vcpu->fd;
360 struct kvm_regs regs;
361 struct kvm_sregs sregs;
362 int r, n;
363 int back_offset;
364 unsigned char code;
365 char code_str[SHOW_CODE_LEN * 3 + 1];
366 unsigned long rip;
367 kvm_context_t kvm = vcpu->kvm;
368
369 r = ioctl(fd, KVM_GET_SREGS, &sregs);
370 if (r == -1) {
371 perror("KVM_GET_SREGS");
372 return;
373 }
374 r = ioctl(fd, KVM_GET_REGS, &regs);
375 if (r == -1) {
376 perror("KVM_GET_REGS");
377 return;
378 }
379 rip = sregs.cs.base + regs.rip;
380 back_offset = regs.rip;
381 if (back_offset > 20)
382 back_offset = 20;
383 *code_str = 0;
384 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
385 if (n == 0)
386 strcat(code_str, " -->");
387 r = kvm_mmio_read(kvm->opaque, rip + n, &code, 1);
388 if (r < 0) {
389 strcat(code_str, " xx");
390 continue;
391 }
392 sprintf(code_str + strlen(code_str), " %02x", code);
393 }
394 fprintf(stderr, "code:%s\n", code_str);
395 }
396
397
398 /*
399 * Returns available msr list. User must free.
400 */
401 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
402 {
403 struct kvm_msr_list sizer, *msrs;
404 int r;
405
406 sizer.nmsrs = 0;
407 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, &sizer);
408 if (r < 0 && r != -E2BIG)
409 return NULL;
410 /* Old kernel modules had a bug and could write beyond the provided
411 memory. Allocate at least a safe amount of 1K. */
412 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
413 sizer.nmsrs * sizeof(*msrs->indices)));
414
415 msrs->nmsrs = sizer.nmsrs;
416 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, msrs);
417 if (r < 0) {
418 free(msrs);
419 errno = r;
420 return NULL;
421 }
422 return msrs;
423 }
424
425 int kvm_get_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
426 {
427 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
428 int r, e;
429
430 kmsrs->nmsrs = n;
431 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
432 r = ioctl(vcpu->fd, KVM_GET_MSRS, kmsrs);
433 e = errno;
434 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
435 free(kmsrs);
436 errno = e;
437 return r;
438 }
439
440 int kvm_set_msrs(kvm_vcpu_context_t vcpu, struct kvm_msr_entry *msrs, int n)
441 {
442 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
443 int r, e;
444
445 kmsrs->nmsrs = n;
446 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
447 r = ioctl(vcpu->fd, KVM_SET_MSRS, kmsrs);
448 e = errno;
449 free(kmsrs);
450 errno = e;
451 return r;
452 }
453
454 int kvm_get_mce_cap_supported(kvm_context_t kvm, uint64_t *mce_cap,
455 int *max_banks)
456 {
457 #ifdef KVM_CAP_MCE
458 int r;
459
460 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
461 if (r > 0) {
462 *max_banks = r;
463 return kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
464 }
465 #endif
466 return -ENOSYS;
467 }
468
469 int kvm_setup_mce(kvm_vcpu_context_t vcpu, uint64_t *mcg_cap)
470 {
471 #ifdef KVM_CAP_MCE
472 return ioctl(vcpu->fd, KVM_X86_SETUP_MCE, mcg_cap);
473 #else
474 return -ENOSYS;
475 #endif
476 }
477
478 int kvm_set_mce(kvm_vcpu_context_t vcpu, struct kvm_x86_mce *m)
479 {
480 #ifdef KVM_CAP_MCE
481 return ioctl(vcpu->fd, KVM_X86_SET_MCE, m);
482 #else
483 return -ENOSYS;
484 #endif
485 }
486
487 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
488 {
489 fprintf(stderr,
490 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
491 " g %d avl %d)\n",
492 name, seg->selector, seg->base, seg->limit, seg->present,
493 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
494 seg->avl);
495 }
496
497 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
498 {
499 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
500 }
501
502 void kvm_show_regs(kvm_vcpu_context_t vcpu)
503 {
504 int fd = vcpu->fd;
505 struct kvm_regs regs;
506 struct kvm_sregs sregs;
507 int r;
508
509 r = ioctl(fd, KVM_GET_REGS, &regs);
510 if (r == -1) {
511 perror("KVM_GET_REGS");
512 return;
513 }
514 fprintf(stderr,
515 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
516 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
517 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
518 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
519 "rip %016llx rflags %08llx\n",
520 regs.rax, regs.rbx, regs.rcx, regs.rdx,
521 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
522 regs.r8, regs.r9, regs.r10, regs.r11,
523 regs.r12, regs.r13, regs.r14, regs.r15,
524 regs.rip, regs.rflags);
525 r = ioctl(fd, KVM_GET_SREGS, &sregs);
526 if (r == -1) {
527 perror("KVM_GET_SREGS");
528 return;
529 }
530 print_seg(stderr, "cs", &sregs.cs);
531 print_seg(stderr, "ds", &sregs.ds);
532 print_seg(stderr, "es", &sregs.es);
533 print_seg(stderr, "ss", &sregs.ss);
534 print_seg(stderr, "fs", &sregs.fs);
535 print_seg(stderr, "gs", &sregs.gs);
536 print_seg(stderr, "tr", &sregs.tr);
537 print_seg(stderr, "ldt", &sregs.ldt);
538 print_dt(stderr, "gdt", &sregs.gdt);
539 print_dt(stderr, "idt", &sregs.idt);
540 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
541 " efer %llx\n",
542 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
543 sregs.efer);
544 }
545
546 uint64_t kvm_get_apic_base(kvm_vcpu_context_t vcpu)
547 {
548 return vcpu->run->apic_base;
549 }
550
551 void kvm_set_cr8(kvm_vcpu_context_t vcpu, uint64_t cr8)
552 {
553 vcpu->run->cr8 = cr8;
554 }
555
556 __u64 kvm_get_cr8(kvm_vcpu_context_t vcpu)
557 {
558 return vcpu->run->cr8;
559 }
560
561 int kvm_setup_cpuid(kvm_vcpu_context_t vcpu, int nent,
562 struct kvm_cpuid_entry *entries)
563 {
564 struct kvm_cpuid *cpuid;
565 int r;
566
567 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
568
569 cpuid->nent = nent;
570 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
571 r = ioctl(vcpu->fd, KVM_SET_CPUID, cpuid);
572
573 free(cpuid);
574 return r;
575 }
576
577 int kvm_setup_cpuid2(kvm_vcpu_context_t vcpu, int nent,
578 struct kvm_cpuid_entry2 *entries)
579 {
580 struct kvm_cpuid2 *cpuid;
581 int r;
582
583 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
584
585 cpuid->nent = nent;
586 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
587 r = ioctl(vcpu->fd, KVM_SET_CPUID2, cpuid);
588 if (r == -1) {
589 fprintf(stderr, "kvm_setup_cpuid2: %m\n");
590 r = -errno;
591 }
592 free(cpuid);
593 return r;
594 }
595
596 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
597 {
598 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
599 int r;
600
601 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
602 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
603 if (r > 0) {
604 r = kvm_vm_ioctl(kvm_state, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
605 if (r < 0) {
606 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
607 return r;
608 }
609 return 0;
610 }
611 #endif
612 return -1;
613 }
614
615 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
616 {
617 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
618 int r;
619
620 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
621 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
622 if (r > 0) {
623 *nrshadow_pages = kvm_vm_ioctl(kvm_state, KVM_GET_NR_MMU_PAGES);
624 return 0;
625 }
626 #endif
627 return -1;
628 }
629
630 #ifdef KVM_CAP_VAPIC
631
632 static int tpr_access_reporting(kvm_vcpu_context_t vcpu, int enabled)
633 {
634 int r;
635 struct kvm_tpr_access_ctl tac = {
636 .enabled = enabled,
637 };
638
639 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
640 if (r <= 0)
641 return -ENOSYS;
642 r = ioctl(vcpu->fd, KVM_TPR_ACCESS_REPORTING, &tac);
643 if (r == -1) {
644 r = -errno;
645 perror("KVM_TPR_ACCESS_REPORTING");
646 return r;
647 }
648 return 0;
649 }
650
651 int kvm_enable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
652 {
653 return tpr_access_reporting(vcpu, 1);
654 }
655
656 int kvm_disable_tpr_access_reporting(kvm_vcpu_context_t vcpu)
657 {
658 return tpr_access_reporting(vcpu, 0);
659 }
660
661 #endif
662
663 #ifdef KVM_CAP_EXT_CPUID
664
665 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
666 {
667 struct kvm_cpuid2 *cpuid;
668 int r, size;
669
670 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
671 cpuid = qemu_malloc(size);
672 cpuid->nent = max;
673 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_CPUID, cpuid);
674 if (r == 0 && cpuid->nent >= max)
675 r = -E2BIG;
676 if (r < 0) {
677 if (r == -E2BIG) {
678 free(cpuid);
679 return NULL;
680 } else {
681 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
682 strerror(-r));
683 exit(1);
684 }
685 }
686 return cpuid;
687 }
688
689 #define R_EAX 0
690 #define R_ECX 1
691 #define R_EDX 2
692 #define R_EBX 3
693 #define R_ESP 4
694 #define R_EBP 5
695 #define R_ESI 6
696 #define R_EDI 7
697
698 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
699 {
700 struct kvm_cpuid2 *cpuid;
701 int i, max;
702 uint32_t ret = 0;
703 uint32_t cpuid_1_edx;
704
705 if (!kvm_check_extension(kvm_state, KVM_CAP_EXT_CPUID)) {
706 return -1U;
707 }
708
709 max = 1;
710 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
711 max *= 2;
712 }
713
714 for (i = 0; i < cpuid->nent; ++i) {
715 if (cpuid->entries[i].function == function) {
716 switch (reg) {
717 case R_EAX:
718 ret = cpuid->entries[i].eax;
719 break;
720 case R_EBX:
721 ret = cpuid->entries[i].ebx;
722 break;
723 case R_ECX:
724 ret = cpuid->entries[i].ecx;
725 break;
726 case R_EDX:
727 ret = cpuid->entries[i].edx;
728 if (function == 1) {
729 /* kvm misreports the following features
730 */
731 ret |= 1 << 12; /* MTRR */
732 ret |= 1 << 16; /* PAT */
733 ret |= 1 << 7; /* MCE */
734 ret |= 1 << 14; /* MCA */
735 }
736
737 /* On Intel, kvm returns cpuid according to
738 * the Intel spec, so add missing bits
739 * according to the AMD spec:
740 */
741 if (function == 0x80000001) {
742 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
743 ret |= cpuid_1_edx & 0xdfeff7ff;
744 }
745 break;
746 }
747 }
748 }
749
750 free(cpuid);
751
752 return ret;
753 }
754
755 #else
756
757 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
758 {
759 return -1U;
760 }
761
762 #endif
763 int kvm_qemu_create_memory_alias(uint64_t phys_start,
764 uint64_t len,
765 uint64_t target_phys)
766 {
767 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
768 }
769
770 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
771 {
772 return kvm_destroy_memory_alias(kvm_context, phys_start);
773 }
774
775 int kvm_arch_qemu_create_context(void)
776 {
777 int i;
778 struct utsname utsname;
779
780 uname(&utsname);
781 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
782
783 if (kvm_shadow_memory)
784 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
785
786 kvm_msr_list = kvm_get_msr_list(kvm_context);
787 if (!kvm_msr_list)
788 return -1;
789 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
790 if (kvm_msr_list->indices[i] == MSR_STAR)
791 kvm_has_msr_star = 1;
792 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
793 kvm_has_vm_hsave_pa = 1;
794 }
795
796 return 0;
797 }
798
799 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
800 uint64_t data)
801 {
802 entry->index = index;
803 entry->data = data;
804 }
805
806 /* returns 0 on success, non-0 on failure */
807 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
808 {
809 switch (entry->index) {
810 case MSR_IA32_SYSENTER_CS:
811 env->sysenter_cs = entry->data;
812 break;
813 case MSR_IA32_SYSENTER_ESP:
814 env->sysenter_esp = entry->data;
815 break;
816 case MSR_IA32_SYSENTER_EIP:
817 env->sysenter_eip = entry->data;
818 break;
819 case MSR_STAR:
820 env->star = entry->data;
821 break;
822 #ifdef TARGET_X86_64
823 case MSR_CSTAR:
824 env->cstar = entry->data;
825 break;
826 case MSR_KERNELGSBASE:
827 env->kernelgsbase = entry->data;
828 break;
829 case MSR_FMASK:
830 env->fmask = entry->data;
831 break;
832 case MSR_LSTAR:
833 env->lstar = entry->data;
834 break;
835 #endif
836 case MSR_IA32_TSC:
837 env->tsc = entry->data;
838 break;
839 case MSR_VM_HSAVE_PA:
840 env->vm_hsave = entry->data;
841 break;
842 case MSR_KVM_SYSTEM_TIME:
843 env->system_time_msr = entry->data;
844 break;
845 case MSR_KVM_WALL_CLOCK:
846 env->wall_clock_msr = entry->data;
847 break;
848 default:
849 printf("Warning unknown msr index 0x%x\n", entry->index);
850 return 1;
851 }
852 return 0;
853 }
854
855 #ifdef TARGET_X86_64
856 #define MSR_COUNT 12
857 #else
858 #define MSR_COUNT 8
859 #endif
860
861 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
862 {
863 lhs->selector = rhs->selector;
864 lhs->base = rhs->base;
865 lhs->limit = rhs->limit;
866 lhs->type = 3;
867 lhs->present = 1;
868 lhs->dpl = 3;
869 lhs->db = 0;
870 lhs->s = 1;
871 lhs->l = 0;
872 lhs->g = 0;
873 lhs->avl = 0;
874 lhs->unusable = 0;
875 }
876
877 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
878 {
879 unsigned flags = rhs->flags;
880 lhs->selector = rhs->selector;
881 lhs->base = rhs->base;
882 lhs->limit = rhs->limit;
883 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
884 lhs->present = (flags & DESC_P_MASK) != 0;
885 lhs->dpl = rhs->selector & 3;
886 lhs->db = (flags >> DESC_B_SHIFT) & 1;
887 lhs->s = (flags & DESC_S_MASK) != 0;
888 lhs->l = (flags >> DESC_L_SHIFT) & 1;
889 lhs->g = (flags & DESC_G_MASK) != 0;
890 lhs->avl = (flags & DESC_AVL_MASK) != 0;
891 lhs->unusable = 0;
892 }
893
894 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
895 {
896 lhs->selector = rhs->selector;
897 lhs->base = rhs->base;
898 lhs->limit = rhs->limit;
899 lhs->flags =
900 (rhs->type << DESC_TYPE_SHIFT)
901 | (rhs->present * DESC_P_MASK)
902 | (rhs->dpl << DESC_DPL_SHIFT)
903 | (rhs->db << DESC_B_SHIFT)
904 | (rhs->s * DESC_S_MASK)
905 | (rhs->l << DESC_L_SHIFT)
906 | (rhs->g * DESC_G_MASK)
907 | (rhs->avl * DESC_AVL_MASK);
908 }
909
910 void kvm_arch_load_regs(CPUState *env)
911 {
912 struct kvm_regs regs;
913 struct kvm_fpu fpu;
914 struct kvm_sregs sregs;
915 struct kvm_msr_entry msrs[MSR_COUNT];
916 int rc, n, i;
917
918 regs.rax = env->regs[R_EAX];
919 regs.rbx = env->regs[R_EBX];
920 regs.rcx = env->regs[R_ECX];
921 regs.rdx = env->regs[R_EDX];
922 regs.rsi = env->regs[R_ESI];
923 regs.rdi = env->regs[R_EDI];
924 regs.rsp = env->regs[R_ESP];
925 regs.rbp = env->regs[R_EBP];
926 #ifdef TARGET_X86_64
927 regs.r8 = env->regs[8];
928 regs.r9 = env->regs[9];
929 regs.r10 = env->regs[10];
930 regs.r11 = env->regs[11];
931 regs.r12 = env->regs[12];
932 regs.r13 = env->regs[13];
933 regs.r14 = env->regs[14];
934 regs.r15 = env->regs[15];
935 #endif
936
937 regs.rflags = env->eflags;
938 regs.rip = env->eip;
939
940 kvm_set_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
941
942 memset(&fpu, 0, sizeof fpu);
943 fpu.fsw = env->fpus & ~(7 << 11);
944 fpu.fsw |= (env->fpstt & 7) << 11;
945 fpu.fcw = env->fpuc;
946 for (i = 0; i < 8; ++i)
947 fpu.ftwx |= (!env->fptags[i]) << i;
948 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
949 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
950 fpu.mxcsr = env->mxcsr;
951 kvm_set_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
952
953 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
954
955 if ((env->eflags & VM_MASK)) {
956 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
957 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
958 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
959 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
960 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
961 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
962 } else {
963 set_seg(&sregs.cs, &env->segs[R_CS]);
964 set_seg(&sregs.ds, &env->segs[R_DS]);
965 set_seg(&sregs.es, &env->segs[R_ES]);
966 set_seg(&sregs.fs, &env->segs[R_FS]);
967 set_seg(&sregs.gs, &env->segs[R_GS]);
968 set_seg(&sregs.ss, &env->segs[R_SS]);
969
970 if (env->cr[0] & CR0_PE_MASK) {
971 /* force ss cpl to cs cpl */
972 sregs.ss.selector = (sregs.ss.selector & ~3) |
973 (sregs.cs.selector & 3);
974 sregs.ss.dpl = sregs.ss.selector & 3;
975 }
976 }
977
978 set_seg(&sregs.tr, &env->tr);
979 set_seg(&sregs.ldt, &env->ldt);
980
981 sregs.idt.limit = env->idt.limit;
982 sregs.idt.base = env->idt.base;
983 sregs.gdt.limit = env->gdt.limit;
984 sregs.gdt.base = env->gdt.base;
985
986 sregs.cr0 = env->cr[0];
987 sregs.cr2 = env->cr[2];
988 sregs.cr3 = env->cr[3];
989 sregs.cr4 = env->cr[4];
990
991 sregs.cr8 = cpu_get_apic_tpr(env);
992 sregs.apic_base = cpu_get_apic_base(env);
993
994 sregs.efer = env->efer;
995
996 kvm_set_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
997
998 /* msrs */
999 n = 0;
1000 /* Remember to increase MSR_COUNT if you add new registers below */
1001 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1002 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1003 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1004 if (kvm_has_msr_star)
1005 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
1006 if (kvm_has_vm_hsave_pa)
1007 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1008 #ifdef TARGET_X86_64
1009 if (lm_capable_kernel) {
1010 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
1011 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1012 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
1013 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
1014 }
1015 #endif
1016 set_msr_entry(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1017 set_msr_entry(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1018
1019 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1020 if (rc == -1)
1021 perror("kvm_set_msrs FAILED");
1022 }
1023
1024 void kvm_load_tsc(CPUState *env)
1025 {
1026 int rc;
1027 struct kvm_msr_entry msr;
1028
1029 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
1030
1031 rc = kvm_set_msrs(env->kvm_cpu_state.vcpu_ctx, &msr, 1);
1032 if (rc == -1)
1033 perror("kvm_set_tsc FAILED.\n");
1034 }
1035
1036 void kvm_arch_save_mpstate(CPUState *env)
1037 {
1038 #ifdef KVM_CAP_MP_STATE
1039 int r;
1040 struct kvm_mp_state mp_state;
1041
1042 r = kvm_get_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
1043 if (r < 0)
1044 env->mp_state = -1;
1045 else
1046 env->mp_state = mp_state.mp_state;
1047 #endif
1048 }
1049
1050 void kvm_arch_load_mpstate(CPUState *env)
1051 {
1052 #ifdef KVM_CAP_MP_STATE
1053 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1054
1055 /*
1056 * -1 indicates that the host did not support GET_MP_STATE ioctl,
1057 * so don't touch it.
1058 */
1059 if (env->mp_state != -1)
1060 kvm_set_mpstate(env->kvm_cpu_state.vcpu_ctx, &mp_state);
1061 #endif
1062 }
1063
1064 void kvm_arch_save_regs(CPUState *env)
1065 {
1066 struct kvm_regs regs;
1067 struct kvm_fpu fpu;
1068 struct kvm_sregs sregs;
1069 struct kvm_msr_entry msrs[MSR_COUNT];
1070 uint32_t hflags;
1071 uint32_t i, n, rc;
1072
1073 kvm_get_regs(env->kvm_cpu_state.vcpu_ctx, &regs);
1074
1075 env->regs[R_EAX] = regs.rax;
1076 env->regs[R_EBX] = regs.rbx;
1077 env->regs[R_ECX] = regs.rcx;
1078 env->regs[R_EDX] = regs.rdx;
1079 env->regs[R_ESI] = regs.rsi;
1080 env->regs[R_EDI] = regs.rdi;
1081 env->regs[R_ESP] = regs.rsp;
1082 env->regs[R_EBP] = regs.rbp;
1083 #ifdef TARGET_X86_64
1084 env->regs[8] = regs.r8;
1085 env->regs[9] = regs.r9;
1086 env->regs[10] = regs.r10;
1087 env->regs[11] = regs.r11;
1088 env->regs[12] = regs.r12;
1089 env->regs[13] = regs.r13;
1090 env->regs[14] = regs.r14;
1091 env->regs[15] = regs.r15;
1092 #endif
1093
1094 env->eflags = regs.rflags;
1095 env->eip = regs.rip;
1096
1097 kvm_get_fpu(env->kvm_cpu_state.vcpu_ctx, &fpu);
1098 env->fpstt = (fpu.fsw >> 11) & 7;
1099 env->fpus = fpu.fsw;
1100 env->fpuc = fpu.fcw;
1101 for (i = 0; i < 8; ++i)
1102 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1103 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1104 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1105 env->mxcsr = fpu.mxcsr;
1106
1107 kvm_get_sregs(env->kvm_cpu_state.vcpu_ctx, &sregs);
1108
1109 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1110
1111 get_seg(&env->segs[R_CS], &sregs.cs);
1112 get_seg(&env->segs[R_DS], &sregs.ds);
1113 get_seg(&env->segs[R_ES], &sregs.es);
1114 get_seg(&env->segs[R_FS], &sregs.fs);
1115 get_seg(&env->segs[R_GS], &sregs.gs);
1116 get_seg(&env->segs[R_SS], &sregs.ss);
1117
1118 get_seg(&env->tr, &sregs.tr);
1119 get_seg(&env->ldt, &sregs.ldt);
1120
1121 env->idt.limit = sregs.idt.limit;
1122 env->idt.base = sregs.idt.base;
1123 env->gdt.limit = sregs.gdt.limit;
1124 env->gdt.base = sregs.gdt.base;
1125
1126 env->cr[0] = sregs.cr0;
1127 env->cr[2] = sregs.cr2;
1128 env->cr[3] = sregs.cr3;
1129 env->cr[4] = sregs.cr4;
1130
1131 cpu_set_apic_base(env, sregs.apic_base);
1132
1133 env->efer = sregs.efer;
1134 //cpu_set_apic_tpr(env, sregs.cr8);
1135
1136 #define HFLAG_COPY_MASK ~( \
1137 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1138 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1139 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1140 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1141
1142
1143
1144 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1145 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1146 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1147 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1148 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1149 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1150 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1151
1152 if (env->efer & MSR_EFER_LMA) {
1153 hflags |= HF_LMA_MASK;
1154 }
1155
1156 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1157 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1158 } else {
1159 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1160 (DESC_B_SHIFT - HF_CS32_SHIFT);
1161 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1162 (DESC_B_SHIFT - HF_SS32_SHIFT);
1163 if (!(env->cr[0] & CR0_PE_MASK) ||
1164 (env->eflags & VM_MASK) ||
1165 !(hflags & HF_CS32_MASK)) {
1166 hflags |= HF_ADDSEG_MASK;
1167 } else {
1168 hflags |= ((env->segs[R_DS].base |
1169 env->segs[R_ES].base |
1170 env->segs[R_SS].base) != 0) <<
1171 HF_ADDSEG_SHIFT;
1172 }
1173 }
1174 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1175
1176 /* msrs */
1177 n = 0;
1178 /* Remember to increase MSR_COUNT if you add new registers below */
1179 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1180 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1181 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1182 if (kvm_has_msr_star)
1183 msrs[n++].index = MSR_STAR;
1184 msrs[n++].index = MSR_IA32_TSC;
1185 if (kvm_has_vm_hsave_pa)
1186 msrs[n++].index = MSR_VM_HSAVE_PA;
1187 #ifdef TARGET_X86_64
1188 if (lm_capable_kernel) {
1189 msrs[n++].index = MSR_CSTAR;
1190 msrs[n++].index = MSR_KERNELGSBASE;
1191 msrs[n++].index = MSR_FMASK;
1192 msrs[n++].index = MSR_LSTAR;
1193 }
1194 #endif
1195 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1196 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1197
1198 rc = kvm_get_msrs(env->kvm_cpu_state.vcpu_ctx, msrs, n);
1199 if (rc == -1) {
1200 perror("kvm_get_msrs FAILED");
1201 }
1202 else {
1203 n = rc; /* actual number of MSRs */
1204 for (i=0 ; i<n; i++) {
1205 if (get_msr_entry(&msrs[i], env))
1206 return;
1207 }
1208 }
1209 }
1210
1211 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1212 uint32_t count, CPUState *env)
1213 {
1214 env->regs[R_EAX] = function;
1215 env->regs[R_ECX] = count;
1216 qemu_kvm_cpuid_on_env(env);
1217 e->function = function;
1218 e->flags = 0;
1219 e->index = 0;
1220 e->eax = env->regs[R_EAX];
1221 e->ebx = env->regs[R_EBX];
1222 e->ecx = env->regs[R_ECX];
1223 e->edx = env->regs[R_EDX];
1224 }
1225
1226 struct kvm_para_features {
1227 int cap;
1228 int feature;
1229 } para_features[] = {
1230 #ifdef KVM_CAP_CLOCKSOURCE
1231 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1232 #endif
1233 #ifdef KVM_CAP_NOP_IO_DELAY
1234 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1235 #endif
1236 #ifdef KVM_CAP_PV_MMU
1237 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1238 #endif
1239 #ifdef KVM_CAP_CR3_CACHE
1240 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1241 #endif
1242 { -1, -1 }
1243 };
1244
1245 static int get_para_features(kvm_context_t kvm_context)
1246 {
1247 int i, features = 0;
1248
1249 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1250 if (kvm_check_extension(kvm_state, para_features[i].cap))
1251 features |= (1 << para_features[i].feature);
1252 }
1253
1254 return features;
1255 }
1256
1257 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1258 {
1259 int i;
1260 uint32_t mask;
1261
1262 for (i = 0; i < 32; ++i) {
1263 mask = 1U << i;
1264 if ((*features & mask) && !(supported & mask)) {
1265 *features &= ~mask;
1266 }
1267 }
1268 }
1269
1270 int kvm_arch_qemu_init_env(CPUState *cenv)
1271 {
1272 struct kvm_cpuid_entry2 cpuid_ent[100];
1273 #ifdef KVM_CPUID_SIGNATURE
1274 struct kvm_cpuid_entry2 *pv_ent;
1275 uint32_t signature[3];
1276 #endif
1277 int cpuid_nent = 0;
1278 CPUState copy;
1279 uint32_t i, j, limit;
1280
1281 qemu_kvm_load_lapic(cenv);
1282
1283
1284 #ifdef KVM_CPUID_SIGNATURE
1285 /* Paravirtualization CPUIDs */
1286 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1287 pv_ent = &cpuid_ent[cpuid_nent++];
1288 memset(pv_ent, 0, sizeof(*pv_ent));
1289 pv_ent->function = KVM_CPUID_SIGNATURE;
1290 pv_ent->eax = 0;
1291 pv_ent->ebx = signature[0];
1292 pv_ent->ecx = signature[1];
1293 pv_ent->edx = signature[2];
1294
1295 pv_ent = &cpuid_ent[cpuid_nent++];
1296 memset(pv_ent, 0, sizeof(*pv_ent));
1297 pv_ent->function = KVM_CPUID_FEATURES;
1298 pv_ent->eax = get_para_features(kvm_context);
1299 #endif
1300
1301 kvm_trim_features(&cenv->cpuid_features,
1302 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1303
1304 /* prevent the hypervisor bit from being cleared by the kernel */
1305 i = cenv->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
1306 kvm_trim_features(&cenv->cpuid_ext_features,
1307 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1308 cenv->cpuid_ext_features |= i;
1309
1310 kvm_trim_features(&cenv->cpuid_ext2_features,
1311 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1312 kvm_trim_features(&cenv->cpuid_ext3_features,
1313 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1314
1315 copy = *cenv;
1316
1317 copy.regs[R_EAX] = 0;
1318 qemu_kvm_cpuid_on_env(&copy);
1319 limit = copy.regs[R_EAX];
1320
1321 for (i = 0; i <= limit; ++i) {
1322 if (i == 4 || i == 0xb || i == 0xd) {
1323 for (j = 0; ; ++j) {
1324 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1325
1326 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1327 cpuid_ent[cpuid_nent].index = j;
1328
1329 cpuid_nent++;
1330
1331 if (i == 4 && copy.regs[R_EAX] == 0)
1332 break;
1333 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1334 break;
1335 if (i == 0xd && copy.regs[R_EAX] == 0)
1336 break;
1337 }
1338 } else
1339 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1340 }
1341
1342 copy.regs[R_EAX] = 0x80000000;
1343 qemu_kvm_cpuid_on_env(&copy);
1344 limit = copy.regs[R_EAX];
1345
1346 for (i = 0x80000000; i <= limit; ++i)
1347 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1348
1349 kvm_setup_cpuid2(cenv->kvm_cpu_state.vcpu_ctx, cpuid_nent, cpuid_ent);
1350
1351 #ifdef KVM_CAP_MCE
1352 if (((cenv->cpuid_version >> 8)&0xF) >= 6
1353 && (cenv->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
1354 && kvm_check_extension(kvm_state, KVM_CAP_MCE) > 0) {
1355 uint64_t mcg_cap;
1356 int banks;
1357
1358 if (kvm_get_mce_cap_supported(kvm_context, &mcg_cap, &banks))
1359 perror("kvm_get_mce_cap_supported FAILED");
1360 else {
1361 if (banks > MCE_BANKS_DEF)
1362 banks = MCE_BANKS_DEF;
1363 mcg_cap &= MCE_CAP_DEF;
1364 mcg_cap |= banks;
1365 if (kvm_setup_mce(cenv->kvm_cpu_state.vcpu_ctx, &mcg_cap))
1366 perror("kvm_setup_mce FAILED");
1367 else
1368 cenv->mcg_cap = mcg_cap;
1369 }
1370 }
1371 #endif
1372
1373 return 0;
1374 }
1375
1376 int kvm_arch_halt(void *opaque, kvm_vcpu_context_t vcpu)
1377 {
1378 CPUState *env = cpu_single_env;
1379
1380 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1381 (env->eflags & IF_MASK)) &&
1382 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1383 env->halted = 1;
1384 }
1385 return 1;
1386 }
1387
1388 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
1389 {
1390 if (!kvm_irqchip_in_kernel(kvm_context))
1391 kvm_set_cr8(env->kvm_cpu_state.vcpu_ctx, cpu_get_apic_tpr(env));
1392 }
1393
1394 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
1395 {
1396 cpu_single_env = env;
1397
1398 env->eflags = kvm_get_interrupt_flag(env->kvm_cpu_state.vcpu_ctx)
1399 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
1400
1401 cpu_set_apic_tpr(env, kvm_get_cr8(env->kvm_cpu_state.vcpu_ctx));
1402 cpu_set_apic_base(env, kvm_get_apic_base(env->kvm_cpu_state.vcpu_ctx));
1403 }
1404
1405 int kvm_arch_has_work(CPUState *env)
1406 {
1407 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1408 (env->eflags & IF_MASK)) ||
1409 (env->interrupt_request & CPU_INTERRUPT_NMI))
1410 return 1;
1411 return 0;
1412 }
1413
1414 int kvm_arch_try_push_interrupts(void *opaque)
1415 {
1416 CPUState *env = cpu_single_env;
1417 int r, irq;
1418
1419 if (kvm_is_ready_for_interrupt_injection(env->kvm_cpu_state.vcpu_ctx) &&
1420 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1421 (env->eflags & IF_MASK)) {
1422 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1423 irq = cpu_get_pic_interrupt(env);
1424 if (irq >= 0) {
1425 r = kvm_inject_irq(env->kvm_cpu_state.vcpu_ctx, irq);
1426 if (r < 0)
1427 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1428 }
1429 }
1430
1431 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1432 }
1433
1434 #ifdef KVM_CAP_USER_NMI
1435 void kvm_arch_push_nmi(void *opaque)
1436 {
1437 CPUState *env = cpu_single_env;
1438 int r;
1439
1440 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1441 return;
1442
1443 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1444 r = kvm_inject_nmi(env->kvm_cpu_state.vcpu_ctx);
1445 if (r < 0)
1446 printf("cpu %d fail inject NMI\n", env->cpu_index);
1447 }
1448 #endif /* KVM_CAP_USER_NMI */
1449
1450 void kvm_arch_update_regs_for_sipi(CPUState *env)
1451 {
1452 SegmentCache cs = env->segs[R_CS];
1453
1454 kvm_arch_save_regs(env);
1455 env->segs[R_CS] = cs;
1456 env->eip = 0;
1457 kvm_arch_load_regs(env);
1458 }
1459
1460 void kvm_arch_cpu_reset(CPUState *env)
1461 {
1462 kvm_arch_load_regs(env);
1463 if (!cpu_is_bsp(env)) {
1464 if (kvm_irqchip_in_kernel(kvm_context)) {
1465 #ifdef KVM_CAP_MP_STATE
1466 kvm_reset_mpstate(env->kvm_cpu_state.vcpu_ctx);
1467 #endif
1468 } else {
1469 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1470 env->halted = 1;
1471 }
1472 }
1473 }
1474
1475 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1476 {
1477 uint8_t int3 = 0xcc;
1478
1479 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1480 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1481 return -EINVAL;
1482 return 0;
1483 }
1484
1485 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1486 {
1487 uint8_t int3;
1488
1489 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1490 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1491 return -EINVAL;
1492 return 0;
1493 }
1494
1495 #ifdef KVM_CAP_SET_GUEST_DEBUG
1496 static struct {
1497 target_ulong addr;
1498 int len;
1499 int type;
1500 } hw_breakpoint[4];
1501
1502 static int nb_hw_breakpoint;
1503
1504 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1505 {
1506 int n;
1507
1508 for (n = 0; n < nb_hw_breakpoint; n++)
1509 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1510 (hw_breakpoint[n].len == len || len == -1))
1511 return n;
1512 return -1;
1513 }
1514
1515 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1516 target_ulong len, int type)
1517 {
1518 switch (type) {
1519 case GDB_BREAKPOINT_HW:
1520 len = 1;
1521 break;
1522 case GDB_WATCHPOINT_WRITE:
1523 case GDB_WATCHPOINT_ACCESS:
1524 switch (len) {
1525 case 1:
1526 break;
1527 case 2:
1528 case 4:
1529 case 8:
1530 if (addr & (len - 1))
1531 return -EINVAL;
1532 break;
1533 default:
1534 return -EINVAL;
1535 }
1536 break;
1537 default:
1538 return -ENOSYS;
1539 }
1540
1541 if (nb_hw_breakpoint == 4)
1542 return -ENOBUFS;
1543
1544 if (find_hw_breakpoint(addr, len, type) >= 0)
1545 return -EEXIST;
1546
1547 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1548 hw_breakpoint[nb_hw_breakpoint].len = len;
1549 hw_breakpoint[nb_hw_breakpoint].type = type;
1550 nb_hw_breakpoint++;
1551
1552 return 0;
1553 }
1554
1555 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1556 target_ulong len, int type)
1557 {
1558 int n;
1559
1560 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1561 if (n < 0)
1562 return -ENOENT;
1563
1564 nb_hw_breakpoint--;
1565 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1566
1567 return 0;
1568 }
1569
1570 void kvm_arch_remove_all_hw_breakpoints(void)
1571 {
1572 nb_hw_breakpoint = 0;
1573 }
1574
1575 static CPUWatchpoint hw_watchpoint;
1576
1577 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1578 {
1579 int handle = 0;
1580 int n;
1581
1582 if (arch_info->exception == 1) {
1583 if (arch_info->dr6 & (1 << 14)) {
1584 if (cpu_single_env->singlestep_enabled)
1585 handle = 1;
1586 } else {
1587 for (n = 0; n < 4; n++)
1588 if (arch_info->dr6 & (1 << n))
1589 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1590 case 0x0:
1591 handle = 1;
1592 break;
1593 case 0x1:
1594 handle = 1;
1595 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1596 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1597 hw_watchpoint.flags = BP_MEM_WRITE;
1598 break;
1599 case 0x3:
1600 handle = 1;
1601 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1602 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1603 hw_watchpoint.flags = BP_MEM_ACCESS;
1604 break;
1605 }
1606 }
1607 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1608 handle = 1;
1609
1610 if (!handle)
1611 kvm_update_guest_debug(cpu_single_env,
1612 (arch_info->exception == 1) ?
1613 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1614
1615 return handle;
1616 }
1617
1618 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1619 {
1620 const uint8_t type_code[] = {
1621 [GDB_BREAKPOINT_HW] = 0x0,
1622 [GDB_WATCHPOINT_WRITE] = 0x1,
1623 [GDB_WATCHPOINT_ACCESS] = 0x3
1624 };
1625 const uint8_t len_code[] = {
1626 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1627 };
1628 int n;
1629
1630 if (kvm_sw_breakpoints_active(env))
1631 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1632
1633 if (nb_hw_breakpoint > 0) {
1634 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1635 dbg->arch.debugreg[7] = 0x0600;
1636 for (n = 0; n < nb_hw_breakpoint; n++) {
1637 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1638 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1639 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1640 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1641 }
1642 }
1643 }
1644 #endif
1645
1646 void kvm_arch_do_ioperm(void *_data)
1647 {
1648 struct ioperm_data *data = _data;
1649 ioperm(data->start_port, data->num, data->turn_on);
1650 }
1651
1652 /*
1653 * Setup x86 specific IRQ routing
1654 */
1655 int kvm_arch_init_irq_routing(void)
1656 {
1657 int i, r;
1658
1659 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1660 kvm_clear_gsi_routes(kvm_context);
1661 for (i = 0; i < 8; ++i) {
1662 if (i == 2)
1663 continue;
1664 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1665 if (r < 0)
1666 return r;
1667 }
1668 for (i = 8; i < 16; ++i) {
1669 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1670 if (r < 0)
1671 return r;
1672 }
1673 for (i = 0; i < 24; ++i) {
1674 if (i == 0) {
1675 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1676 } else if (i != 2) {
1677 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1678 }
1679 if (r < 0)
1680 return r;
1681 }
1682 kvm_commit_irq_routes(kvm_context);
1683 }
1684 return 0;
1685 }
1686
1687 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1688 int reg)
1689 {
1690 return kvm_get_supported_cpuid(kvm_context, function, reg);
1691 }
1692
1693 void kvm_arch_process_irqchip_events(CPUState *env)
1694 {
1695 kvm_arch_save_regs(env);
1696 if (env->interrupt_request & CPU_INTERRUPT_INIT)
1697 do_cpu_init(env);
1698 if (env->interrupt_request & CPU_INTERRUPT_SIPI)
1699 do_cpu_sipi(env);
1700 kvm_arch_load_regs(env);
1701 }
Patches shipped by Fedora