target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26
  27 #ifdef KVM_UPSTREAM
  28 //#define DEBUG_KVM
  29
  30 #ifdef DEBUG_KVM
  31 #define dprintf(fmt, ...) \
  32     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  33 #else
  34 #define dprintf(fmt, ...) \
  35     do { } while (0)
  36 #endif
  37
  38 #ifdef KVM_CAP_EXT_CPUID
  39
  40 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  41 {
  42     struct kvm_cpuid2 *cpuid;
  43     int r, size;
  44
  45     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  46     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  47     cpuid->nent = max;
  48     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  49     if (r == 0 && cpuid->nent >= max) {
  50         r = -E2BIG;
  51     }
  52     if (r < 0) {
  53         if (r == -E2BIG) {
  54             qemu_free(cpuid);
  55             return NULL;
  56         } else {
  57             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  58                     strerror(-r));
  59             exit(1);
  60         }
  61     }
  62     return cpuid;
  63 }
  64
  65 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  66 {
  67     struct kvm_cpuid2 *cpuid;
  68     int i, max;
  69     uint32_t ret = 0;
  70     uint32_t cpuid_1_edx;
  71
  72     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  73         return -1U;
  74     }
  75
  76     max = 1;
  77     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  78         max *= 2;
  79     }
  80
  81     for (i = 0; i < cpuid->nent; ++i) {
  82         if (cpuid->entries[i].function == function) {
  83             switch (reg) {
  84             case R_EAX:
  85                 ret = cpuid->entries[i].eax;
  86                 break;
  87             case R_EBX:
  88                 ret = cpuid->entries[i].ebx;
  89                 break;
  90             case R_ECX:
  91                 ret = cpuid->entries[i].ecx;
  92                 break;
  93             case R_EDX:
  94                 ret = cpuid->entries[i].edx;
  95                 if (function == 0x80000001) {
  96                     /* On Intel, kvm returns cpuid according to the Intel spec,
  97                      * so add missing bits according to the AMD spec:
  98                      */
  99                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 100                     ret |= cpuid_1_edx & 0xdfeff7ff;
 101                 }
 102                 break;
 103             }
 104         }
 105     }
 106
 107     qemu_free(cpuid);
 108
 109     return ret;
 110 }
 111
 112 #else
 113
 114 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 115 {
 116     return -1U;
 117 }
 118
 119 #endif
 120
 121 static void kvm_trim_features(uint32_t *features, uint32_t supported)
 122 {
 123     int i;
 124     uint32_t mask;
 125
 126     for (i = 0; i < 32; ++i) {
 127         mask = 1U << i;
 128         if ((*features & mask) && !(supported & mask)) {
 129             *features &= ~mask;
 130         }
 131     }
 132 }
 133
 134 int kvm_arch_init_vcpu(CPUState *env)
 135 {
 136     struct {
 137         struct kvm_cpuid2 cpuid;
 138         struct kvm_cpuid_entry2 entries[100];
 139     } __attribute__((packed)) cpuid_data;
 140     uint32_t limit, i, j, cpuid_i;
 141     uint32_t unused;
 142
 143     env->mp_state = KVM_MP_STATE_RUNNABLE;
 144
 145     kvm_trim_features(&env->cpuid_features,
 146         kvm_arch_get_supported_cpuid(env, 1, R_EDX));
 147
 148     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 149     kvm_trim_features(&env->cpuid_ext_features,
 150         kvm_arch_get_supported_cpuid(env, 1, R_ECX));
 151     env->cpuid_ext_features |= i;
 152
 153     kvm_trim_features(&env->cpuid_ext2_features,
 154         kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
 155     kvm_trim_features(&env->cpuid_ext3_features,
 156         kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
 157
 158     cpuid_i = 0;
 159
 160     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 161
 162     for (i = 0; i <= limit; i++) {
 163         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 164
 165         switch (i) {
 166         case 2: {
 167             /* Keep reading function 2 till all the input is received */
 168             int times;
 169
 170             c->function = i;
 171             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 172                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 173             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 174             times = c->eax & 0xff;
 175
 176             for (j = 1; j < times; ++j) {
 177                 c = &cpuid_data.entries[cpuid_i++];
 178                 c->function = i;
 179                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 180                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 181             }
 182             break;
 183         }
 184         case 4:
 185         case 0xb:
 186         case 0xd:
 187             for (j = 0; ; j++) {
 188                 c->function = i;
 189                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 190                 c->index = j;
 191                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 192
 193                 if (i == 4 && c->eax == 0)
 194                     break;
 195                 if (i == 0xb && !(c->ecx & 0xff00))
 196                     break;
 197                 if (i == 0xd && c->eax == 0)
 198                     break;
 199
 200                 c = &cpuid_data.entries[cpuid_i++];
 201             }
 202             break;
 203         default:
 204             c->function = i;
 205             c->flags = 0;
 206             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 207             break;
 208         }
 209     }
 210     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 211
 212     for (i = 0x80000000; i <= limit; i++) {
 213         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 214
 215         c->function = i;
 216         c->flags = 0;
 217         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 218     }
 219
 220     cpuid_data.cpuid.nent = cpuid_i;
 221
 222     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 223 }
 224
 225 static int kvm_has_msr_star(CPUState *env)
 226 {
 227     static int has_msr_star;
 228     int ret;
 229
 230     /* first time */
 231     if (has_msr_star == 0) {
 232         struct kvm_msr_list msr_list, *kvm_msr_list;
 233
 234         has_msr_star = -1;
 235
 236         /* Obtain MSR list from KVM.  These are the MSRs that we must
 237          * save/restore */
 238         msr_list.nmsrs = 0;
 239         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 240         if (ret < 0)
 241             return 0;
 242
 243         /* Old kernel modules had a bug and could write beyond the provided
 244            memory. Allocate at least a safe amount of 1K. */
 245         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 246                                               msr_list.nmsrs *
 247                                               sizeof(msr_list.indices[0])));
 248
 249         kvm_msr_list->nmsrs = msr_list.nmsrs;
 250         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 251         if (ret >= 0) {
 252             int i;
 253
 254             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 255                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 256                     has_msr_star = 1;
 257                     break;
 258                 }
 259             }
 260         }
 261
 262         free(kvm_msr_list);
 263     }
 264
 265     if (has_msr_star == 1)
 266         return 1;
 267     return 0;
 268 }
 269
 270 int kvm_arch_init(KVMState *s, int smp_cpus)
 271 {
 272     int ret;
 273
 274     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 275      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 276      * must be part of guest physical memory, we need to allocate it.  Older
 277      * versions of KVM just assumed that it would be at the end of physical
 278      * memory but that doesn't work with more than 4GB of memory.  We simply
 279      * refuse to work with those older versions of KVM. */
 280     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 281     if (ret <= 0) {
 282         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 283         return ret;
 284     }
 285
 286     /* this address is 3 pages before the bios, and the bios should present
 287      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 288      * this?
 289      */
 290     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 291 }
 292
 293 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 294 {
 295     lhs->selector = rhs->selector;
 296     lhs->base = rhs->base;
 297     lhs->limit = rhs->limit;
 298     lhs->type = 3;
 299     lhs->present = 1;
 300     lhs->dpl = 3;
 301     lhs->db = 0;
 302     lhs->s = 1;
 303     lhs->l = 0;
 304     lhs->g = 0;
 305     lhs->avl = 0;
 306     lhs->unusable = 0;
 307 }
 308
 309 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 310 {
 311     unsigned flags = rhs->flags;
 312     lhs->selector = rhs->selector;
 313     lhs->base = rhs->base;
 314     lhs->limit = rhs->limit;
 315     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 316     lhs->present = (flags & DESC_P_MASK) != 0;
 317     lhs->dpl = rhs->selector & 3;
 318     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 319     lhs->s = (flags & DESC_S_MASK) != 0;
 320     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 321     lhs->g = (flags & DESC_G_MASK) != 0;
 322     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 323     lhs->unusable = 0;
 324 }
 325
 326 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 327 {
 328     lhs->selector = rhs->selector;
 329     lhs->base = rhs->base;
 330     lhs->limit = rhs->limit;
 331     lhs->flags =
 332         (rhs->type << DESC_TYPE_SHIFT)
 333         | (rhs->present * DESC_P_MASK)
 334         | (rhs->dpl << DESC_DPL_SHIFT)
 335         | (rhs->db << DESC_B_SHIFT)
 336         | (rhs->s * DESC_S_MASK)
 337         | (rhs->l << DESC_L_SHIFT)
 338         | (rhs->g * DESC_G_MASK)
 339         | (rhs->avl * DESC_AVL_MASK);
 340 }
 341
 342 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 343 {
 344     if (set)
 345         *kvm_reg = *qemu_reg;
 346     else
 347         *qemu_reg = *kvm_reg;
 348 }
 349
 350 static int kvm_getput_regs(CPUState *env, int set)
 351 {
 352     struct kvm_regs regs;
 353     int ret = 0;
 354
 355     if (!set) {
 356         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 357         if (ret < 0)
 358             return ret;
 359     }
 360
 361     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 362     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 363     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 364     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 365     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 366     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 367     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 368     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 369 #ifdef TARGET_X86_64
 370     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 371     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 372     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 373     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 374     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 375     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 376     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 377     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 378 #endif
 379
 380     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 381     kvm_getput_reg(&regs.rip, &env->eip, set);
 382
 383     if (set)
 384         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 385
 386     return ret;
 387 }
 388
 389 static int kvm_put_fpu(CPUState *env)
 390 {
 391     struct kvm_fpu fpu;
 392     int i;
 393
 394     memset(&fpu, 0, sizeof fpu);
 395     fpu.fsw = env->fpus & ~(7 << 11);
 396     fpu.fsw |= (env->fpstt & 7) << 11;
 397     fpu.fcw = env->fpuc;
 398     for (i = 0; i < 8; ++i)
 399         fpu.ftwx |= (!env->fptags[i]) << i;
 400     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 401     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 402     fpu.mxcsr = env->mxcsr;
 403
 404     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 405 }
 406
 407 static int kvm_put_sregs(CPUState *env)
 408 {
 409     struct kvm_sregs sregs;
 410
 411     memcpy(sregs.interrupt_bitmap,
 412            env->interrupt_bitmap,
 413            sizeof(sregs.interrupt_bitmap));
 414
 415     if ((env->eflags & VM_MASK)) {
 416             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 417             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 418             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 419             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 420             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 421             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 422     } else {
 423             set_seg(&sregs.cs, &env->segs[R_CS]);
 424             set_seg(&sregs.ds, &env->segs[R_DS]);
 425             set_seg(&sregs.es, &env->segs[R_ES]);
 426             set_seg(&sregs.fs, &env->segs[R_FS]);
 427             set_seg(&sregs.gs, &env->segs[R_GS]);
 428             set_seg(&sregs.ss, &env->segs[R_SS]);
 429
 430             if (env->cr[0] & CR0_PE_MASK) {
 431                 /* force ss cpl to cs cpl */
 432                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 433                         (sregs.cs.selector & 3);
 434                 sregs.ss.dpl = sregs.ss.selector & 3;
 435             }
 436     }
 437
 438     set_seg(&sregs.tr, &env->tr);
 439     set_seg(&sregs.ldt, &env->ldt);
 440
 441     sregs.idt.limit = env->idt.limit;
 442     sregs.idt.base = env->idt.base;
 443     sregs.gdt.limit = env->gdt.limit;
 444     sregs.gdt.base = env->gdt.base;
 445
 446     sregs.cr0 = env->cr[0];
 447     sregs.cr2 = env->cr[2];
 448     sregs.cr3 = env->cr[3];
 449     sregs.cr4 = env->cr[4];
 450
 451     sregs.cr8 = cpu_get_apic_tpr(env);
 452     sregs.apic_base = cpu_get_apic_base(env);
 453
 454     sregs.efer = env->efer;
 455
 456     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 457 }
 458
 459 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 460                               uint32_t index, uint64_t value)
 461 {
 462     entry->index = index;
 463     entry->data = value;
 464 }
 465
 466 static int kvm_put_msrs(CPUState *env)
 467 {
 468     struct {
 469         struct kvm_msrs info;
 470         struct kvm_msr_entry entries[100];
 471     } msr_data;
 472     struct kvm_msr_entry *msrs = msr_data.entries;
 473     int n = 0;
 474
 475     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 476     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 477     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 478     if (kvm_has_msr_star(env))
 479         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 480     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 481     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 482 #ifdef TARGET_X86_64
 483     /* FIXME if lm capable */
 484     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 485     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 486     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 487     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 488 #endif
 489     msr_data.info.nmsrs = n;
 490
 491     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 492
 493 }
 494
 495
 496 static int kvm_get_fpu(CPUState *env)
 497 {
 498     struct kvm_fpu fpu;
 499     int i, ret;
 500
 501     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 502     if (ret < 0)
 503         return ret;
 504
 505     env->fpstt = (fpu.fsw >> 11) & 7;
 506     env->fpus = fpu.fsw;
 507     env->fpuc = fpu.fcw;
 508     for (i = 0; i < 8; ++i)
 509         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 510     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 511     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 512     env->mxcsr = fpu.mxcsr;
 513
 514     return 0;
 515 }
 516
 517 static int kvm_get_sregs(CPUState *env)
 518 {
 519     struct kvm_sregs sregs;
 520     uint32_t hflags;
 521     int ret;
 522
 523     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 524     if (ret < 0)
 525         return ret;
 526
 527     memcpy(env->interrupt_bitmap,
 528            sregs.interrupt_bitmap,
 529            sizeof(sregs.interrupt_bitmap));
 530
 531     get_seg(&env->segs[R_CS], &sregs.cs);
 532     get_seg(&env->segs[R_DS], &sregs.ds);
 533     get_seg(&env->segs[R_ES], &sregs.es);
 534     get_seg(&env->segs[R_FS], &sregs.fs);
 535     get_seg(&env->segs[R_GS], &sregs.gs);
 536     get_seg(&env->segs[R_SS], &sregs.ss);
 537
 538     get_seg(&env->tr, &sregs.tr);
 539     get_seg(&env->ldt, &sregs.ldt);
 540
 541     env->idt.limit = sregs.idt.limit;
 542     env->idt.base = sregs.idt.base;
 543     env->gdt.limit = sregs.gdt.limit;
 544     env->gdt.base = sregs.gdt.base;
 545
 546     env->cr[0] = sregs.cr0;
 547     env->cr[2] = sregs.cr2;
 548     env->cr[3] = sregs.cr3;
 549     env->cr[4] = sregs.cr4;
 550
 551     cpu_set_apic_base(env, sregs.apic_base);
 552
 553     env->efer = sregs.efer;
 554     //cpu_set_apic_tpr(env, sregs.cr8);
 555
 556 #define HFLAG_COPY_MASK ~( \
 557                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 558                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 559                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 560                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 561
 562
 563
 564     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 565     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 566     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 567             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 568     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 569     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 570             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 571
 572     if (env->efer & MSR_EFER_LMA) {
 573         hflags |= HF_LMA_MASK;
 574     }
 575
 576     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 577         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 578     } else {
 579         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 580                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 581         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 582                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 583         if (!(env->cr[0] & CR0_PE_MASK) ||
 584                    (env->eflags & VM_MASK) ||
 585                    !(hflags & HF_CS32_MASK)) {
 586                 hflags |= HF_ADDSEG_MASK;
 587             } else {
 588                 hflags |= ((env->segs[R_DS].base |
 589                                 env->segs[R_ES].base |
 590                                 env->segs[R_SS].base) != 0) <<
 591                     HF_ADDSEG_SHIFT;
 592             }
 593     }
 594     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 595
 596     return 0;
 597 }
 598
 599 static int kvm_get_msrs(CPUState *env)
 600 {
 601     struct {
 602         struct kvm_msrs info;
 603         struct kvm_msr_entry entries[100];
 604     } msr_data;
 605     struct kvm_msr_entry *msrs = msr_data.entries;
 606     int ret, i, n;
 607
 608     n = 0;
 609     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 610     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 611     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 612     if (kvm_has_msr_star(env))
 613         msrs[n++].index = MSR_STAR;
 614     msrs[n++].index = MSR_IA32_TSC;
 615     msrs[n++].index = MSR_VM_HSAVE_PA;
 616 #ifdef TARGET_X86_64
 617     /* FIXME lm_capable_kernel */
 618     msrs[n++].index = MSR_CSTAR;
 619     msrs[n++].index = MSR_KERNELGSBASE;
 620     msrs[n++].index = MSR_FMASK;
 621     msrs[n++].index = MSR_LSTAR;
 622 #endif
 623     msr_data.info.nmsrs = n;
 624     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 625     if (ret < 0)
 626         return ret;
 627
 628     for (i = 0; i < ret; i++) {
 629         switch (msrs[i].index) {
 630         case MSR_IA32_SYSENTER_CS:
 631             env->sysenter_cs = msrs[i].data;
 632             break;
 633         case MSR_IA32_SYSENTER_ESP:
 634             env->sysenter_esp = msrs[i].data;
 635             break;
 636         case MSR_IA32_SYSENTER_EIP:
 637             env->sysenter_eip = msrs[i].data;
 638             break;
 639         case MSR_STAR:
 640             env->star = msrs[i].data;
 641             break;
 642 #ifdef TARGET_X86_64
 643         case MSR_CSTAR:
 644             env->cstar = msrs[i].data;
 645             break;
 646         case MSR_KERNELGSBASE:
 647             env->kernelgsbase = msrs[i].data;
 648             break;
 649         case MSR_FMASK:
 650             env->fmask = msrs[i].data;
 651             break;
 652         case MSR_LSTAR:
 653             env->lstar = msrs[i].data;
 654             break;
 655 #endif
 656         case MSR_IA32_TSC:
 657             env->tsc = msrs[i].data;
 658             break;
 659         case MSR_VM_HSAVE_PA:
 660             env->vm_hsave = msrs[i].data;
 661             break;
 662         }
 663     }
 664
 665     return 0;
 666 }
 667
 668 int kvm_arch_put_registers(CPUState *env)
 669 {
 670     int ret;
 671
 672     ret = kvm_getput_regs(env, 1);
 673     if (ret < 0)
 674         return ret;
 675
 676     ret = kvm_put_fpu(env);
 677     if (ret < 0)
 678         return ret;
 679
 680     ret = kvm_put_sregs(env);
 681     if (ret < 0)
 682         return ret;
 683
 684     ret = kvm_put_msrs(env);
 685     if (ret < 0)
 686         return ret;
 687
 688     ret = kvm_put_mp_state(env);
 689     if (ret < 0)
 690         return ret;
 691
 692     ret = kvm_get_mp_state(env);
 693     if (ret < 0)
 694         return ret;
 695
 696     return 0;
 697 }
 698
 699 int kvm_arch_get_registers(CPUState *env)
 700 {
 701     int ret;
 702
 703     ret = kvm_getput_regs(env, 0);
 704     if (ret < 0)
 705         return ret;
 706
 707     ret = kvm_get_fpu(env);
 708     if (ret < 0)
 709         return ret;
 710
 711     ret = kvm_get_sregs(env);
 712     if (ret < 0)
 713         return ret;
 714
 715     ret = kvm_get_msrs(env);
 716     if (ret < 0)
 717         return ret;
 718
 719     return 0;
 720 }
 721
 722 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 723 {
 724     /* Try to inject an interrupt if the guest can accept it */
 725     if (run->ready_for_interrupt_injection &&
 726         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 727         (env->eflags & IF_MASK)) {
 728         int irq;
 729
 730         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 731         irq = cpu_get_pic_interrupt(env);
 732         if (irq >= 0) {
 733             struct kvm_interrupt intr;
 734             intr.irq = irq;
 735             /* FIXME: errors */
 736             dprintf("injected interrupt %d\n", irq);
 737             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 738         }
 739     }
 740
 741     /* If we have an interrupt but the guest is not ready to receive an
 742      * interrupt, request an interrupt window exit.  This will
 743      * cause a return to userspace as soon as the guest is ready to
 744      * receive interrupts. */
 745     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 746         run->request_interrupt_window = 1;
 747     else
 748         run->request_interrupt_window = 0;
 749
 750     dprintf("setting tpr\n");
 751     run->cr8 = cpu_get_apic_tpr(env);
 752
 753     return 0;
 754 }
 755
 756 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 757 {
 758     if (run->if_flag)
 759         env->eflags |= IF_MASK;
 760     else
 761         env->eflags &= ~IF_MASK;
 762
 763     cpu_set_apic_tpr(env, run->cr8);
 764     cpu_set_apic_base(env, run->apic_base);
 765
 766     return 0;
 767 }
 768
 769 static int kvm_handle_halt(CPUState *env)
 770 {
 771     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 772           (env->eflags & IF_MASK)) &&
 773         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 774         env->halted = 1;
 775         env->exception_index = EXCP_HLT;
 776         return 0;
 777     }
 778
 779     return 1;
 780 }
 781
 782 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 783 {
 784     int ret = 0;
 785
 786     switch (run->exit_reason) {
 787     case KVM_EXIT_HLT:
 788         dprintf("handle_hlt\n");
 789         ret = kvm_handle_halt(env);
 790         break;
 791     }
 792
 793     return ret;
 794 }
 795
 796 #ifdef KVM_CAP_SET_GUEST_DEBUG
 797 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 798 {
 799     const static uint8_t int3 = 0xcc;
 800
 801     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 802         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 803         return -EINVAL;
 804     return 0;
 805 }
 806
 807 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 808 {
 809     uint8_t int3;
 810
 811     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 812         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 813         return -EINVAL;
 814     return 0;
 815 }
 816
 817 static struct {
 818     target_ulong addr;
 819     int len;
 820     int type;
 821 } hw_breakpoint[4];
 822
 823 static int nb_hw_breakpoint;
 824
 825 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 826 {
 827     int n;
 828
 829     for (n = 0; n < nb_hw_breakpoint; n++)
 830         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 831             (hw_breakpoint[n].len == len || len == -1))
 832             return n;
 833     return -1;
 834 }
 835
 836 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 837                                   target_ulong len, int type)
 838 {
 839     switch (type) {
 840     case GDB_BREAKPOINT_HW:
 841         len = 1;
 842         break;
 843     case GDB_WATCHPOINT_WRITE:
 844     case GDB_WATCHPOINT_ACCESS:
 845         switch (len) {
 846         case 1:
 847             break;
 848         case 2:
 849         case 4:
 850         case 8:
 851             if (addr & (len - 1))
 852                 return -EINVAL;
 853             break;
 854         default:
 855             return -EINVAL;
 856         }
 857         break;
 858     default:
 859         return -ENOSYS;
 860     }
 861
 862     if (nb_hw_breakpoint == 4)
 863         return -ENOBUFS;
 864
 865     if (find_hw_breakpoint(addr, len, type) >= 0)
 866         return -EEXIST;
 867
 868     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 869     hw_breakpoint[nb_hw_breakpoint].len = len;
 870     hw_breakpoint[nb_hw_breakpoint].type = type;
 871     nb_hw_breakpoint++;
 872
 873     return 0;
 874 }
 875
 876 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 877                                   target_ulong len, int type)
 878 {
 879     int n;
 880
 881     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 882     if (n < 0)
 883         return -ENOENT;
 884
 885     nb_hw_breakpoint--;
 886     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 887
 888     return 0;
 889 }
 890
 891 void kvm_arch_remove_all_hw_breakpoints(void)
 892 {
 893     nb_hw_breakpoint = 0;
 894 }
 895
 896 static CPUWatchpoint hw_watchpoint;
 897
 898 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 899 {
 900     int handle = 0;
 901     int n;
 902
 903     if (arch_info->exception == 1) {
 904         if (arch_info->dr6 & (1 << 14)) {
 905             if (cpu_single_env->singlestep_enabled)
 906                 handle = 1;
 907         } else {
 908             for (n = 0; n < 4; n++)
 909                 if (arch_info->dr6 & (1 << n))
 910                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 911                     case 0x0:
 912                         handle = 1;
 913                         break;
 914                     case 0x1:
 915                         handle = 1;
 916                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 917                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 918                         hw_watchpoint.flags = BP_MEM_WRITE;
 919                         break;
 920                     case 0x3:
 921                         handle = 1;
 922                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 923                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 924                         hw_watchpoint.flags = BP_MEM_ACCESS;
 925                         break;
 926                     }
 927         }
 928     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
 929         handle = 1;
 930
 931     if (!handle)
 932         kvm_update_guest_debug(cpu_single_env,
 933                         (arch_info->exception == 1) ?
 934                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 935
 936     return handle;
 937 }
 938
 939 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 940 {
 941     const uint8_t type_code[] = {
 942         [GDB_BREAKPOINT_HW] = 0x0,
 943         [GDB_WATCHPOINT_WRITE] = 0x1,
 944         [GDB_WATCHPOINT_ACCESS] = 0x3
 945     };
 946     const uint8_t len_code[] = {
 947         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 948     };
 949     int n;
 950
 951     if (kvm_sw_breakpoints_active(env))
 952         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 953
 954     if (nb_hw_breakpoint > 0) {
 955         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 956         dbg->arch.debugreg[7] = 0x0600;
 957         for (n = 0; n < nb_hw_breakpoint; n++) {
 958             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 959             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 960                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 961                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 962         }
 963     }
 964 }
 965 #endif /* KVM_CAP_SET_GUEST_DEBUG */
 966 #endif
 967
 968 #include "qemu-kvm-x86.c"