target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/pc.h"
   4 #include "hw/isa.h"
   5
   6 #include "exec-all.h"
   7 #include "qemu-kvm.h"
   8
   9 void register_machines(void)
  10 {
  11     qemu_register_machine(&pc_machine);
  12     qemu_register_machine(&isapc_machine);
  13 }
  14
  15 static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
  16 {
  17     qemu_put_be32(f, dt->selector);
  18     qemu_put_betl(f, dt->base);
  19     qemu_put_be32(f, dt->limit);
  20     qemu_put_be32(f, dt->flags);
  21 }
  22
  23 static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
  24 {
  25     dt->selector = qemu_get_be32(f);
  26     dt->base = qemu_get_betl(f);
  27     dt->limit = qemu_get_be32(f);
  28     dt->flags = qemu_get_be32(f);
  29 }
  30
  31 void cpu_save(QEMUFile *f, void *opaque)
  32 {
  33     CPUState *env = opaque;
  34     uint16_t fptag, fpus, fpuc, fpregs_format;
  35     uint32_t hflags;
  36     int32_t a20_mask;
  37     int i;
  38
  39     if (kvm_enabled()) {
  40         kvm_save_registers(env);
  41         kvm_save_mpstate(env);
  42     }
  43
  44     for(i = 0; i < CPU_NB_REGS; i++)
  45         qemu_put_betls(f, &env->regs[i]);
  46     qemu_put_betls(f, &env->eip);
  47     qemu_put_betls(f, &env->eflags);
  48     hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
  49     qemu_put_be32s(f, &hflags);
  50
  51     /* FPU */
  52     fpuc = env->fpuc;
  53     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
  54     fptag = 0;
  55     for(i = 0; i < 8; i++) {
  56         fptag |= ((!env->fptags[i]) << i);
  57     }
  58
  59     qemu_put_be16s(f, &fpuc);
  60     qemu_put_be16s(f, &fpus);
  61     qemu_put_be16s(f, &fptag);
  62
  63 #ifdef USE_X86LDOUBLE
  64     fpregs_format = 0;
  65 #else
  66     fpregs_format = 1;
  67 #endif
  68     qemu_put_be16s(f, &fpregs_format);
  69
  70     for(i = 0; i < 8; i++) {
  71 #ifdef USE_X86LDOUBLE
  72         {
  73             uint64_t mant;
  74             uint16_t exp;
  75             /* we save the real CPU data (in case of MMX usage only 'mant'
  76                contains the MMX register */
  77             cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
  78             qemu_put_be64(f, mant);
  79             qemu_put_be16(f, exp);
  80         }
  81 #else
  82         /* if we use doubles for float emulation, we save the doubles to
  83            avoid losing information in case of MMX usage. It can give
  84            problems if the image is restored on a CPU where long
  85            doubles are used instead. */
  86         qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
  87 #endif
  88     }
  89
  90     for(i = 0; i < 6; i++)
  91         cpu_put_seg(f, &env->segs[i]);
  92     cpu_put_seg(f, &env->ldt);
  93     cpu_put_seg(f, &env->tr);
  94     cpu_put_seg(f, &env->gdt);
  95     cpu_put_seg(f, &env->idt);
  96
  97     qemu_put_be32s(f, &env->sysenter_cs);
  98     qemu_put_betls(f, &env->sysenter_esp);
  99     qemu_put_betls(f, &env->sysenter_eip);
 100
 101     qemu_put_betls(f, &env->cr[0]);
 102     qemu_put_betls(f, &env->cr[2]);
 103     qemu_put_betls(f, &env->cr[3]);
 104     qemu_put_betls(f, &env->cr[4]);
 105
 106     for(i = 0; i < 8; i++)
 107         qemu_put_betls(f, &env->dr[i]);
 108
 109     /* MMU */
 110     a20_mask = (int32_t) env->a20_mask;
 111     qemu_put_sbe32s(f, &a20_mask);
 112
 113     /* XMM */
 114     qemu_put_be32s(f, &env->mxcsr);
 115     for(i = 0; i < CPU_NB_REGS; i++) {
 116         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 117         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 118     }
 119
 120 #ifdef TARGET_X86_64
 121     qemu_put_be64s(f, &env->efer);
 122     qemu_put_be64s(f, &env->star);
 123     qemu_put_be64s(f, &env->lstar);
 124     qemu_put_be64s(f, &env->cstar);
 125     qemu_put_be64s(f, &env->fmask);
 126     qemu_put_be64s(f, &env->kernelgsbase);
 127 #endif
 128     qemu_put_be32s(f, &env->smbase);
 129     qemu_put_be64s(f, &env->pat);
 130     qemu_put_be32s(f, &env->hflags2);
 131
 132     qemu_put_be64s(f, &env->vm_hsave);
 133     qemu_put_be64s(f, &env->vm_vmcb);
 134     qemu_put_be64s(f, &env->tsc_offset);
 135     qemu_put_be64s(f, &env->intercept);
 136     qemu_put_be16s(f, &env->intercept_cr_read);
 137     qemu_put_be16s(f, &env->intercept_cr_write);
 138     qemu_put_be16s(f, &env->intercept_dr_read);
 139     qemu_put_be16s(f, &env->intercept_dr_write);
 140     qemu_put_be32s(f, &env->intercept_exceptions);
 141     qemu_put_8s(f, &env->v_tpr);
 142
 143     /* MTRRs */
 144     for(i = 0; i < 11; i++)
 145         qemu_put_be64s(f, &env->mtrr_fixed[i]);
 146     qemu_put_be64s(f, &env->mtrr_deftype);
 147     for(i = 0; i < 8; i++) {
 148         qemu_put_be64s(f, &env->mtrr_var[i].base);
 149         qemu_put_be64s(f, &env->mtrr_var[i].mask);
 150     }
 151
 152     if (kvm_enabled()) {
 153         for (i = 0; i < sizeof(env->interrupt_bitmap)/8 ; i++) {
 154             qemu_put_be64s(f, &env->interrupt_bitmap[i]);
 155         }
 156         qemu_put_be64s(f, &env->tsc);
 157         qemu_put_be32s(f, &env->mp_state);
 158     }
 159 }
 160
 161 #ifdef USE_X86LDOUBLE
 162 /* XXX: add that in a FPU generic layer */
 163 union x86_longdouble {
 164     uint64_t mant;
 165     uint16_t exp;
 166 };
 167
 168 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
 169 #define EXPBIAS1 1023
 170 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
 171 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
 172
 173 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
 174 {
 175     int e;
 176     /* mantissa */
 177     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 178     /* exponent + sign */
 179     e = EXPD1(temp) - EXPBIAS1 + 16383;
 180     e |= SIGND1(temp) >> 16;
 181     p->exp = e;
 182 }
 183 #endif
 184
 185 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 186 {
 187     CPUState *env = opaque;
 188     int i, guess_mmx;
 189     uint32_t hflags;
 190     uint16_t fpus, fpuc, fptag, fpregs_format;
 191     int32_t a20_mask;
 192
 193     if (version_id != 3 && version_id != 4 && version_id != 5
 194         && version_id != 6 && version_id != 7 && version_id != 8)
 195         return -EINVAL;
 196     for(i = 0; i < CPU_NB_REGS; i++)
 197         qemu_get_betls(f, &env->regs[i]);
 198     qemu_get_betls(f, &env->eip);
 199     qemu_get_betls(f, &env->eflags);
 200     qemu_get_be32s(f, &hflags);
 201
 202     qemu_get_be16s(f, &fpuc);
 203     qemu_get_be16s(f, &fpus);
 204     qemu_get_be16s(f, &fptag);
 205     qemu_get_be16s(f, &fpregs_format);
 206
 207     /* NOTE: we cannot always restore the FPU state if the image come
 208        from a host with a different 'USE_X86LDOUBLE' define. We guess
 209        if we are in an MMX state to restore correctly in that case. */
 210     guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
 211     for(i = 0; i < 8; i++) {
 212         uint64_t mant;
 213         uint16_t exp;
 214
 215         switch(fpregs_format) {
 216         case 0:
 217             mant = qemu_get_be64(f);
 218             exp = qemu_get_be16(f);
 219 #ifdef USE_X86LDOUBLE
 220             env->fpregs[i].d = cpu_set_fp80(mant, exp);
 221 #else
 222             /* difficult case */
 223             if (guess_mmx)
 224                 env->fpregs[i].mmx.MMX_Q(0) = mant;
 225             else
 226                 env->fpregs[i].d = cpu_set_fp80(mant, exp);
 227 #endif
 228             break;
 229         case 1:
 230             mant = qemu_get_be64(f);
 231 #ifdef USE_X86LDOUBLE
 232             {
 233                 union x86_longdouble *p;
 234                 /* difficult case */
 235                 p = (void *)&env->fpregs[i];
 236                 if (guess_mmx) {
 237                     p->mant = mant;
 238                     p->exp = 0xffff;
 239                 } else {
 240                     fp64_to_fp80(p, mant);
 241                 }
 242             }
 243 #else
 244             env->fpregs[i].mmx.MMX_Q(0) = mant;
 245 #endif
 246             break;
 247         default:
 248             return -EINVAL;
 249         }
 250     }
 251
 252     env->fpuc = fpuc;
 253     /* XXX: restore FPU round state */
 254     env->fpstt = (fpus >> 11) & 7;
 255     env->fpus = fpus & ~0x3800;
 256     fptag ^= 0xff;
 257     for(i = 0; i < 8; i++) {
 258         env->fptags[i] = (fptag >> i) & 1;
 259     }
 260
 261     for(i = 0; i < 6; i++)
 262         cpu_get_seg(f, &env->segs[i]);
 263     cpu_get_seg(f, &env->ldt);
 264     cpu_get_seg(f, &env->tr);
 265     cpu_get_seg(f, &env->gdt);
 266     cpu_get_seg(f, &env->idt);
 267
 268     qemu_get_be32s(f, &env->sysenter_cs);
 269     if (version_id >= 7) {
 270         qemu_get_betls(f, &env->sysenter_esp);
 271         qemu_get_betls(f, &env->sysenter_eip);
 272     } else {
 273         env->sysenter_esp = qemu_get_be32(f);
 274         env->sysenter_eip = qemu_get_be32(f);
 275     }
 276
 277     qemu_get_betls(f, &env->cr[0]);
 278     qemu_get_betls(f, &env->cr[2]);
 279     qemu_get_betls(f, &env->cr[3]);
 280     qemu_get_betls(f, &env->cr[4]);
 281
 282     for(i = 0; i < 8; i++)
 283         qemu_get_betls(f, &env->dr[i]);
 284     cpu_breakpoint_remove_all(env, BP_CPU);
 285     cpu_watchpoint_remove_all(env, BP_CPU);
 286     for (i = 0; i < 4; i++)
 287         hw_breakpoint_insert(env, i);
 288
 289     /* MMU */
 290     qemu_get_sbe32s(f, &a20_mask);
 291     env->a20_mask = a20_mask;
 292
 293     qemu_get_be32s(f, &env->mxcsr);
 294     for(i = 0; i < CPU_NB_REGS; i++) {
 295         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 296         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 297     }
 298
 299 #ifdef TARGET_X86_64
 300     qemu_get_be64s(f, &env->efer);
 301     qemu_get_be64s(f, &env->star);
 302     qemu_get_be64s(f, &env->lstar);
 303     qemu_get_be64s(f, &env->cstar);
 304     qemu_get_be64s(f, &env->fmask);
 305     qemu_get_be64s(f, &env->kernelgsbase);
 306 #endif
 307     if (version_id >= 4) {
 308         qemu_get_be32s(f, &env->smbase);
 309     }
 310     if (version_id >= 5) {
 311         qemu_get_be64s(f, &env->pat);
 312         qemu_get_be32s(f, &env->hflags2);
 313         if (version_id < 6)
 314             qemu_get_be32s(f, &env->halted);
 315
 316         qemu_get_be64s(f, &env->vm_hsave);
 317         qemu_get_be64s(f, &env->vm_vmcb);
 318         qemu_get_be64s(f, &env->tsc_offset);
 319         qemu_get_be64s(f, &env->intercept);
 320         qemu_get_be16s(f, &env->intercept_cr_read);
 321         qemu_get_be16s(f, &env->intercept_cr_write);
 322         qemu_get_be16s(f, &env->intercept_dr_read);
 323         qemu_get_be16s(f, &env->intercept_dr_write);
 324         qemu_get_be32s(f, &env->intercept_exceptions);
 325         qemu_get_8s(f, &env->v_tpr);
 326     }
 327
 328     if (version_id >= 8) {
 329         /* MTRRs */
 330         for(i = 0; i < 11; i++)
 331             qemu_get_be64s(f, &env->mtrr_fixed[i]);
 332         qemu_get_be64s(f, &env->mtrr_deftype);
 333         for(i = 0; i < 8; i++) {
 334             qemu_get_be64s(f, &env->mtrr_var[i].base);
 335             qemu_get_be64s(f, &env->mtrr_var[i].mask);
 336         }
 337     }
 338
 339     /* XXX: ensure compatiblity for halted bit ? */
 340     /* XXX: compute redundant hflags bits */
 341     env->hflags = hflags;
 342     tlb_flush(env, 1);
 343     if (kvm_enabled()) {
 344         /* when in-kernel irqchip is used, env->halted causes deadlock
 345            because no userspace IRQs will ever clear this flag */
 346         env->halted = 0;
 347         for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
 348             qemu_get_be64s(f, &env->interrupt_bitmap[i]);
 349         }
 350         qemu_get_be64s(f, &env->tsc);
 351         kvm_load_registers(env);
 352         kvm_load_tsc(env);
 353         if (version_id >= 5) {
 354             qemu_get_be32s(f, &env->mp_state);
 355             kvm_load_mpstate(env);
 356         }
 357     }
 358     return 0;
 359 }