target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/pc.h"
   4 #include "hw/isa.h"
   5 #include "host-utils.h"
   6
   7 #include "exec-all.h"
   8 #include "kvm.h"
   9 #include "qemu-kvm.h"
  10
  11 static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
  12 {
  13     qemu_put_be32(f, dt->selector);
  14     qemu_put_betl(f, dt->base);
  15     qemu_put_be32(f, dt->limit);
  16     qemu_put_be32(f, dt->flags);
  17 }
  18
  19 static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
  20 {
  21     dt->selector = qemu_get_be32(f);
  22     dt->base = qemu_get_betl(f);
  23     dt->limit = qemu_get_be32(f);
  24     dt->flags = qemu_get_be32(f);
  25 }
  26
  27 void cpu_save(QEMUFile *f, void *opaque)
  28 {
  29     CPUState *env = opaque;
  30     uint16_t fptag, fpus, fpuc, fpregs_format;
  31     uint32_t hflags;
  32     int32_t a20_mask;
  33     int32_t pending_irq;
  34     int i, bit;
  35
  36     if (kvm_enabled()) {
  37         kvm_save_registers(env);
  38         kvm_arch_save_mpstate(env);
  39     }
  40
  41     for(i = 0; i < CPU_NB_REGS; i++)
  42         qemu_put_betls(f, &env->regs[i]);
  43     qemu_put_betls(f, &env->eip);
  44     qemu_put_betls(f, &env->eflags);
  45     hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
  46     qemu_put_be32s(f, &hflags);
  47
  48     /* FPU */
  49     fpuc = env->fpuc;
  50     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
  51     fptag = 0;
  52     for(i = 0; i < 8; i++) {
  53         fptag |= ((!env->fptags[i]) << i);
  54     }
  55
  56     qemu_put_be16s(f, &fpuc);
  57     qemu_put_be16s(f, &fpus);
  58     qemu_put_be16s(f, &fptag);
  59
  60 #ifdef USE_X86LDOUBLE
  61     fpregs_format = 0;
  62 #else
  63     fpregs_format = 1;
  64 #endif
  65     qemu_put_be16s(f, &fpregs_format);
  66
  67     for(i = 0; i < 8; i++) {
  68 #ifdef USE_X86LDOUBLE
  69         {
  70             uint64_t mant;
  71             uint16_t exp;
  72             /* we save the real CPU data (in case of MMX usage only 'mant'
  73                contains the MMX register */
  74             cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
  75             qemu_put_be64(f, mant);
  76             qemu_put_be16(f, exp);
  77         }
  78 #else
  79         /* if we use doubles for float emulation, we save the doubles to
  80            avoid losing information in case of MMX usage. It can give
  81            problems if the image is restored on a CPU where long
  82            doubles are used instead. */
  83         qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
  84 #endif
  85     }
  86
  87     for(i = 0; i < 6; i++)
  88         cpu_put_seg(f, &env->segs[i]);
  89     cpu_put_seg(f, &env->ldt);
  90     cpu_put_seg(f, &env->tr);
  91     cpu_put_seg(f, &env->gdt);
  92     cpu_put_seg(f, &env->idt);
  93
  94     qemu_put_be32s(f, &env->sysenter_cs);
  95     qemu_put_betls(f, &env->sysenter_esp);
  96     qemu_put_betls(f, &env->sysenter_eip);
  97
  98     qemu_put_betls(f, &env->cr[0]);
  99     qemu_put_betls(f, &env->cr[2]);
 100     qemu_put_betls(f, &env->cr[3]);
 101     qemu_put_betls(f, &env->cr[4]);
 102
 103     for(i = 0; i < 8; i++)
 104         qemu_put_betls(f, &env->dr[i]);
 105
 106     /* MMU */
 107     a20_mask = (int32_t) env->a20_mask;
 108     qemu_put_sbe32s(f, &a20_mask);
 109
 110     /* XMM */
 111     qemu_put_be32s(f, &env->mxcsr);
 112     for(i = 0; i < CPU_NB_REGS; i++) {
 113         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 114         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 115     }
 116
 117 #ifdef TARGET_X86_64
 118     qemu_put_be64s(f, &env->efer);
 119     qemu_put_be64s(f, &env->star);
 120     qemu_put_be64s(f, &env->lstar);
 121     qemu_put_be64s(f, &env->cstar);
 122     qemu_put_be64s(f, &env->fmask);
 123     qemu_put_be64s(f, &env->kernelgsbase);
 124 #endif
 125     qemu_put_be32s(f, &env->smbase);
 126     qemu_put_be64s(f, &env->pat);
 127     qemu_put_be32s(f, &env->hflags2);
 128
 129     qemu_put_be64s(f, &env->vm_hsave);
 130     qemu_put_be64s(f, &env->vm_vmcb);
 131     qemu_put_be64s(f, &env->tsc_offset);
 132     qemu_put_be64s(f, &env->intercept);
 133     qemu_put_be16s(f, &env->intercept_cr_read);
 134     qemu_put_be16s(f, &env->intercept_cr_write);
 135     qemu_put_be16s(f, &env->intercept_dr_read);
 136     qemu_put_be16s(f, &env->intercept_dr_write);
 137     qemu_put_be32s(f, &env->intercept_exceptions);
 138     qemu_put_8s(f, &env->v_tpr);
 139
 140     /* MTRRs */
 141     for(i = 0; i < 11; i++)
 142         qemu_put_be64s(f, &env->mtrr_fixed[i]);
 143     qemu_put_be64s(f, &env->mtrr_deftype);
 144     for(i = 0; i < 8; i++) {
 145         qemu_put_be64s(f, &env->mtrr_var[i].base);
 146         qemu_put_be64s(f, &env->mtrr_var[i].mask);
 147     }
 148
 149     /* KVM-related states */
 150
 151     /* There can only be one pending IRQ set in the bitmap at a time, so try
 152        to find it and save its number instead (-1 for none). */
 153     pending_irq = -1;
 154     for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
 155         if (env->interrupt_bitmap[i]) {
 156             bit = ctz64(env->interrupt_bitmap[i]);
 157             pending_irq = i * 64 + bit;
 158             break;
 159         }
 160     }
 161     qemu_put_sbe32s(f, &pending_irq);
 162     qemu_put_be32s(f, &env->mp_state);
 163     qemu_put_be64s(f, &env->tsc);
 164
 165     /* MCE */
 166     qemu_put_be64s(f, &env->mcg_cap);
 167     if (env->mcg_cap && !kvm_enabled()) {
 168         qemu_put_be64s(f, &env->mcg_status);
 169         qemu_put_be64s(f, &env->mcg_ctl);
 170         for (i = 0; i < (env->mcg_cap & 0xff); i++) {
 171             qemu_put_be64s(f, &env->mce_banks[4*i]);
 172             qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
 173             qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
 174             qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
 175         }
 176     }
 177  }
 178
 179 #ifdef USE_X86LDOUBLE
 180 /* XXX: add that in a FPU generic layer */
 181 union x86_longdouble {
 182     uint64_t mant;
 183     uint16_t exp;
 184 };
 185
 186 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
 187 #define EXPBIAS1 1023
 188 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
 189 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
 190
 191 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
 192 {
 193     int e;
 194     /* mantissa */
 195     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 196     /* exponent + sign */
 197     e = EXPD1(temp) - EXPBIAS1 + 16383;
 198     e |= SIGND1(temp) >> 16;
 199     p->exp = e;
 200 }
 201 #endif
 202
 203 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 204 {
 205     CPUState *env = opaque;
 206     int i, guess_mmx;
 207     uint32_t hflags;
 208     uint16_t fpus, fpuc, fptag, fpregs_format;
 209     int32_t a20_mask;
 210     int32_t pending_irq;
 211
 212     if (version_id < 3 || version_id > CPU_SAVE_VERSION)
 213         return -EINVAL;
 214     for(i = 0; i < CPU_NB_REGS; i++)
 215         qemu_get_betls(f, &env->regs[i]);
 216     qemu_get_betls(f, &env->eip);
 217     qemu_get_betls(f, &env->eflags);
 218     qemu_get_be32s(f, &hflags);
 219
 220     qemu_get_be16s(f, &fpuc);
 221     qemu_get_be16s(f, &fpus);
 222     qemu_get_be16s(f, &fptag);
 223     qemu_get_be16s(f, &fpregs_format);
 224
 225     /* NOTE: we cannot always restore the FPU state if the image come
 226        from a host with a different 'USE_X86LDOUBLE' define. We guess
 227        if we are in an MMX state to restore correctly in that case. */
 228     guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
 229     for(i = 0; i < 8; i++) {
 230         uint64_t mant;
 231         uint16_t exp;
 232
 233         switch(fpregs_format) {
 234         case 0:
 235             mant = qemu_get_be64(f);
 236             exp = qemu_get_be16(f);
 237 #ifdef USE_X86LDOUBLE
 238             env->fpregs[i].d = cpu_set_fp80(mant, exp);
 239 #else
 240             /* difficult case */
 241             if (guess_mmx)
 242                 env->fpregs[i].mmx.MMX_Q(0) = mant;
 243             else
 244                 env->fpregs[i].d = cpu_set_fp80(mant, exp);
 245 #endif
 246             break;
 247         case 1:
 248             mant = qemu_get_be64(f);
 249 #ifdef USE_X86LDOUBLE
 250             {
 251                 union x86_longdouble *p;
 252                 /* difficult case */
 253                 p = (void *)&env->fpregs[i];
 254                 if (guess_mmx) {
 255                     p->mant = mant;
 256                     p->exp = 0xffff;
 257                 } else {
 258                     fp64_to_fp80(p, mant);
 259                 }
 260             }
 261 #else
 262             env->fpregs[i].mmx.MMX_Q(0) = mant;
 263 #endif
 264             break;
 265         default:
 266             return -EINVAL;
 267         }
 268     }
 269
 270     env->fpuc = fpuc;
 271     /* XXX: restore FPU round state */
 272     env->fpstt = (fpus >> 11) & 7;
 273     env->fpus = fpus & ~0x3800;
 274     fptag ^= 0xff;
 275     for(i = 0; i < 8; i++) {
 276         env->fptags[i] = (fptag >> i) & 1;
 277     }
 278
 279     for(i = 0; i < 6; i++)
 280         cpu_get_seg(f, &env->segs[i]);
 281     cpu_get_seg(f, &env->ldt);
 282     cpu_get_seg(f, &env->tr);
 283     cpu_get_seg(f, &env->gdt);
 284     cpu_get_seg(f, &env->idt);
 285
 286     qemu_get_be32s(f, &env->sysenter_cs);
 287     if (version_id >= 7) {
 288         qemu_get_betls(f, &env->sysenter_esp);
 289         qemu_get_betls(f, &env->sysenter_eip);
 290     } else {
 291         env->sysenter_esp = qemu_get_be32(f);
 292         env->sysenter_eip = qemu_get_be32(f);
 293     }
 294
 295     qemu_get_betls(f, &env->cr[0]);
 296     qemu_get_betls(f, &env->cr[2]);
 297     qemu_get_betls(f, &env->cr[3]);
 298     qemu_get_betls(f, &env->cr[4]);
 299
 300     for(i = 0; i < 8; i++)
 301         qemu_get_betls(f, &env->dr[i]);
 302     cpu_breakpoint_remove_all(env, BP_CPU);
 303     cpu_watchpoint_remove_all(env, BP_CPU);
 304     for (i = 0; i < 4; i++)
 305         hw_breakpoint_insert(env, i);
 306
 307     /* MMU */
 308     qemu_get_sbe32s(f, &a20_mask);
 309     env->a20_mask = a20_mask;
 310
 311     qemu_get_be32s(f, &env->mxcsr);
 312     for(i = 0; i < CPU_NB_REGS; i++) {
 313         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 314         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 315     }
 316
 317 #ifdef TARGET_X86_64
 318     qemu_get_be64s(f, &env->efer);
 319     qemu_get_be64s(f, &env->star);
 320     qemu_get_be64s(f, &env->lstar);
 321     qemu_get_be64s(f, &env->cstar);
 322     qemu_get_be64s(f, &env->fmask);
 323     qemu_get_be64s(f, &env->kernelgsbase);
 324 #endif
 325     if (version_id >= 4) {
 326         qemu_get_be32s(f, &env->smbase);
 327     }
 328     if (version_id >= 5) {
 329         qemu_get_be64s(f, &env->pat);
 330         qemu_get_be32s(f, &env->hflags2);
 331         if (version_id < 6)
 332             qemu_get_be32s(f, &env->halted);
 333
 334         qemu_get_be64s(f, &env->vm_hsave);
 335         qemu_get_be64s(f, &env->vm_vmcb);
 336         qemu_get_be64s(f, &env->tsc_offset);
 337         qemu_get_be64s(f, &env->intercept);
 338         qemu_get_be16s(f, &env->intercept_cr_read);
 339         qemu_get_be16s(f, &env->intercept_cr_write);
 340         qemu_get_be16s(f, &env->intercept_dr_read);
 341         qemu_get_be16s(f, &env->intercept_dr_write);
 342         qemu_get_be32s(f, &env->intercept_exceptions);
 343         qemu_get_8s(f, &env->v_tpr);
 344     }
 345
 346     if (version_id >= 8) {
 347         /* MTRRs */
 348         for(i = 0; i < 11; i++)
 349             qemu_get_be64s(f, &env->mtrr_fixed[i]);
 350         qemu_get_be64s(f, &env->mtrr_deftype);
 351         for(i = 0; i < 8; i++) {
 352             qemu_get_be64s(f, &env->mtrr_var[i].base);
 353             qemu_get_be64s(f, &env->mtrr_var[i].mask);
 354         }
 355     }
 356
 357     if (version_id >= 9) {
 358         qemu_get_sbe32s(f, &pending_irq);
 359         memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap));
 360         if (pending_irq >= 0) {
 361             env->interrupt_bitmap[pending_irq / 64] |=
 362                 (uint64_t)1 << (pending_irq % 64);
 363         }
 364         qemu_get_be32s(f, &env->mp_state);
 365         qemu_get_be64s(f, &env->tsc);
 366     }
 367
 368     if (version_id >= 10) {
 369         qemu_get_be64s(f, &env->mcg_cap);
 370         if (env->mcg_cap && !kvm_enabled()) {
 371             qemu_get_be64s(f, &env->mcg_status);
 372             qemu_get_be64s(f, &env->mcg_ctl);
 373             for (i = 0; i < (env->mcg_cap & 0xff); i++) {
 374                 qemu_get_be64s(f, &env->mce_banks[4*i]);
 375                 qemu_get_be64s(f, &env->mce_banks[4*i + 1]);
 376                 qemu_get_be64s(f, &env->mce_banks[4*i + 2]);
 377                 qemu_get_be64s(f, &env->mce_banks[4*i + 3]);
 378             }
 379         }
 380     }
 381
 382     /* XXX: ensure compatiblity for halted bit ? */
 383     /* XXX: compute redundant hflags bits */
 384     env->hflags = hflags;
 385     tlb_flush(env, 1);
 386     cpu_synchronize_state(env, 1);
 387     if (kvm_enabled()) {
 388         /* when in-kernel irqchip is used, env->halted causes deadlock
 389            because no userspace IRQs will ever clear this flag */
 390         env->halted = 0;
 391         if (version_id < 9) {
 392             for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
 393                 qemu_get_be64s(f, &env->interrupt_bitmap[i]);
 394             }
 395             qemu_get_be64s(f, &env->tsc);
 396             kvm_load_registers(env);
 397             kvm_load_tsc(env);
 398             if (version_id >= 5) {
 399                 qemu_get_be32s(f, &env->mp_state);
 400                 kvm_arch_load_mpstate(env);
 401             }
 402         } else {
 403             kvm_load_registers(env);
 404             kvm_load_tsc(env);
 405             kvm_arch_load_mpstate(env);
 406         }
 407     }
 408     return 0;
 409 }