exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* is_jmp field values */
  29 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  30 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  31 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  32 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  33
  34 typedef struct TranslationBlock TranslationBlock;
  35
  36 /* XXX: make safe guess about sizes */
  37 #define MAX_OP_PER_INSTR 64
  38 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  39 #define MAX_OPC_PARAM 10
  40 #define OPC_BUF_SIZE 512
  41 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  42
  43 /* Maximum size a TCG op can expand to.  This is complicated because a
  44    single op may require several host instructions and regirster reloads.
  45    For now take a wild guess at 128 bytes, which should allow at least
  46    a couple of fixup instructions per argument.  */
  47 #define TCG_MAX_OP_SIZE 128
  48
  49 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  50
  51 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  52 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  53 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  54 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  55 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  56 extern target_ulong gen_opc_jump_pc[2];
  57 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  58
  59 #include "qemu-log.h"
  60
  61 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  62 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  63 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  64                  unsigned long searched_pc, int pc_pos, void *puc);
  65
  66 unsigned long code_gen_max_block_size(void);
  67 void cpu_gen_init(void);
  68 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  69                  int *gen_code_size_ptr);
  70 int cpu_restore_state(struct TranslationBlock *tb,
  71                       CPUState *env, unsigned long searched_pc,
  72                       void *puc);
  73 int cpu_restore_state_copy(struct TranslationBlock *tb,
  74                            CPUState *env, unsigned long searched_pc,
  75                            void *puc);
  76 void cpu_resume_from_signal(CPUState *env1, void *puc);
  77 void cpu_io_recompile(CPUState *env, void *retaddr);
  78 TranslationBlock *tb_gen_code(CPUState *env,
  79                               target_ulong pc, target_ulong cs_base, int flags,
  80                               int cflags);
  81 void cpu_exec_init(CPUState *env);
  82 void QEMU_NORETURN cpu_loop_exit(void);
  83 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  84 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  85                                    int is_cpu_write_access);
  86 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  87 void tlb_flush_page(CPUState *env, target_ulong addr);
  88 void tlb_flush(CPUState *env, int flush_global);
  89 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  90                       target_phys_addr_t paddr, int prot,
  91                       int mmu_idx, int is_softmmu);
  92 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
  93                                target_phys_addr_t paddr, int prot,
  94                                int mmu_idx, int is_softmmu)
  95 {
  96     if (prot & PAGE_READ)
  97         prot |= PAGE_EXEC;
  98     return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
  99 }
 100
 101 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 102
 103 #define CODE_GEN_PHYS_HASH_BITS     15
 104 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 105
 106 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 107
 108 /* estimated block size for TB allocation */
 109 /* XXX: use a per code average code fragment size and modulate it
 110    according to the host CPU */
 111 #if defined(CONFIG_SOFTMMU)
 112 #define CODE_GEN_AVG_BLOCK_SIZE 128
 113 #else
 114 #define CODE_GEN_AVG_BLOCK_SIZE 64
 115 #endif
 116
 117 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__)
 118 #define USE_DIRECT_JUMP
 119 #endif
 120 #if defined(__i386__) && !defined(_WIN32)
 121 #define USE_DIRECT_JUMP
 122 #endif
 123
 124 struct TranslationBlock {
 125     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 126     target_ulong cs_base; /* CS base for this block */
 127     uint64_t flags; /* flags defining in which context the code was generated */
 128     uint16_t size;      /* size of target code for this block (1 <=
 129                            size <= TARGET_PAGE_SIZE) */
 130     uint16_t cflags;    /* compile flags */
 131 #define CF_COUNT_MASK  0x7fff
 132 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 133
 134     uint8_t *tc_ptr;    /* pointer to the translated code */
 135     /* next matching tb for physical address. */
 136     struct TranslationBlock *phys_hash_next;
 137     /* first and second physical page containing code. The lower bit
 138        of the pointer tells the index in page_next[] */
 139     struct TranslationBlock *page_next[2];
 140     target_ulong page_addr[2];
 141
 142     /* the following data are used to directly call another TB from
 143        the code of this one. */
 144     uint16_t tb_next_offset[2]; /* offset of original jump target */
 145 #ifdef USE_DIRECT_JUMP
 146     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 147 #else
 148     unsigned long tb_next[2]; /* address of jump generated code */
 149 #endif
 150     /* list of TBs jumping to this one. This is a circular list using
 151        the two least significant bits of the pointers to tell what is
 152        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 153        jmp_first */
 154     struct TranslationBlock *jmp_next[2];
 155     struct TranslationBlock *jmp_first;
 156     uint32_t icount;
 157 };
 158
 159 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 160 {
 161     target_ulong tmp;
 162     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 163     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 164 }
 165
 166 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 167 {
 168     target_ulong tmp;
 169     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 170     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 171             | (tmp & TB_JMP_ADDR_MASK));
 172 }
 173
 174 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 175 {
 176     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 177 }
 178
 179 TranslationBlock *tb_alloc(target_ulong pc);
 180 void tb_free(TranslationBlock *tb);
 181 void tb_flush(CPUState *env);
 182 void tb_link_phys(TranslationBlock *tb,
 183                   target_ulong phys_pc, target_ulong phys_page2);
 184 void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
 185
 186 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 187 extern uint8_t *code_gen_ptr;
 188 extern int code_gen_max_blocks;
 189
 190 #if defined(USE_DIRECT_JUMP)
 191
 192 #if defined(_ARCH_PPC)
 193 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 194 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 195 #elif defined(__i386__) || defined(__x86_64__)
 196 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 197 {
 198     /* patch the branch destination */
 199     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 200     /* no need to flush icache explicitly */
 201 }
 202 #elif defined(__arm__)
 203 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 204 {
 205 #if QEMU_GNUC_PREREQ(4, 1)
 206     void __clear_cache(char *beg, char *end);
 207 #else
 208     register unsigned long _beg __asm ("a1");
 209     register unsigned long _end __asm ("a2");
 210     register unsigned long _flg __asm ("a3");
 211 #endif
 212
 213     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 214     *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
 215
 216 #if QEMU_GNUC_PREREQ(4, 1)
 217     __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 218 #else
 219     /* flush icache */
 220     _beg = jmp_addr;
 221     _end = jmp_addr + 4;
 222     _flg = 0;
 223     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 224 #endif
 225 }
 226 #endif
 227
 228 static inline void tb_set_jmp_target(TranslationBlock *tb,
 229                                      int n, unsigned long addr)
 230 {
 231     unsigned long offset;
 232
 233     offset = tb->tb_jmp_offset[n];
 234     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 235     offset = tb->tb_jmp_offset[n + 2];
 236     if (offset != 0xffff)
 237         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 238 }
 239
 240 #else
 241
 242 /* set the jump target */
 243 static inline void tb_set_jmp_target(TranslationBlock *tb,
 244                                      int n, unsigned long addr)
 245 {
 246     tb->tb_next[n] = addr;
 247 }
 248
 249 #endif
 250
 251 static inline void tb_add_jump(TranslationBlock *tb, int n,
 252                                TranslationBlock *tb_next)
 253 {
 254     /* NOTE: this test is only needed for thread safety */
 255     if (!tb->jmp_next[n]) {
 256         /* patch the native jump address */
 257         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 258
 259         /* add in TB jmp circular list */
 260         tb->jmp_next[n] = tb_next->jmp_first;
 261         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 262     }
 263 }
 264
 265 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 266
 267 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 268 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 269 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 270
 271 #include "qemu-lock.h"
 272
 273 extern spinlock_t tb_lock;
 274
 275 extern int tb_invalidated_flag;
 276
 277 #if !defined(CONFIG_USER_ONLY)
 278
 279 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 280               void *retaddr);
 281
 282 #include "softmmu_defs.h"
 283
 284 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 285 #define MEMSUFFIX _code
 286 #define env cpu_single_env
 287
 288 #define DATA_SIZE 1
 289 #include "softmmu_header.h"
 290
 291 #define DATA_SIZE 2
 292 #include "softmmu_header.h"
 293
 294 #define DATA_SIZE 4
 295 #include "softmmu_header.h"
 296
 297 #define DATA_SIZE 8
 298 #include "softmmu_header.h"
 299
 300 #undef ACCESS_TYPE
 301 #undef MEMSUFFIX
 302 #undef env
 303
 304 #endif
 305
 306 #if defined(CONFIG_USER_ONLY)
 307 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 308 {
 309     return addr;
 310 }
 311 #else
 312 /* NOTE: this function can trigger an exception */
 313 /* NOTE2: the returned address is not exactly the physical address: it
 314    is the offset relative to phys_ram_base */
 315 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 316 {
 317     int mmu_idx, page_index, pd;
 318     void *p;
 319
 320     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 321     mmu_idx = cpu_mmu_index(env1);
 322     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 323                  (addr & TARGET_PAGE_MASK))) {
 324         ldub_code(addr);
 325     }
 326     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 327     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 328 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 329         do_unassigned_access(addr, 0, 1, 0, 4);
 330 #else
 331         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 332 #endif
 333     }
 334     p = (void *)(unsigned long)addr
 335         + env1->tlb_table[mmu_idx][page_index].addend;
 336     return qemu_ram_addr_from_host(p);
 337 }
 338
 339 /* Deterministic execution requires that IO only be performed on the last
 340    instruction of a TB so that interrupts take effect immediately.  */
 341 static inline int can_do_io(CPUState *env)
 342 {
 343     if (!use_icount)
 344         return 1;
 345
 346     /* If not executing code then assume we are ok.  */
 347     if (!env->current_tb)
 348         return 1;
 349
 350     return env->can_do_io != 0;
 351 }
 352 #endif
 353
 354 #ifdef CONFIG_KQEMU
 355 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 356
 357 #define MSR_QPI_COMMBASE 0xfabe0010
 358
 359 int kqemu_init(CPUState *env);
 360 int kqemu_cpu_exec(CPUState *env);
 361 void kqemu_flush_page(CPUState *env, target_ulong addr);
 362 void kqemu_flush(CPUState *env, int global);
 363 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 364 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 365 void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
 366                         ram_addr_t phys_offset);
 367 void kqemu_cpu_interrupt(CPUState *env);
 368 void kqemu_record_dump(void);
 369
 370 extern uint32_t kqemu_comm_base;
 371
 372 extern ram_addr_t kqemu_phys_ram_size;
 373 extern uint8_t *kqemu_phys_ram_base;
 374
 375 static inline int kqemu_is_ok(CPUState *env)
 376 {
 377     return(env->kqemu_enabled &&
 378            (env->cr[0] & CR0_PE_MASK) &&
 379            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 380            (env->eflags & IF_MASK) &&
 381            !(env->eflags & VM_MASK) &&
 382            (env->kqemu_enabled == 2 ||
 383             ((env->hflags & HF_CPL_MASK) == 3 &&
 384              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 385 }
 386
 387 #endif
 388
 389 typedef void (CPUDebugExcpHandler)(CPUState *env);
 390
 391 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
 392
 393 /* vl.c */
 394 extern int singlestep;
 395
 396 #endif