hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "audio/audio.h"
  21 #include "i2c.h"
  22
  23 #define MP_MISC_BASE            0x80002000
  24 #define MP_MISC_SIZE            0x00001000
  25
  26 #define MP_ETH_BASE             0x80008000
  27 #define MP_ETH_SIZE             0x00001000
  28
  29 #define MP_WLAN_BASE            0x8000C000
  30 #define MP_WLAN_SIZE            0x00000800
  31
  32 #define MP_UART1_BASE           0x8000C840
  33 #define MP_UART2_BASE           0x8000C940
  34
  35 #define MP_GPIO_BASE            0x8000D000
  36 #define MP_GPIO_SIZE            0x00001000
  37
  38 #define MP_FLASHCFG_BASE        0x90006000
  39 #define MP_FLASHCFG_SIZE        0x00001000
  40
  41 #define MP_AUDIO_BASE           0x90007000
  42 #define MP_AUDIO_SIZE           0x00001000
  43
  44 #define MP_PIC_BASE             0x90008000
  45 #define MP_PIC_SIZE             0x00001000
  46
  47 #define MP_PIT_BASE             0x90009000
  48 #define MP_PIT_SIZE             0x00001000
  49
  50 #define MP_LCD_BASE             0x9000c000
  51 #define MP_LCD_SIZE             0x00001000
  52
  53 #define MP_SRAM_BASE            0xC0000000
  54 #define MP_SRAM_SIZE            0x00020000
  55
  56 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  57 #define MP_FLASH_SIZE_MAX       32*1024*1024
  58
  59 #define MP_TIMER1_IRQ           4
  60 #define MP_TIMER2_IRQ           5
  61 #define MP_TIMER3_IRQ           6
  62 #define MP_TIMER4_IRQ           7
  63 #define MP_EHCI_IRQ             8
  64 #define MP_ETH_IRQ              9
  65 #define MP_UART1_IRQ            11
  66 #define MP_UART2_IRQ            11
  67 #define MP_GPIO_IRQ             12
  68 #define MP_RTC_IRQ              28
  69 #define MP_AUDIO_IRQ            30
  70
  71 static uint32_t gpio_in_state = 0xffffffff;
  72 static uint32_t gpio_isr;
  73 static uint32_t gpio_out_state;
  74 static ram_addr_t sram_off;
  75
  76 typedef enum i2c_state {
  77     STOPPED = 0,
  78     INITIALIZING,
  79     SENDING_BIT7,
  80     SENDING_BIT6,
  81     SENDING_BIT5,
  82     SENDING_BIT4,
  83     SENDING_BIT3,
  84     SENDING_BIT2,
  85     SENDING_BIT1,
  86     SENDING_BIT0,
  87     WAITING_FOR_ACK,
  88     RECEIVING_BIT7,
  89     RECEIVING_BIT6,
  90     RECEIVING_BIT5,
  91     RECEIVING_BIT4,
  92     RECEIVING_BIT3,
  93     RECEIVING_BIT2,
  94     RECEIVING_BIT1,
  95     RECEIVING_BIT0,
  96     SENDING_ACK
  97 } i2c_state;
  98
  99 typedef struct i2c_interface {
 100     i2c_bus *bus;
 101     i2c_state state;
 102     int last_data;
 103     int last_clock;
 104     uint8_t buffer;
 105     int current_addr;
 106 } i2c_interface;
 107
 108 static void i2c_enter_stop(i2c_interface *i2c)
 109 {
 110     if (i2c->current_addr >= 0)
 111         i2c_end_transfer(i2c->bus);
 112     i2c->current_addr = -1;
 113     i2c->state = STOPPED;
 114 }
 115
 116 static void i2c_state_update(i2c_interface *i2c, int data, int clock)
 117 {
 118     if (!i2c)
 119         return;
 120
 121     switch (i2c->state) {
 122     case STOPPED:
 123         if (data == 0 && i2c->last_data == 1 && clock == 1)
 124             i2c->state = INITIALIZING;
 125         break;
 126
 127     case INITIALIZING:
 128         if (clock == 0 && i2c->last_clock == 1 && data == 0)
 129             i2c->state = SENDING_BIT7;
 130         else
 131             i2c_enter_stop(i2c);
 132         break;
 133
 134     case SENDING_BIT7 ... SENDING_BIT0:
 135         if (clock == 0 && i2c->last_clock == 1) {
 136             i2c->buffer = (i2c->buffer << 1) | data;
 137             i2c->state++; /* will end up in WAITING_FOR_ACK */
 138         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 139             i2c_enter_stop(i2c);
 140         break;
 141
 142     case WAITING_FOR_ACK:
 143         if (clock == 0 && i2c->last_clock == 1) {
 144             if (i2c->current_addr < 0) {
 145                 i2c->current_addr = i2c->buffer;
 146                 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
 147                                    i2c->buffer & 1);
 148             } else
 149                 i2c_send(i2c->bus, i2c->buffer);
 150             if (i2c->current_addr & 1) {
 151                 i2c->state = RECEIVING_BIT7;
 152                 i2c->buffer = i2c_recv(i2c->bus);
 153             } else
 154                 i2c->state = SENDING_BIT7;
 155         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 156             i2c_enter_stop(i2c);
 157         break;
 158
 159     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 160         if (clock == 0 && i2c->last_clock == 1) {
 161             i2c->state++; /* will end up in SENDING_ACK */
 162             i2c->buffer <<= 1;
 163         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 164             i2c_enter_stop(i2c);
 165         break;
 166
 167     case SENDING_ACK:
 168         if (clock == 0 && i2c->last_clock == 1) {
 169             i2c->state = RECEIVING_BIT7;
 170             if (data == 0)
 171                 i2c->buffer = i2c_recv(i2c->bus);
 172             else
 173                 i2c_nack(i2c->bus);
 174         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 175             i2c_enter_stop(i2c);
 176         break;
 177     }
 178
 179     i2c->last_data = data;
 180     i2c->last_clock = clock;
 181 }
 182
 183 static int i2c_get_data(i2c_interface *i2c)
 184 {
 185     if (!i2c)
 186         return 0;
 187
 188     switch (i2c->state) {
 189     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 190         return (i2c->buffer >> 7);
 191
 192     case WAITING_FOR_ACK:
 193     default:
 194         return 0;
 195     }
 196 }
 197
 198 static i2c_interface *mixer_i2c;
 199
 200 #ifdef HAS_AUDIO
 201
 202 /* Audio register offsets */
 203 #define MP_AUDIO_PLAYBACK_MODE  0x00
 204 #define MP_AUDIO_CLOCK_DIV      0x18
 205 #define MP_AUDIO_IRQ_STATUS     0x20
 206 #define MP_AUDIO_IRQ_ENABLE     0x24
 207 #define MP_AUDIO_TX_START_LO    0x28
 208 #define MP_AUDIO_TX_THRESHOLD   0x2C
 209 #define MP_AUDIO_TX_STATUS      0x38
 210 #define MP_AUDIO_TX_START_HI    0x40
 211
 212 /* Status register and IRQ enable bits */
 213 #define MP_AUDIO_TX_HALF        (1 << 6)
 214 #define MP_AUDIO_TX_FULL        (1 << 7)
 215
 216 /* Playback mode bits */
 217 #define MP_AUDIO_16BIT_SAMPLE   (1 << 0)
 218 #define MP_AUDIO_PLAYBACK_EN    (1 << 7)
 219 #define MP_AUDIO_CLOCK_24MHZ    (1 << 9)
 220 #define MP_AUDIO_MONO           (1 << 14)
 221
 222 /* Wolfson 8750 I2C address */
 223 #define MP_WM_ADDR              0x34
 224
 225 static const char audio_name[] = "mv88w8618";
 226
 227 typedef struct musicpal_audio_state {
 228     qemu_irq irq;
 229     uint32_t playback_mode;
 230     uint32_t status;
 231     uint32_t irq_enable;
 232     unsigned long phys_buf;
 233     uint32_t target_buffer;
 234     unsigned int threshold;
 235     unsigned int play_pos;
 236     unsigned int last_free;
 237     uint32_t clock_div;
 238     DeviceState *wm;
 239 } musicpal_audio_state;
 240
 241 static void audio_callback(void *opaque, int free_out, int free_in)
 242 {
 243     musicpal_audio_state *s = opaque;
 244     int16_t *codec_buffer;
 245     int8_t buf[4096];
 246     int8_t *mem_buffer;
 247     int pos, block_size;
 248
 249     if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
 250         return;
 251
 252     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
 253         free_out <<= 1;
 254
 255     if (!(s->playback_mode & MP_AUDIO_MONO))
 256         free_out <<= 1;
 257
 258     block_size = s->threshold/2;
 259     if (free_out - s->last_free < block_size)
 260         return;
 261
 262     if (block_size > 4096)
 263         return;
 264
 265     cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf,
 266                              block_size);
 267     mem_buffer = buf;
 268     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
 269         if (s->playback_mode & MP_AUDIO_MONO) {
 270             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 271             for (pos = 0; pos < block_size; pos += 2) {
 272                 *codec_buffer++ = *(int16_t *)mem_buffer;
 273                 *codec_buffer++ = *(int16_t *)mem_buffer;
 274                 mem_buffer += 2;
 275             }
 276         } else
 277             memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
 278                    (uint32_t *)mem_buffer, block_size);
 279     } else {
 280         if (s->playback_mode & MP_AUDIO_MONO) {
 281             codec_buffer = wm8750_dac_buffer(s->wm, block_size);
 282             for (pos = 0; pos < block_size; pos++) {
 283                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
 284                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 285             }
 286         } else {
 287             codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 288             for (pos = 0; pos < block_size; pos += 2) {
 289                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 290                 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
 291             }
 292         }
 293     }
 294     wm8750_dac_commit(s->wm);
 295
 296     s->last_free = free_out - block_size;
 297
 298     if (s->play_pos == 0) {
 299         s->status |= MP_AUDIO_TX_HALF;
 300         s->play_pos = block_size;
 301     } else {
 302         s->status |= MP_AUDIO_TX_FULL;
 303         s->play_pos = 0;
 304     }
 305
 306     if (s->status & s->irq_enable)
 307         qemu_irq_raise(s->irq);
 308 }
 309
 310 static void musicpal_audio_clock_update(musicpal_audio_state *s)
 311 {
 312     int rate;
 313
 314     if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
 315         rate = 24576000 / 64; /* 24.576MHz */
 316     else
 317         rate = 11289600 / 64; /* 11.2896MHz */
 318
 319     rate /= ((s->clock_div >> 8) & 0xff) + 1;
 320
 321     wm8750_set_bclk_in(s->wm, rate);
 322 }
 323
 324 static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
 325 {
 326     musicpal_audio_state *s = opaque;
 327
 328     switch (offset) {
 329     case MP_AUDIO_PLAYBACK_MODE:
 330         return s->playback_mode;
 331
 332     case MP_AUDIO_CLOCK_DIV:
 333         return s->clock_div;
 334
 335     case MP_AUDIO_IRQ_STATUS:
 336         return s->status;
 337
 338     case MP_AUDIO_IRQ_ENABLE:
 339         return s->irq_enable;
 340
 341     case MP_AUDIO_TX_STATUS:
 342         return s->play_pos >> 2;
 343
 344     default:
 345         return 0;
 346     }
 347 }
 348
 349 static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
 350                                  uint32_t value)
 351 {
 352     musicpal_audio_state *s = opaque;
 353
 354     switch (offset) {
 355     case MP_AUDIO_PLAYBACK_MODE:
 356         if (value & MP_AUDIO_PLAYBACK_EN &&
 357             !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
 358             s->status = 0;
 359             s->last_free = 0;
 360             s->play_pos = 0;
 361         }
 362         s->playback_mode = value;
 363         musicpal_audio_clock_update(s);
 364         break;
 365
 366     case MP_AUDIO_CLOCK_DIV:
 367         s->clock_div = value;
 368         s->last_free = 0;
 369         s->play_pos = 0;
 370         musicpal_audio_clock_update(s);
 371         break;
 372
 373     case MP_AUDIO_IRQ_STATUS:
 374         s->status &= ~value;
 375         break;
 376
 377     case MP_AUDIO_IRQ_ENABLE:
 378         s->irq_enable = value;
 379         if (s->status & s->irq_enable)
 380             qemu_irq_raise(s->irq);
 381         break;
 382
 383     case MP_AUDIO_TX_START_LO:
 384         s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
 385         s->target_buffer = s->phys_buf;
 386         s->play_pos = 0;
 387         s->last_free = 0;
 388         break;
 389
 390     case MP_AUDIO_TX_THRESHOLD:
 391         s->threshold = (value + 1) * 4;
 392         break;
 393
 394     case MP_AUDIO_TX_START_HI:
 395         s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
 396         s->target_buffer = s->phys_buf;
 397         s->play_pos = 0;
 398         s->last_free = 0;
 399         break;
 400     }
 401 }
 402
 403 static void musicpal_audio_reset(void *opaque)
 404 {
 405     musicpal_audio_state *s = opaque;
 406
 407     s->playback_mode = 0;
 408     s->status = 0;
 409     s->irq_enable = 0;
 410 }
 411
 412 static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
 413     musicpal_audio_read,
 414     musicpal_audio_read,
 415     musicpal_audio_read
 416 };
 417
 418 static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
 419     musicpal_audio_write,
 420     musicpal_audio_write,
 421     musicpal_audio_write
 422 };
 423
 424 static i2c_interface *musicpal_audio_init(qemu_irq irq)
 425 {
 426     musicpal_audio_state *s;
 427     i2c_interface *i2c;
 428     int iomemtype;
 429
 430     s = qemu_mallocz(sizeof(musicpal_audio_state));
 431     s->irq = irq;
 432
 433     i2c = qemu_mallocz(sizeof(i2c_interface));
 434     i2c->bus = i2c_init_bus();
 435     i2c->current_addr = -1;
 436
 437     s->wm = i2c_create_slave(i2c->bus, "wm8750", MP_WM_ADDR);
 438     wm8750_data_req_set(s->wm, audio_callback, s);
 439
 440     iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
 441                        musicpal_audio_writefn, s);
 442     cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
 443
 444     qemu_register_reset(musicpal_audio_reset, 0, s);
 445
 446     return i2c;
 447 }
 448 #else  /* !HAS_AUDIO */
 449 static i2c_interface *musicpal_audio_init(qemu_irq irq)
 450 {
 451     return NULL;
 452 }
 453 #endif /* !HAS_AUDIO */
 454
 455 /* Ethernet register offsets */
 456 #define MP_ETH_SMIR             0x010
 457 #define MP_ETH_PCXR             0x408
 458 #define MP_ETH_SDCMR            0x448
 459 #define MP_ETH_ICR              0x450
 460 #define MP_ETH_IMR              0x458
 461 #define MP_ETH_FRDP0            0x480
 462 #define MP_ETH_FRDP1            0x484
 463 #define MP_ETH_FRDP2            0x488
 464 #define MP_ETH_FRDP3            0x48C
 465 #define MP_ETH_CRDP0            0x4A0
 466 #define MP_ETH_CRDP1            0x4A4
 467 #define MP_ETH_CRDP2            0x4A8
 468 #define MP_ETH_CRDP3            0x4AC
 469 #define MP_ETH_CTDP0            0x4E0
 470 #define MP_ETH_CTDP1            0x4E4
 471 #define MP_ETH_CTDP2            0x4E8
 472 #define MP_ETH_CTDP3            0x4EC
 473
 474 /* MII PHY access */
 475 #define MP_ETH_SMIR_DATA        0x0000FFFF
 476 #define MP_ETH_SMIR_ADDR        0x03FF0000
 477 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 478 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 479
 480 /* PHY registers */
 481 #define MP_ETH_PHY1_BMSR        0x00210000
 482 #define MP_ETH_PHY1_PHYSID1     0x00410000
 483 #define MP_ETH_PHY1_PHYSID2     0x00610000
 484
 485 #define MP_PHY_BMSR_LINK        0x0004
 486 #define MP_PHY_BMSR_AUTONEG     0x0008
 487
 488 #define MP_PHY_88E3015          0x01410E20
 489
 490 /* TX descriptor status */
 491 #define MP_ETH_TX_OWN           (1 << 31)
 492
 493 /* RX descriptor status */
 494 #define MP_ETH_RX_OWN           (1 << 31)
 495
 496 /* Interrupt cause/mask bits */
 497 #define MP_ETH_IRQ_RX_BIT       0
 498 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 499 #define MP_ETH_IRQ_TXHI_BIT     2
 500 #define MP_ETH_IRQ_TXLO_BIT     3
 501
 502 /* Port config bits */
 503 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 504
 505 /* SDMA command bits */
 506 #define MP_ETH_CMD_TXHI         (1 << 23)
 507 #define MP_ETH_CMD_TXLO         (1 << 22)
 508
 509 typedef struct mv88w8618_tx_desc {
 510     uint32_t cmdstat;
 511     uint16_t res;
 512     uint16_t bytes;
 513     uint32_t buffer;
 514     uint32_t next;
 515 } mv88w8618_tx_desc;
 516
 517 typedef struct mv88w8618_rx_desc {
 518     uint32_t cmdstat;
 519     uint16_t bytes;
 520     uint16_t buffer_size;
 521     uint32_t buffer;
 522     uint32_t next;
 523 } mv88w8618_rx_desc;
 524
 525 typedef struct mv88w8618_eth_state {
 526     SysBusDevice busdev;
 527     qemu_irq irq;
 528     uint32_t smir;
 529     uint32_t icr;
 530     uint32_t imr;
 531     int mmio_index;
 532     int vlan_header;
 533     uint32_t tx_queue[2];
 534     uint32_t rx_queue[4];
 535     uint32_t frx_queue[4];
 536     uint32_t cur_rx[4];
 537     VLANClientState *vc;
 538 } mv88w8618_eth_state;
 539
 540 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 541 {
 542     cpu_to_le32s(&desc->cmdstat);
 543     cpu_to_le16s(&desc->bytes);
 544     cpu_to_le16s(&desc->buffer_size);
 545     cpu_to_le32s(&desc->buffer);
 546     cpu_to_le32s(&desc->next);
 547     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 548 }
 549
 550 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 551 {
 552     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 553     le32_to_cpus(&desc->cmdstat);
 554     le16_to_cpus(&desc->bytes);
 555     le16_to_cpus(&desc->buffer_size);
 556     le32_to_cpus(&desc->buffer);
 557     le32_to_cpus(&desc->next);
 558 }
 559
 560 static int eth_can_receive(void *opaque)
 561 {
 562     return 1;
 563 }
 564
 565 static void eth_receive(void *opaque, const uint8_t *buf, int size)
 566 {
 567     mv88w8618_eth_state *s = opaque;
 568     uint32_t desc_addr;
 569     mv88w8618_rx_desc desc;
 570     int i;
 571
 572     for (i = 0; i < 4; i++) {
 573         desc_addr = s->cur_rx[i];
 574         if (!desc_addr)
 575             continue;
 576         do {
 577             eth_rx_desc_get(desc_addr, &desc);
 578             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 579                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 580                                           buf, size);
 581                 desc.bytes = size + s->vlan_header;
 582                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 583                 s->cur_rx[i] = desc.next;
 584
 585                 s->icr |= MP_ETH_IRQ_RX;
 586                 if (s->icr & s->imr)
 587                     qemu_irq_raise(s->irq);
 588                 eth_rx_desc_put(desc_addr, &desc);
 589                 return;
 590             }
 591             desc_addr = desc.next;
 592         } while (desc_addr != s->rx_queue[i]);
 593     }
 594 }
 595
 596 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 597 {
 598     cpu_to_le32s(&desc->cmdstat);
 599     cpu_to_le16s(&desc->res);
 600     cpu_to_le16s(&desc->bytes);
 601     cpu_to_le32s(&desc->buffer);
 602     cpu_to_le32s(&desc->next);
 603     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 604 }
 605
 606 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 607 {
 608     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 609     le32_to_cpus(&desc->cmdstat);
 610     le16_to_cpus(&desc->res);
 611     le16_to_cpus(&desc->bytes);
 612     le32_to_cpus(&desc->buffer);
 613     le32_to_cpus(&desc->next);
 614 }
 615
 616 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 617 {
 618     uint32_t desc_addr = s->tx_queue[queue_index];
 619     mv88w8618_tx_desc desc;
 620     uint8_t buf[2048];
 621     int len;
 622
 623
 624     do {
 625         eth_tx_desc_get(desc_addr, &desc);
 626         if (desc.cmdstat & MP_ETH_TX_OWN) {
 627             len = desc.bytes;
 628             if (len < 2048) {
 629                 cpu_physical_memory_read(desc.buffer, buf, len);
 630                 qemu_send_packet(s->vc, buf, len);
 631             }
 632             desc.cmdstat &= ~MP_ETH_TX_OWN;
 633             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 634             eth_tx_desc_put(desc_addr, &desc);
 635         }
 636         desc_addr = desc.next;
 637     } while (desc_addr != s->tx_queue[queue_index]);
 638 }
 639
 640 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 641 {
 642     mv88w8618_eth_state *s = opaque;
 643
 644     switch (offset) {
 645     case MP_ETH_SMIR:
 646         if (s->smir & MP_ETH_SMIR_OPCODE) {
 647             switch (s->smir & MP_ETH_SMIR_ADDR) {
 648             case MP_ETH_PHY1_BMSR:
 649                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 650                        MP_ETH_SMIR_RDVALID;
 651             case MP_ETH_PHY1_PHYSID1:
 652                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 653             case MP_ETH_PHY1_PHYSID2:
 654                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 655             default:
 656                 return MP_ETH_SMIR_RDVALID;
 657             }
 658         }
 659         return 0;
 660
 661     case MP_ETH_ICR:
 662         return s->icr;
 663
 664     case MP_ETH_IMR:
 665         return s->imr;
 666
 667     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 668         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 669
 670     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 671         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 672
 673     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 674         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 675
 676     default:
 677         return 0;
 678     }
 679 }
 680
 681 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 682                                 uint32_t value)
 683 {
 684     mv88w8618_eth_state *s = opaque;
 685
 686     switch (offset) {
 687     case MP_ETH_SMIR:
 688         s->smir = value;
 689         break;
 690
 691     case MP_ETH_PCXR:
 692         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 693         break;
 694
 695     case MP_ETH_SDCMR:
 696         if (value & MP_ETH_CMD_TXHI)
 697             eth_send(s, 1);
 698         if (value & MP_ETH_CMD_TXLO)
 699             eth_send(s, 0);
 700         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 701             qemu_irq_raise(s->irq);
 702         break;
 703
 704     case MP_ETH_ICR:
 705         s->icr &= value;
 706         break;
 707
 708     case MP_ETH_IMR:
 709         s->imr = value;
 710         if (s->icr & s->imr)
 711             qemu_irq_raise(s->irq);
 712         break;
 713
 714     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 715         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 716         break;
 717
 718     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 719         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 720             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 721         break;
 722
 723     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 724         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 725         break;
 726     }
 727 }
 728
 729 static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
 730     mv88w8618_eth_read,
 731     mv88w8618_eth_read,
 732     mv88w8618_eth_read
 733 };
 734
 735 static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
 736     mv88w8618_eth_write,
 737     mv88w8618_eth_write,
 738     mv88w8618_eth_write
 739 };
 740
 741 static void eth_cleanup(VLANClientState *vc)
 742 {
 743     mv88w8618_eth_state *s = vc->opaque;
 744
 745     cpu_unregister_io_memory(s->mmio_index);
 746
 747     qemu_free(s);
 748 }
 749
 750 static void mv88w8618_eth_init(SysBusDevice *dev)
 751 {
 752     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 753
 754     sysbus_init_irq(dev, &s->irq);
 755     s->vc = qdev_get_vlan_client(&dev->qdev,
 756                                  eth_receive, eth_can_receive,
 757                                  eth_cleanup, s);
 758     s->mmio_index = cpu_register_io_memory(0, mv88w8618_eth_readfn,
 759                                            mv88w8618_eth_writefn, s);
 760     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 761 }
 762
 763 /* LCD register offsets */
 764 #define MP_LCD_IRQCTRL          0x180
 765 #define MP_LCD_IRQSTAT          0x184
 766 #define MP_LCD_SPICTRL          0x1ac
 767 #define MP_LCD_INST             0x1bc
 768 #define MP_LCD_DATA             0x1c0
 769
 770 /* Mode magics */
 771 #define MP_LCD_SPI_DATA         0x00100011
 772 #define MP_LCD_SPI_CMD          0x00104011
 773 #define MP_LCD_SPI_INVALID      0x00000000
 774
 775 /* Commmands */
 776 #define MP_LCD_INST_SETPAGE0    0xB0
 777 /* ... */
 778 #define MP_LCD_INST_SETPAGE7    0xB7
 779
 780 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 781
 782 typedef struct musicpal_lcd_state {
 783     SysBusDevice busdev;
 784     uint32_t mode;
 785     uint32_t irqctrl;
 786     int page;
 787     int page_off;
 788     DisplayState *ds;
 789     uint8_t video_ram[128*64/8];
 790 } musicpal_lcd_state;
 791
 792 static uint32_t lcd_brightness;
 793
 794 static uint8_t scale_lcd_color(uint8_t col)
 795 {
 796     int tmp = col;
 797
 798     switch (lcd_brightness) {
 799     case 0x00000007: /* 0 */
 800         return 0;
 801
 802     case 0x00020000: /* 1 */
 803         return (tmp * 1) / 7;
 804
 805     case 0x00020001: /* 2 */
 806         return (tmp * 2) / 7;
 807
 808     case 0x00040000: /* 3 */
 809         return (tmp * 3) / 7;
 810
 811     case 0x00010006: /* 4 */
 812         return (tmp * 4) / 7;
 813
 814     case 0x00020005: /* 5 */
 815         return (tmp * 5) / 7;
 816
 817     case 0x00040003: /* 6 */
 818         return (tmp * 6) / 7;
 819
 820     case 0x00030004: /* 7 */
 821     default:
 822         return col;
 823     }
 824 }
 825
 826 #define SET_LCD_PIXEL(depth, type) \
 827 static inline void glue(set_lcd_pixel, depth) \
 828         (musicpal_lcd_state *s, int x, int y, type col) \
 829 { \
 830     int dx, dy; \
 831     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 832 \
 833     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 834         for (dx = 0; dx < 3; dx++, pixel++) \
 835             *pixel = col; \
 836 }
 837 SET_LCD_PIXEL(8, uint8_t)
 838 SET_LCD_PIXEL(16, uint16_t)
 839 SET_LCD_PIXEL(32, uint32_t)
 840
 841 #include "pixel_ops.h"
 842
 843 static void lcd_refresh(void *opaque)
 844 {
 845     musicpal_lcd_state *s = opaque;
 846     int x, y, col;
 847
 848     switch (ds_get_bits_per_pixel(s->ds)) {
 849     case 0:
 850         return;
 851 #define LCD_REFRESH(depth, func) \
 852     case depth: \
 853         col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 854                    scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 855                    scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
 856         for (x = 0; x < 128; x++) \
 857             for (y = 0; y < 64; y++) \
 858                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 859                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 860                 else \
 861                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 862         break;
 863     LCD_REFRESH(8, rgb_to_pixel8)
 864     LCD_REFRESH(16, rgb_to_pixel16)
 865     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 866                      rgb_to_pixel32bgr : rgb_to_pixel32))
 867     default:
 868         hw_error("unsupported colour depth %i\n",
 869                   ds_get_bits_per_pixel(s->ds));
 870     }
 871
 872     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 873 }
 874
 875 static void lcd_invalidate(void *opaque)
 876 {
 877 }
 878
 879 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 880 {
 881     musicpal_lcd_state *s = opaque;
 882
 883     switch (offset) {
 884     case MP_LCD_IRQCTRL:
 885         return s->irqctrl;
 886
 887     default:
 888         return 0;
 889     }
 890 }
 891
 892 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 893                                uint32_t value)
 894 {
 895     musicpal_lcd_state *s = opaque;
 896
 897     switch (offset) {
 898     case MP_LCD_IRQCTRL:
 899         s->irqctrl = value;
 900         break;
 901
 902     case MP_LCD_SPICTRL:
 903         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 904             s->mode = value;
 905         else
 906             s->mode = MP_LCD_SPI_INVALID;
 907         break;
 908
 909     case MP_LCD_INST:
 910         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 911             s->page = value - MP_LCD_INST_SETPAGE0;
 912             s->page_off = 0;
 913         }
 914         break;
 915
 916     case MP_LCD_DATA:
 917         if (s->mode == MP_LCD_SPI_CMD) {
 918             if (value >= MP_LCD_INST_SETPAGE0 &&
 919                 value <= MP_LCD_INST_SETPAGE7) {
 920                 s->page = value - MP_LCD_INST_SETPAGE0;
 921                 s->page_off = 0;
 922             }
 923         } else if (s->mode == MP_LCD_SPI_DATA) {
 924             s->video_ram[s->page*128 + s->page_off] = value;
 925             s->page_off = (s->page_off + 1) & 127;
 926         }
 927         break;
 928     }
 929 }
 930
 931 static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
 932     musicpal_lcd_read,
 933     musicpal_lcd_read,
 934     musicpal_lcd_read
 935 };
 936
 937 static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
 938     musicpal_lcd_write,
 939     musicpal_lcd_write,
 940     musicpal_lcd_write
 941 };
 942
 943 static void musicpal_lcd_init(SysBusDevice *dev)
 944 {
 945     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 946     int iomemtype;
 947
 948     iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
 949                                        musicpal_lcd_writefn, s);
 950     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 951     cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);
 952
 953     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 954                                  NULL, NULL, s);
 955     qemu_console_resize(s->ds, 128*3, 64*3);
 956 }
 957
 958 /* PIC register offsets */
 959 #define MP_PIC_STATUS           0x00
 960 #define MP_PIC_ENABLE_SET       0x08
 961 #define MP_PIC_ENABLE_CLR       0x0C
 962
 963 typedef struct mv88w8618_pic_state
 964 {
 965     SysBusDevice busdev;
 966     uint32_t level;
 967     uint32_t enabled;
 968     qemu_irq parent_irq;
 969 } mv88w8618_pic_state;
 970
 971 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 972 {
 973     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 974 }
 975
 976 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 977 {
 978     mv88w8618_pic_state *s = opaque;
 979
 980     if (level)
 981         s->level |= 1 << irq;
 982     else
 983         s->level &= ~(1 << irq);
 984     mv88w8618_pic_update(s);
 985 }
 986
 987 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 988 {
 989     mv88w8618_pic_state *s = opaque;
 990
 991     switch (offset) {
 992     case MP_PIC_STATUS:
 993         return s->level & s->enabled;
 994
 995     default:
 996         return 0;
 997     }
 998 }
 999
1000 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
1001                                 uint32_t value)
1002 {
1003     mv88w8618_pic_state *s = opaque;
1004
1005     switch (offset) {
1006     case MP_PIC_ENABLE_SET:
1007         s->enabled |= value;
1008         break;
1009
1010     case MP_PIC_ENABLE_CLR:
1011         s->enabled &= ~value;
1012         s->level &= ~value;
1013         break;
1014     }
1015     mv88w8618_pic_update(s);
1016 }
1017
1018 static void mv88w8618_pic_reset(void *opaque)
1019 {
1020     mv88w8618_pic_state *s = opaque;
1021
1022     s->level = 0;
1023     s->enabled = 0;
1024 }
1025
1026 static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
1027     mv88w8618_pic_read,
1028     mv88w8618_pic_read,
1029     mv88w8618_pic_read
1030 };
1031
1032 static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1033     mv88w8618_pic_write,
1034     mv88w8618_pic_write,
1035     mv88w8618_pic_write
1036 };
1037
1038 static void mv88w8618_pic_init(SysBusDevice *dev)
1039 {
1040     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
1041     int iomemtype;
1042
1043     qdev_init_irq_sink(&dev->qdev, mv88w8618_pic_set_irq, 32);
1044     sysbus_init_irq(dev, &s->parent_irq);
1045     iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1046                                        mv88w8618_pic_writefn, s);
1047     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
1048
1049     qemu_register_reset(mv88w8618_pic_reset, 0, s);
1050 }
1051
1052 /* PIT register offsets */
1053 #define MP_PIT_TIMER1_LENGTH    0x00
1054 /* ... */
1055 #define MP_PIT_TIMER4_LENGTH    0x0C
1056 #define MP_PIT_CONTROL          0x10
1057 #define MP_PIT_TIMER1_VALUE     0x14
1058 /* ... */
1059 #define MP_PIT_TIMER4_VALUE     0x20
1060 #define MP_BOARD_RESET          0x34
1061
1062 /* Magic board reset value (probably some watchdog behind it) */
1063 #define MP_BOARD_RESET_MAGIC    0x10000
1064
1065 typedef struct mv88w8618_timer_state {
1066     ptimer_state *ptimer;
1067     uint32_t limit;
1068     int freq;
1069     qemu_irq irq;
1070 } mv88w8618_timer_state;
1071
1072 typedef struct mv88w8618_pit_state {
1073     SysBusDevice busdev;
1074     mv88w8618_timer_state timer[4];
1075     uint32_t control;
1076 } mv88w8618_pit_state;
1077
1078 static void mv88w8618_timer_tick(void *opaque)
1079 {
1080     mv88w8618_timer_state *s = opaque;
1081
1082     qemu_irq_raise(s->irq);
1083 }
1084
1085 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
1086                                  uint32_t freq)
1087 {
1088     QEMUBH *bh;
1089
1090     sysbus_init_irq(dev, &s->irq);
1091     s->freq = freq;
1092
1093     bh = qemu_bh_new(mv88w8618_timer_tick, s);
1094     s->ptimer = ptimer_init(bh);
1095 }
1096
1097 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1098 {
1099     mv88w8618_pit_state *s = opaque;
1100     mv88w8618_timer_state *t;
1101
1102     switch (offset) {
1103     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1104         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1105         return ptimer_get_count(t->ptimer);
1106
1107     default:
1108         return 0;
1109     }
1110 }
1111
1112 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1113                                 uint32_t value)
1114 {
1115     mv88w8618_pit_state *s = opaque;
1116     mv88w8618_timer_state *t;
1117     int i;
1118
1119     switch (offset) {
1120     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1121         t = &s->timer[offset >> 2];
1122         t->limit = value;
1123         ptimer_set_limit(t->ptimer, t->limit, 1);
1124         break;
1125
1126     case MP_PIT_CONTROL:
1127         for (i = 0; i < 4; i++) {
1128             if (value & 0xf) {
1129                 t = &s->timer[i];
1130                 ptimer_set_limit(t->ptimer, t->limit, 0);
1131                 ptimer_set_freq(t->ptimer, t->freq);
1132                 ptimer_run(t->ptimer, 0);
1133             }
1134             value >>= 4;
1135         }
1136         break;
1137
1138     case MP_BOARD_RESET:
1139         if (value == MP_BOARD_RESET_MAGIC)
1140             qemu_system_reset_request();
1141         break;
1142     }
1143 }
1144
1145 static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1146     mv88w8618_pit_read,
1147     mv88w8618_pit_read,
1148     mv88w8618_pit_read
1149 };
1150
1151 static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1152     mv88w8618_pit_write,
1153     mv88w8618_pit_write,
1154     mv88w8618_pit_write
1155 };
1156
1157 static void mv88w8618_pit_init(SysBusDevice *dev)
1158 {
1159     int iomemtype;
1160     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
1161     int i;
1162
1163     /* Letting them all run at 1 MHz is likely just a pragmatic
1164      * simplification. */
1165     for (i = 0; i < 4; i++) {
1166         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
1167     }
1168
1169     iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1170                                        mv88w8618_pit_writefn, s);
1171     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
1172 }
1173
1174 /* Flash config register offsets */
1175 #define MP_FLASHCFG_CFGR0    0x04
1176
1177 typedef struct mv88w8618_flashcfg_state {
1178     SysBusDevice busdev;
1179     uint32_t cfgr0;
1180 } mv88w8618_flashcfg_state;
1181
1182 static uint32_t mv88w8618_flashcfg_read(void *opaque,
1183                                         target_phys_addr_t offset)
1184 {
1185     mv88w8618_flashcfg_state *s = opaque;
1186
1187     switch (offset) {
1188     case MP_FLASHCFG_CFGR0:
1189         return s->cfgr0;
1190
1191     default:
1192         return 0;
1193     }
1194 }
1195
1196 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1197                                      uint32_t value)
1198 {
1199     mv88w8618_flashcfg_state *s = opaque;
1200
1201     switch (offset) {
1202     case MP_FLASHCFG_CFGR0:
1203         s->cfgr0 = value;
1204         break;
1205     }
1206 }
1207
1208 static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1209     mv88w8618_flashcfg_read,
1210     mv88w8618_flashcfg_read,
1211     mv88w8618_flashcfg_read
1212 };
1213
1214 static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1215     mv88w8618_flashcfg_write,
1216     mv88w8618_flashcfg_write,
1217     mv88w8618_flashcfg_write
1218 };
1219
1220 static void mv88w8618_flashcfg_init(SysBusDevice *dev)
1221 {
1222     int iomemtype;
1223     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
1224
1225     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1226     iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1227                        mv88w8618_flashcfg_writefn, s);
1228     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
1229 }
1230
1231 /* Misc register offsets */
1232 #define MP_MISC_BOARD_REVISION  0x18
1233
1234 #define MP_BOARD_REVISION       0x31
1235
1236 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
1237 {
1238     switch (offset) {
1239     case MP_MISC_BOARD_REVISION:
1240         return MP_BOARD_REVISION;
1241
1242     default:
1243         return 0;
1244     }
1245 }
1246
1247 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1248                                 uint32_t value)
1249 {
1250 }
1251
1252 static CPUReadMemoryFunc *musicpal_misc_readfn[] = {
1253     musicpal_misc_read,
1254     musicpal_misc_read,
1255     musicpal_misc_read,
1256 };
1257
1258 static CPUWriteMemoryFunc *musicpal_misc_writefn[] = {
1259     musicpal_misc_write,
1260     musicpal_misc_write,
1261     musicpal_misc_write,
1262 };
1263
1264 static void musicpal_misc_init(void)
1265 {
1266     int iomemtype;
1267
1268     iomemtype = cpu_register_io_memory(0, musicpal_misc_readfn,
1269                                        musicpal_misc_writefn, NULL);
1270     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1271 }
1272
1273 /* WLAN register offsets */
1274 #define MP_WLAN_MAGIC1          0x11c
1275 #define MP_WLAN_MAGIC2          0x124
1276
1277 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
1278 {
1279     switch (offset) {
1280     /* Workaround to allow loading the binary-only wlandrv.ko crap
1281      * from the original Freecom firmware. */
1282     case MP_WLAN_MAGIC1:
1283         return ~3;
1284     case MP_WLAN_MAGIC2:
1285         return -1;
1286
1287     default:
1288         return 0;
1289     }
1290 }
1291
1292 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1293                                  uint32_t value)
1294 {
1295 }
1296
1297 static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = {
1298     mv88w8618_wlan_read,
1299     mv88w8618_wlan_read,
1300     mv88w8618_wlan_read,
1301 };
1302
1303 static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = {
1304     mv88w8618_wlan_write,
1305     mv88w8618_wlan_write,
1306     mv88w8618_wlan_write,
1307 };
1308
1309 static void mv88w8618_wlan_init(SysBusDevice *dev)
1310 {
1311     int iomemtype;
1312
1313     iomemtype = cpu_register_io_memory(0, mv88w8618_wlan_readfn,
1314                                        mv88w8618_wlan_writefn, NULL);
1315     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
1316 }
1317
1318 /* GPIO register offsets */
1319 #define MP_GPIO_OE_LO           0x008
1320 #define MP_GPIO_OUT_LO          0x00c
1321 #define MP_GPIO_IN_LO           0x010
1322 #define MP_GPIO_ISR_LO          0x020
1323 #define MP_GPIO_OE_HI           0x508
1324 #define MP_GPIO_OUT_HI          0x50c
1325 #define MP_GPIO_IN_HI           0x510
1326 #define MP_GPIO_ISR_HI          0x520
1327
1328 /* GPIO bits & masks */
1329 #define MP_GPIO_WHEEL_VOL       (1 << 8)
1330 #define MP_GPIO_WHEEL_VOL_INV   (1 << 9)
1331 #define MP_GPIO_WHEEL_NAV       (1 << 10)
1332 #define MP_GPIO_WHEEL_NAV_INV   (1 << 11)
1333 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1334 #define MP_GPIO_BTN_FAVORITS    (1 << 19)
1335 #define MP_GPIO_BTN_MENU        (1 << 20)
1336 #define MP_GPIO_BTN_VOLUME      (1 << 21)
1337 #define MP_GPIO_BTN_NAVIGATION  (1 << 22)
1338 #define MP_GPIO_I2C_DATA_BIT    29
1339 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
1340 #define MP_GPIO_I2C_CLOCK_BIT   30
1341
1342 /* LCD brightness bits in GPIO_OE_HI */
1343 #define MP_OE_LCD_BRIGHTNESS    0x0007
1344
1345 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1346 {
1347     switch (offset) {
1348     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1349         return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1350
1351     case MP_GPIO_OUT_LO:
1352         return gpio_out_state & 0xFFFF;
1353     case MP_GPIO_OUT_HI:
1354         return gpio_out_state >> 16;
1355
1356     case MP_GPIO_IN_LO:
1357         return gpio_in_state & 0xFFFF;
1358     case MP_GPIO_IN_HI:
1359         /* Update received I2C data */
1360         gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1361                         (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1362         return gpio_in_state >> 16;
1363
1364     case MP_GPIO_ISR_LO:
1365         return gpio_isr & 0xFFFF;
1366     case MP_GPIO_ISR_HI:
1367         return gpio_isr >> 16;
1368
1369     default:
1370         return 0;
1371     }
1372 }
1373
1374 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1375                                 uint32_t value)
1376 {
1377     switch (offset) {
1378     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1379         lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1380                          (value & MP_OE_LCD_BRIGHTNESS);
1381         break;
1382
1383     case MP_GPIO_OUT_LO:
1384         gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1385         break;
1386     case MP_GPIO_OUT_HI:
1387         gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1388         lcd_brightness = (lcd_brightness & 0xFFFF) |
1389                          (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1390         i2c_state_update(mixer_i2c,
1391                          (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1392                          (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1393         break;
1394
1395     }
1396 }
1397
1398 static CPUReadMemoryFunc *musicpal_gpio_readfn[] = {
1399     musicpal_gpio_read,
1400     musicpal_gpio_read,
1401     musicpal_gpio_read,
1402 };
1403
1404 static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
1405     musicpal_gpio_write,
1406     musicpal_gpio_write,
1407     musicpal_gpio_write,
1408 };
1409
1410 static void musicpal_gpio_init(void)
1411 {
1412     int iomemtype;
1413
1414     iomemtype = cpu_register_io_memory(0, musicpal_gpio_readfn,
1415                                        musicpal_gpio_writefn, NULL);
1416     cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);
1417 }
1418
1419 /* Keyboard codes & masks */
1420 #define KEY_RELEASED            0x80
1421 #define KEY_CODE                0x7f
1422
1423 #define KEYCODE_TAB             0x0f
1424 #define KEYCODE_ENTER           0x1c
1425 #define KEYCODE_F               0x21
1426 #define KEYCODE_M               0x32
1427
1428 #define KEYCODE_EXTENDED        0xe0
1429 #define KEYCODE_UP              0x48
1430 #define KEYCODE_DOWN            0x50
1431 #define KEYCODE_LEFT            0x4b
1432 #define KEYCODE_RIGHT           0x4d
1433
1434 static void musicpal_key_event(void *opaque, int keycode)
1435 {
1436     qemu_irq irq = opaque;
1437     uint32_t event = 0;
1438     static int kbd_extended;
1439
1440     if (keycode == KEYCODE_EXTENDED) {
1441         kbd_extended = 1;
1442         return;
1443     }
1444
1445     if (kbd_extended)
1446         switch (keycode & KEY_CODE) {
1447         case KEYCODE_UP:
1448             event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1449             break;
1450
1451         case KEYCODE_DOWN:
1452             event = MP_GPIO_WHEEL_NAV;
1453             break;
1454
1455         case KEYCODE_LEFT:
1456             event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1457             break;
1458
1459         case KEYCODE_RIGHT:
1460             event = MP_GPIO_WHEEL_VOL;
1461             break;
1462         }
1463     else {
1464         switch (keycode & KEY_CODE) {
1465         case KEYCODE_F:
1466             event = MP_GPIO_BTN_FAVORITS;
1467             break;
1468
1469         case KEYCODE_TAB:
1470             event = MP_GPIO_BTN_VOLUME;
1471             break;
1472
1473         case KEYCODE_ENTER:
1474             event = MP_GPIO_BTN_NAVIGATION;
1475             break;
1476
1477         case KEYCODE_M:
1478             event = MP_GPIO_BTN_MENU;
1479             break;
1480         }
1481         /* Do not repeat already pressed buttons */
1482         if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1483             event = 0;
1484     }
1485
1486     if (event) {
1487         if (keycode & KEY_RELEASED) {
1488             gpio_in_state |= event;
1489         } else {
1490             gpio_in_state &= ~event;
1491             gpio_isr = event;
1492             qemu_irq_raise(irq);
1493         }
1494     }
1495
1496     kbd_extended = 0;
1497 }
1498
1499 static struct arm_boot_info musicpal_binfo = {
1500     .loader_start = 0x0,
1501     .board_id = 0x20e,
1502 };
1503
1504 static void musicpal_init(ram_addr_t ram_size,
1505                const char *boot_device,
1506                const char *kernel_filename, const char *kernel_cmdline,
1507                const char *initrd_filename, const char *cpu_model)
1508 {
1509     CPUState *env;
1510     qemu_irq *cpu_pic;
1511     qemu_irq pic[32];
1512     DeviceState *dev;
1513     int i;
1514     int index;
1515     unsigned long flash_size;
1516
1517     if (!cpu_model)
1518         cpu_model = "arm926";
1519
1520     env = cpu_init(cpu_model);
1521     if (!env) {
1522         fprintf(stderr, "Unable to find CPU definition\n");
1523         exit(1);
1524     }
1525     cpu_pic = arm_pic_init_cpu(env);
1526
1527     /* For now we use a fixed - the original - RAM size */
1528     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1529                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1530
1531     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1532     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1533
1534     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1535                                cpu_pic[ARM_PIC_CPU_IRQ]);
1536     for (i = 0; i < 32; i++) {
1537         pic[i] = qdev_get_irq_sink(dev, i);
1538     }
1539     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1540                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1541                           pic[MP_TIMER4_IRQ], NULL);
1542
1543     if (serial_hds[0])
1544         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1545                    serial_hds[0], 1);
1546     if (serial_hds[1])
1547         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1548                    serial_hds[1], 1);
1549
1550     /* Register flash */
1551     index = drive_get_index(IF_PFLASH, 0, 0);
1552     if (index != -1) {
1553         flash_size = bdrv_getlength(drives_table[index].bdrv);
1554         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1555             flash_size != 32*1024*1024) {
1556             fprintf(stderr, "Invalid flash image size\n");
1557             exit(1);
1558         }
1559
1560         /*
1561          * The original U-Boot accesses the flash at 0xFE000000 instead of
1562          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1563          * image is smaller than 32 MB.
1564          */
1565         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1566                               drives_table[index].bdrv, 0x10000,
1567                               (flash_size + 0xffff) >> 16,
1568                               MP_FLASH_SIZE_MAX / flash_size,
1569                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1570                               0x5555, 0x2AAA);
1571     }
1572     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1573
1574     sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1575
1576     qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1577
1578     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1579     dev = qdev_create(NULL, "mv88w8618_eth");
1580     qdev_set_netdev(dev, &nd_table[0]);
1581     qdev_init(dev);
1582     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1583     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1584
1585     mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]);
1586
1587     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1588
1589     musicpal_misc_init();
1590     musicpal_gpio_init();
1591
1592     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1593     musicpal_binfo.kernel_filename = kernel_filename;
1594     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1595     musicpal_binfo.initrd_filename = initrd_filename;
1596     arm_load_kernel(env, &musicpal_binfo);
1597 }
1598
1599 static QEMUMachine musicpal_machine = {
1600     .name = "musicpal",
1601     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1602     .init = musicpal_init,
1603 };
1604
1605 static void musicpal_machine_init(void)
1606 {
1607     qemu_register_machine(&musicpal_machine);
1608 }
1609
1610 machine_init(musicpal_machine_init);
1611
1612 static void musicpal_register_devices(void)
1613 {
1614     sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state),
1615                         mv88w8618_pic_init);
1616     sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state),
1617                         mv88w8618_pit_init);
1618     sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state),
1619                         mv88w8618_flashcfg_init);
1620     sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state),
1621                         mv88w8618_eth_init);
1622     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1623                         mv88w8618_wlan_init);
1624     sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state),
1625                         musicpal_lcd_init);
1626 }
1627
1628 device_init(musicpal_register_devices)