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kvm: configure: remove unused depmod_version
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blobdfbb59ad74abdca7bcbcc9651f3c9628ab90aaca
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35 #include "qemu-kvm.h"
36
37 /*
38 * TODO:
39 * - destination write mask support not complete (bits 5..7)
40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
44 //#define DEBUG_CIRRUS
45 //#define DEBUG_BITBLT
46
47 /***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
53 // ID
54 #define CIRRUS_ID_CLGD5422 (0x23<<2)
55 #define CIRRUS_ID_CLGD5426 (0x24<<2)
56 #define CIRRUS_ID_CLGD5424 (0x25<<2)
57 #define CIRRUS_ID_CLGD5428 (0x26<<2)
58 #define CIRRUS_ID_CLGD5430 (0x28<<2)
59 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
60 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
61 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
62
63 // sequencer 0x07
64 #define CIRRUS_SR7_BPP_VGA 0x00
65 #define CIRRUS_SR7_BPP_SVGA 0x01
66 #define CIRRUS_SR7_BPP_MASK 0x0e
67 #define CIRRUS_SR7_BPP_8 0x00
68 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69 #define CIRRUS_SR7_BPP_24 0x04
70 #define CIRRUS_SR7_BPP_16 0x06
71 #define CIRRUS_SR7_BPP_32 0x08
72 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74 // sequencer 0x0f
75 #define CIRRUS_MEMSIZE_512k 0x08
76 #define CIRRUS_MEMSIZE_1M 0x10
77 #define CIRRUS_MEMSIZE_2M 0x18
78 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80 // sequencer 0x12
81 #define CIRRUS_CURSOR_SHOW 0x01
82 #define CIRRUS_CURSOR_HIDDENPEL 0x02
83 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85 // sequencer 0x17
86 #define CIRRUS_BUSTYPE_VLBFAST 0x10
87 #define CIRRUS_BUSTYPE_PCI 0x20
88 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
89 #define CIRRUS_BUSTYPE_ISA 0x38
90 #define CIRRUS_MMIO_ENABLE 0x04
91 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94 // control 0x0b
95 #define CIRRUS_BANKING_DUAL 0x01
96 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98 // control 0x30
99 #define CIRRUS_BLTMODE_BACKWARDS 0x01
100 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
105 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111 // control 0x31
112 #define CIRRUS_BLT_BUSY 0x01
113 #define CIRRUS_BLT_START 0x02
114 #define CIRRUS_BLT_RESET 0x04
115 #define CIRRUS_BLT_FIFOUSED 0x10
116 #define CIRRUS_BLT_AUTOSTART 0x80
117
118 // control 0x32
119 #define CIRRUS_ROP_0 0x00
120 #define CIRRUS_ROP_SRC_AND_DST 0x05
121 #define CIRRUS_ROP_NOP 0x06
122 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123 #define CIRRUS_ROP_NOTDST 0x0b
124 #define CIRRUS_ROP_SRC 0x0d
125 #define CIRRUS_ROP_1 0x0e
126 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127 #define CIRRUS_ROP_SRC_XOR_DST 0x59
128 #define CIRRUS_ROP_SRC_OR_DST 0x6d
129 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132 #define CIRRUS_ROP_NOTSRC 0xd0
133 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
136 #define CIRRUS_ROP_NOP_INDEX 2
137 #define CIRRUS_ROP_SRC_INDEX 5
138
139 // control 0x33
140 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
141 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
142 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
143
144 // memory-mapped IO
145 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
155 #define CIRRUS_MMIO_BLTROP 0x1a // byte
156 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
175 // PCI 0x04: command(word), 0x06(word): status
176 #define PCI_COMMAND_IOACCESS 0x0001
177 #define PCI_COMMAND_MEMACCESS 0x0002
178 #define PCI_COMMAND_BUSMASTER 0x0004
179 #define PCI_COMMAND_SPECIALCYCLE 0x0008
180 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
181 #define PCI_COMMAND_PALETTESNOOPING 0x0020
182 #define PCI_COMMAND_PARITYDETECTION 0x0040
183 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
184 #define PCI_COMMAND_SERR 0x0100
185 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
186 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
187 #define PCI_CLASS_BASE_DISPLAY 0x03
188 // PCI 0x08, 0x00ff0000
189 #define PCI_CLASS_SUB_VGA 0x00
190 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
191 #define PCI_CLASS_HEADERTYPE_00h 0x00
192 // 0x10-0x3f (headertype 00h)
193 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
194 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
195 #define PCI_MAP_MEM 0x0
196 #define PCI_MAP_IO 0x1
197 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
198 #define PCI_MAP_IO_ADDR_MASK (~0x3)
199 #define PCI_MAP_MEMFLAGS_32BIT 0x0
200 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
201 #define PCI_MAP_MEMFLAGS_64BIT 0x4
202 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
203 // PCI 0x28: cardbus CIS pointer
204 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
205 // PCI 0x30: expansion ROM base address
206 #define PCI_ROMBIOS_ENABLED 0x1
207 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
208 // PCI 0x38: reserved
209 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
210
211 #define CIRRUS_PNPMMIO_SIZE 0x1000
212
213
214 /* I/O and memory hook */
215 #define CIRRUS_HOOK_NOT_HANDLED 0
216 #define CIRRUS_HOOK_HANDLED 1
217
218 #define ABS(a) ((signed)(a) > 0 ? a : -a)
219
220 #define BLTUNSAFE(s) \
221 ( \
222 ( /* check dst is within bounds */ \
223 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
224 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
225 (s)->vram_size \
226 ) || \
227 ( /* check src is within bounds */ \
228 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
229 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
230 (s)->vram_size \
231 ) \
232 )
233
234 struct CirrusVGAState;
235 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
236 uint8_t * dst, const uint8_t * src,
237 int dstpitch, int srcpitch,
238 int bltwidth, int bltheight);
239 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
240 uint8_t *dst, int dst_pitch, int width, int height);
241
242 typedef struct CirrusVGAState {
243 VGA_STATE_COMMON
244
245 int cirrus_linear_io_addr;
246 int cirrus_linear_bitblt_io_addr;
247 int cirrus_mmio_io_addr;
248 uint32_t cirrus_addr_mask;
249 uint32_t linear_mmio_mask;
250 uint8_t cirrus_shadow_gr0;
251 uint8_t cirrus_shadow_gr1;
252 uint8_t cirrus_hidden_dac_lockindex;
253 uint8_t cirrus_hidden_dac_data;
254 uint32_t cirrus_bank_base[2];
255 uint32_t cirrus_bank_limit[2];
256 uint8_t cirrus_hidden_palette[48];
257 uint32_t hw_cursor_x;
258 uint32_t hw_cursor_y;
259 int cirrus_blt_pixelwidth;
260 int cirrus_blt_width;
261 int cirrus_blt_height;
262 int cirrus_blt_dstpitch;
263 int cirrus_blt_srcpitch;
264 uint32_t cirrus_blt_fgcol;
265 uint32_t cirrus_blt_bgcol;
266 uint32_t cirrus_blt_dstaddr;
267 uint32_t cirrus_blt_srcaddr;
268 uint8_t cirrus_blt_mode;
269 uint8_t cirrus_blt_modeext;
270 cirrus_bitblt_rop_t cirrus_rop;
271 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
272 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
273 uint8_t *cirrus_srcptr;
274 uint8_t *cirrus_srcptr_end;
275 uint32_t cirrus_srccounter;
276 /* hwcursor display state */
277 int last_hw_cursor_size;
278 int last_hw_cursor_x;
279 int last_hw_cursor_y;
280 int last_hw_cursor_y_start;
281 int last_hw_cursor_y_end;
282 int real_vram_size; /* XXX: suppress that */
283 CPUWriteMemoryFunc **cirrus_linear_write;
284 int device_id;
285 int bustype;
286 } CirrusVGAState;
287
288 typedef struct PCICirrusVGAState {
289 PCIDevice dev;
290 CirrusVGAState cirrus_vga;
291 } PCICirrusVGAState;
292
293 static uint8_t rop_to_index[256];
294
295 /***************************************
296 *
297 * prototypes.
298 *
299 ***************************************/
300
301
302 static void cirrus_bitblt_reset(CirrusVGAState *s);
303 static void cirrus_update_memory_access(CirrusVGAState *s);
304
305 /***************************************
306 *
307 * raster operations
308 *
309 ***************************************/
310
311 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
312 uint8_t *dst,const uint8_t *src,
313 int dstpitch,int srcpitch,
314 int bltwidth,int bltheight)
315 {
316 }
317
318 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
319 uint8_t *dst,
320 int dstpitch, int bltwidth,int bltheight)
321 {
322 }
323
324 #define ROP_NAME 0
325 #define ROP_OP(d, s) d = 0
326 #include "cirrus_vga_rop.h"
327
328 #define ROP_NAME src_and_dst
329 #define ROP_OP(d, s) d = (s) & (d)
330 #include "cirrus_vga_rop.h"
331
332 #define ROP_NAME src_and_notdst
333 #define ROP_OP(d, s) d = (s) & (~(d))
334 #include "cirrus_vga_rop.h"
335
336 #define ROP_NAME notdst
337 #define ROP_OP(d, s) d = ~(d)
338 #include "cirrus_vga_rop.h"
339
340 #define ROP_NAME src
341 #define ROP_OP(d, s) d = s
342 #include "cirrus_vga_rop.h"
343
344 #define ROP_NAME 1
345 #define ROP_OP(d, s) d = ~0
346 #include "cirrus_vga_rop.h"
347
348 #define ROP_NAME notsrc_and_dst
349 #define ROP_OP(d, s) d = (~(s)) & (d)
350 #include "cirrus_vga_rop.h"
351
352 #define ROP_NAME src_xor_dst
353 #define ROP_OP(d, s) d = (s) ^ (d)
354 #include "cirrus_vga_rop.h"
355
356 #define ROP_NAME src_or_dst
357 #define ROP_OP(d, s) d = (s) | (d)
358 #include "cirrus_vga_rop.h"
359
360 #define ROP_NAME notsrc_or_notdst
361 #define ROP_OP(d, s) d = (~(s)) | (~(d))
362 #include "cirrus_vga_rop.h"
363
364 #define ROP_NAME src_notxor_dst
365 #define ROP_OP(d, s) d = ~((s) ^ (d))
366 #include "cirrus_vga_rop.h"
367
368 #define ROP_NAME src_or_notdst
369 #define ROP_OP(d, s) d = (s) | (~(d))
370 #include "cirrus_vga_rop.h"
371
372 #define ROP_NAME notsrc
373 #define ROP_OP(d, s) d = (~(s))
374 #include "cirrus_vga_rop.h"
375
376 #define ROP_NAME notsrc_or_dst
377 #define ROP_OP(d, s) d = (~(s)) | (d)
378 #include "cirrus_vga_rop.h"
379
380 #define ROP_NAME notsrc_and_notdst
381 #define ROP_OP(d, s) d = (~(s)) & (~(d))
382 #include "cirrus_vga_rop.h"
383
384 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
385 cirrus_bitblt_rop_fwd_0,
386 cirrus_bitblt_rop_fwd_src_and_dst,
387 cirrus_bitblt_rop_nop,
388 cirrus_bitblt_rop_fwd_src_and_notdst,
389 cirrus_bitblt_rop_fwd_notdst,
390 cirrus_bitblt_rop_fwd_src,
391 cirrus_bitblt_rop_fwd_1,
392 cirrus_bitblt_rop_fwd_notsrc_and_dst,
393 cirrus_bitblt_rop_fwd_src_xor_dst,
394 cirrus_bitblt_rop_fwd_src_or_dst,
395 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
396 cirrus_bitblt_rop_fwd_src_notxor_dst,
397 cirrus_bitblt_rop_fwd_src_or_notdst,
398 cirrus_bitblt_rop_fwd_notsrc,
399 cirrus_bitblt_rop_fwd_notsrc_or_dst,
400 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
401 };
402
403 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
404 cirrus_bitblt_rop_bkwd_0,
405 cirrus_bitblt_rop_bkwd_src_and_dst,
406 cirrus_bitblt_rop_nop,
407 cirrus_bitblt_rop_bkwd_src_and_notdst,
408 cirrus_bitblt_rop_bkwd_notdst,
409 cirrus_bitblt_rop_bkwd_src,
410 cirrus_bitblt_rop_bkwd_1,
411 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
412 cirrus_bitblt_rop_bkwd_src_xor_dst,
413 cirrus_bitblt_rop_bkwd_src_or_dst,
414 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
415 cirrus_bitblt_rop_bkwd_src_notxor_dst,
416 cirrus_bitblt_rop_bkwd_src_or_notdst,
417 cirrus_bitblt_rop_bkwd_notsrc,
418 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
419 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
420 };
421
422 #define TRANSP_ROP(name) {\
423 name ## _8,\
424 name ## _16,\
425 }
426 #define TRANSP_NOP(func) {\
427 func,\
428 func,\
429 }
430
431 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
434 TRANSP_NOP(cirrus_bitblt_rop_nop),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
448 };
449
450 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
453 TRANSP_NOP(cirrus_bitblt_rop_nop),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
467 };
468
469 #define ROP2(name) {\
470 name ## _8,\
471 name ## _16,\
472 name ## _24,\
473 name ## _32,\
474 }
475
476 #define ROP_NOP2(func) {\
477 func,\
478 func,\
479 func,\
480 func,\
481 }
482
483 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
484 ROP2(cirrus_patternfill_0),
485 ROP2(cirrus_patternfill_src_and_dst),
486 ROP_NOP2(cirrus_bitblt_rop_nop),
487 ROP2(cirrus_patternfill_src_and_notdst),
488 ROP2(cirrus_patternfill_notdst),
489 ROP2(cirrus_patternfill_src),
490 ROP2(cirrus_patternfill_1),
491 ROP2(cirrus_patternfill_notsrc_and_dst),
492 ROP2(cirrus_patternfill_src_xor_dst),
493 ROP2(cirrus_patternfill_src_or_dst),
494 ROP2(cirrus_patternfill_notsrc_or_notdst),
495 ROP2(cirrus_patternfill_src_notxor_dst),
496 ROP2(cirrus_patternfill_src_or_notdst),
497 ROP2(cirrus_patternfill_notsrc),
498 ROP2(cirrus_patternfill_notsrc_or_dst),
499 ROP2(cirrus_patternfill_notsrc_and_notdst),
500 };
501
502 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
503 ROP2(cirrus_colorexpand_transp_0),
504 ROP2(cirrus_colorexpand_transp_src_and_dst),
505 ROP_NOP2(cirrus_bitblt_rop_nop),
506 ROP2(cirrus_colorexpand_transp_src_and_notdst),
507 ROP2(cirrus_colorexpand_transp_notdst),
508 ROP2(cirrus_colorexpand_transp_src),
509 ROP2(cirrus_colorexpand_transp_1),
510 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
511 ROP2(cirrus_colorexpand_transp_src_xor_dst),
512 ROP2(cirrus_colorexpand_transp_src_or_dst),
513 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
514 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
515 ROP2(cirrus_colorexpand_transp_src_or_notdst),
516 ROP2(cirrus_colorexpand_transp_notsrc),
517 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
518 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
519 };
520
521 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
522 ROP2(cirrus_colorexpand_0),
523 ROP2(cirrus_colorexpand_src_and_dst),
524 ROP_NOP2(cirrus_bitblt_rop_nop),
525 ROP2(cirrus_colorexpand_src_and_notdst),
526 ROP2(cirrus_colorexpand_notdst),
527 ROP2(cirrus_colorexpand_src),
528 ROP2(cirrus_colorexpand_1),
529 ROP2(cirrus_colorexpand_notsrc_and_dst),
530 ROP2(cirrus_colorexpand_src_xor_dst),
531 ROP2(cirrus_colorexpand_src_or_dst),
532 ROP2(cirrus_colorexpand_notsrc_or_notdst),
533 ROP2(cirrus_colorexpand_src_notxor_dst),
534 ROP2(cirrus_colorexpand_src_or_notdst),
535 ROP2(cirrus_colorexpand_notsrc),
536 ROP2(cirrus_colorexpand_notsrc_or_dst),
537 ROP2(cirrus_colorexpand_notsrc_and_notdst),
538 };
539
540 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
541 ROP2(cirrus_colorexpand_pattern_transp_0),
542 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
543 ROP_NOP2(cirrus_bitblt_rop_nop),
544 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
545 ROP2(cirrus_colorexpand_pattern_transp_notdst),
546 ROP2(cirrus_colorexpand_pattern_transp_src),
547 ROP2(cirrus_colorexpand_pattern_transp_1),
548 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
549 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
550 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
551 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
552 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
553 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
554 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
557 };
558
559 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
560 ROP2(cirrus_colorexpand_pattern_0),
561 ROP2(cirrus_colorexpand_pattern_src_and_dst),
562 ROP_NOP2(cirrus_bitblt_rop_nop),
563 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
564 ROP2(cirrus_colorexpand_pattern_notdst),
565 ROP2(cirrus_colorexpand_pattern_src),
566 ROP2(cirrus_colorexpand_pattern_1),
567 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
568 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
569 ROP2(cirrus_colorexpand_pattern_src_or_dst),
570 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
571 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
572 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
573 ROP2(cirrus_colorexpand_pattern_notsrc),
574 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
575 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
576 };
577
578 static const cirrus_fill_t cirrus_fill[16][4] = {
579 ROP2(cirrus_fill_0),
580 ROP2(cirrus_fill_src_and_dst),
581 ROP_NOP2(cirrus_bitblt_fill_nop),
582 ROP2(cirrus_fill_src_and_notdst),
583 ROP2(cirrus_fill_notdst),
584 ROP2(cirrus_fill_src),
585 ROP2(cirrus_fill_1),
586 ROP2(cirrus_fill_notsrc_and_dst),
587 ROP2(cirrus_fill_src_xor_dst),
588 ROP2(cirrus_fill_src_or_dst),
589 ROP2(cirrus_fill_notsrc_or_notdst),
590 ROP2(cirrus_fill_src_notxor_dst),
591 ROP2(cirrus_fill_src_or_notdst),
592 ROP2(cirrus_fill_notsrc),
593 ROP2(cirrus_fill_notsrc_or_dst),
594 ROP2(cirrus_fill_notsrc_and_notdst),
595 };
596
597 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
598 {
599 unsigned int color;
600 switch (s->cirrus_blt_pixelwidth) {
601 case 1:
602 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
603 break;
604 case 2:
605 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
606 s->cirrus_blt_fgcol = le16_to_cpu(color);
607 break;
608 case 3:
609 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
610 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
611 break;
612 default:
613 case 4:
614 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
615 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
616 s->cirrus_blt_fgcol = le32_to_cpu(color);
617 break;
618 }
619 }
620
621 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
622 {
623 unsigned int color;
624 switch (s->cirrus_blt_pixelwidth) {
625 case 1:
626 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
627 break;
628 case 2:
629 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
630 s->cirrus_blt_bgcol = le16_to_cpu(color);
631 break;
632 case 3:
633 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
634 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
635 break;
636 default:
637 case 4:
638 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
639 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
640 s->cirrus_blt_bgcol = le32_to_cpu(color);
641 break;
642 }
643 }
644
645 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
646 int off_pitch, int bytesperline,
647 int lines)
648 {
649 int y;
650 int off_cur;
651 int off_cur_end;
652
653 for (y = 0; y < lines; y++) {
654 off_cur = off_begin;
655 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
656 off_cur &= TARGET_PAGE_MASK;
657 while (off_cur < off_cur_end) {
658 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
659 off_cur += TARGET_PAGE_SIZE;
660 }
661 off_begin += off_pitch;
662 }
663 }
664
665 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
666 const uint8_t * src)
667 {
668 uint8_t *dst;
669
670 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
671
672 if (BLTUNSAFE(s))
673 return 0;
674
675 (*s->cirrus_rop) (s, dst, src,
676 s->cirrus_blt_dstpitch, 0,
677 s->cirrus_blt_width, s->cirrus_blt_height);
678 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
679 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
680 s->cirrus_blt_height);
681 return 1;
682 }
683
684 /* fill */
685
686 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
687 {
688 cirrus_fill_t rop_func;
689
690 if (BLTUNSAFE(s))
691 return 0;
692 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
693 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
694 s->cirrus_blt_dstpitch,
695 s->cirrus_blt_width, s->cirrus_blt_height);
696 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
697 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
698 s->cirrus_blt_height);
699 cirrus_bitblt_reset(s);
700 return 1;
701 }
702
703 /***************************************
704 *
705 * bitblt (video-to-video)
706 *
707 ***************************************/
708
709 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
710 {
711 return cirrus_bitblt_common_patterncopy(s,
712 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
713 s->cirrus_addr_mask));
714 }
715
716 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
717 {
718 int sx, sy;
719 int dx, dy;
720 int width, height;
721 int depth;
722 int notify = 0;
723
724 depth = s->get_bpp((VGAState *)s) / 8;
725 s->get_resolution((VGAState *)s, &width, &height);
726
727 /* extra x, y */
728 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
729 sy = (src / ABS(s->cirrus_blt_srcpitch));
730 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
731 dy = (dst / ABS(s->cirrus_blt_dstpitch));
732
733 /* normalize width */
734 w /= depth;
735
736 /* if we're doing a backward copy, we have to adjust
737 our x/y to be the upper left corner (instead of the lower
738 right corner) */
739 if (s->cirrus_blt_dstpitch < 0) {
740 sx -= (s->cirrus_blt_width / depth) - 1;
741 dx -= (s->cirrus_blt_width / depth) - 1;
742 sy -= s->cirrus_blt_height - 1;
743 dy -= s->cirrus_blt_height - 1;
744 }
745
746 /* are we in the visible portion of memory? */
747 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
748 (sx + w) <= width && (sy + h) <= height &&
749 (dx + w) <= width && (dy + h) <= height) {
750 notify = 1;
751 }
752
753 /* make to sure only copy if it's a plain copy ROP */
754 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
755 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
756 notify = 0;
757
758 /* we have to flush all pending changes so that the copy
759 is generated at the appropriate moment in time */
760 if (notify)
761 vga_hw_update();
762
763 (*s->cirrus_rop) (s, s->vram_ptr +
764 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
765 s->vram_ptr +
766 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
767 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
768 s->cirrus_blt_width, s->cirrus_blt_height);
769
770 if (notify)
771 qemu_console_copy(s->ds,
772 sx, sy, dx, dy,
773 s->cirrus_blt_width / depth,
774 s->cirrus_blt_height);
775
776 /* we don't have to notify the display that this portion has
777 changed since qemu_console_copy implies this */
778
779 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
780 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
781 s->cirrus_blt_height);
782 }
783
784 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
785 {
786 if (BLTUNSAFE(s))
787 return 0;
788
789 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
790 s->cirrus_blt_srcaddr - s->start_addr,
791 s->cirrus_blt_width, s->cirrus_blt_height);
792
793 return 1;
794 }
795
796 /***************************************
797 *
798 * bitblt (cpu-to-video)
799 *
800 ***************************************/
801
802 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
803 {
804 int copy_count;
805 uint8_t *end_ptr;
806
807 if (s->cirrus_srccounter > 0) {
808 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
809 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
810 the_end:
811 s->cirrus_srccounter = 0;
812 cirrus_bitblt_reset(s);
813 } else {
814 /* at least one scan line */
815 do {
816 (*s->cirrus_rop)(s, s->vram_ptr +
817 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
818 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
819 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
820 s->cirrus_blt_width, 1);
821 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
822 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
823 if (s->cirrus_srccounter <= 0)
824 goto the_end;
825 /* more bytes than needed can be transfered because of
826 word alignment, so we keep them for the next line */
827 /* XXX: keep alignment to speed up transfer */
828 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
829 copy_count = s->cirrus_srcptr_end - end_ptr;
830 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
831 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
832 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
833 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
834 }
835 }
836 }
837
838 /***************************************
839 *
840 * bitblt wrapper
841 *
842 ***************************************/
843
844 static void cirrus_bitblt_reset(CirrusVGAState * s)
845 {
846 int need_update;
847
848 s->gr[0x31] &=
849 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
850 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
851 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
852 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
853 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
854 s->cirrus_srccounter = 0;
855 if (!need_update)
856 return;
857 cirrus_update_memory_access(s);
858 }
859
860 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
861 {
862 int w;
863
864 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
865 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
866 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
867
868 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
869 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
870 s->cirrus_blt_srcpitch = 8;
871 } else {
872 /* XXX: check for 24 bpp */
873 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
874 }
875 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
876 } else {
877 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
878 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
879 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
880 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
881 else
882 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
883 } else {
884 /* always align input size to 32 bits */
885 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
886 }
887 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
888 }
889 s->cirrus_srcptr = s->cirrus_bltbuf;
890 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
891 cirrus_update_memory_access(s);
892 return 1;
893 }
894
895 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
896 {
897 /* XXX */
898 #ifdef DEBUG_BITBLT
899 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
900 #endif
901 return 0;
902 }
903
904 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
905 {
906 int ret;
907
908 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
909 ret = cirrus_bitblt_videotovideo_patterncopy(s);
910 } else {
911 ret = cirrus_bitblt_videotovideo_copy(s);
912 }
913 if (ret)
914 cirrus_bitblt_reset(s);
915 return ret;
916 }
917
918 static void cirrus_bitblt_start(CirrusVGAState * s)
919 {
920 uint8_t blt_rop;
921
922 s->gr[0x31] |= CIRRUS_BLT_BUSY;
923
924 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
925 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
926 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
927 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
928 s->cirrus_blt_dstaddr =
929 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
930 s->cirrus_blt_srcaddr =
931 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
932 s->cirrus_blt_mode = s->gr[0x30];
933 s->cirrus_blt_modeext = s->gr[0x33];
934 blt_rop = s->gr[0x32];
935
936 #ifdef DEBUG_BITBLT
937 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
938 blt_rop,
939 s->cirrus_blt_mode,
940 s->cirrus_blt_modeext,
941 s->cirrus_blt_width,
942 s->cirrus_blt_height,
943 s->cirrus_blt_dstpitch,
944 s->cirrus_blt_srcpitch,
945 s->cirrus_blt_dstaddr,
946 s->cirrus_blt_srcaddr,
947 s->gr[0x2f]);
948 #endif
949
950 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
951 case CIRRUS_BLTMODE_PIXELWIDTH8:
952 s->cirrus_blt_pixelwidth = 1;
953 break;
954 case CIRRUS_BLTMODE_PIXELWIDTH16:
955 s->cirrus_blt_pixelwidth = 2;
956 break;
957 case CIRRUS_BLTMODE_PIXELWIDTH24:
958 s->cirrus_blt_pixelwidth = 3;
959 break;
960 case CIRRUS_BLTMODE_PIXELWIDTH32:
961 s->cirrus_blt_pixelwidth = 4;
962 break;
963 default:
964 #ifdef DEBUG_BITBLT
965 printf("cirrus: bitblt - pixel width is unknown\n");
966 #endif
967 goto bitblt_ignore;
968 }
969 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
970
971 if ((s->
972 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
973 CIRRUS_BLTMODE_MEMSYSDEST))
974 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
975 #ifdef DEBUG_BITBLT
976 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
977 #endif
978 goto bitblt_ignore;
979 }
980
981 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
982 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
983 CIRRUS_BLTMODE_TRANSPARENTCOMP |
984 CIRRUS_BLTMODE_PATTERNCOPY |
985 CIRRUS_BLTMODE_COLOREXPAND)) ==
986 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
987 cirrus_bitblt_fgcol(s);
988 cirrus_bitblt_solidfill(s, blt_rop);
989 } else {
990 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
991 CIRRUS_BLTMODE_PATTERNCOPY)) ==
992 CIRRUS_BLTMODE_COLOREXPAND) {
993
994 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
995 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
996 cirrus_bitblt_bgcol(s);
997 else
998 cirrus_bitblt_fgcol(s);
999 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1000 } else {
1001 cirrus_bitblt_fgcol(s);
1002 cirrus_bitblt_bgcol(s);
1003 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1004 }
1005 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1006 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1007 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1008 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1009 cirrus_bitblt_bgcol(s);
1010 else
1011 cirrus_bitblt_fgcol(s);
1012 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1013 } else {
1014 cirrus_bitblt_fgcol(s);
1015 cirrus_bitblt_bgcol(s);
1016 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1017 }
1018 } else {
1019 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1020 }
1021 } else {
1022 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1023 if (s->cirrus_blt_pixelwidth > 2) {
1024 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1025 goto bitblt_ignore;
1026 }
1027 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1028 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1029 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1030 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1031 } else {
1032 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1033 }
1034 } else {
1035 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1036 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1037 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1038 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1039 } else {
1040 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1041 }
1042 }
1043 }
1044 // setup bitblt engine.
1045 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1046 if (!cirrus_bitblt_cputovideo(s))
1047 goto bitblt_ignore;
1048 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1049 if (!cirrus_bitblt_videotocpu(s))
1050 goto bitblt_ignore;
1051 } else {
1052 if (!cirrus_bitblt_videotovideo(s))
1053 goto bitblt_ignore;
1054 }
1055 }
1056 return;
1057 bitblt_ignore:;
1058 cirrus_bitblt_reset(s);
1059 }
1060
1061 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1062 {
1063 unsigned old_value;
1064
1065 old_value = s->gr[0x31];
1066 s->gr[0x31] = reg_value;
1067
1068 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1069 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1070 cirrus_bitblt_reset(s);
1071 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1072 ((reg_value & CIRRUS_BLT_START) != 0)) {
1073 cirrus_bitblt_start(s);
1074 }
1075 }
1076
1077
1078 /***************************************
1079 *
1080 * basic parameters
1081 *
1082 ***************************************/
1083
1084 static void cirrus_get_offsets(VGAState *s1,
1085 uint32_t *pline_offset,
1086 uint32_t *pstart_addr,
1087 uint32_t *pline_compare)
1088 {
1089 CirrusVGAState * s = (CirrusVGAState *)s1;
1090 uint32_t start_addr, line_offset, line_compare;
1091
1092 line_offset = s->cr[0x13]
1093 | ((s->cr[0x1b] & 0x10) << 4);
1094 line_offset <<= 3;
1095 *pline_offset = line_offset;
1096
1097 start_addr = (s->cr[0x0c] << 8)
1098 | s->cr[0x0d]
1099 | ((s->cr[0x1b] & 0x01) << 16)
1100 | ((s->cr[0x1b] & 0x0c) << 15)
1101 | ((s->cr[0x1d] & 0x80) << 12);
1102 *pstart_addr = start_addr;
1103
1104 line_compare = s->cr[0x18] |
1105 ((s->cr[0x07] & 0x10) << 4) |
1106 ((s->cr[0x09] & 0x40) << 3);
1107 *pline_compare = line_compare;
1108 }
1109
1110 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1111 {
1112 uint32_t ret = 16;
1113
1114 switch (s->cirrus_hidden_dac_data & 0xf) {
1115 case 0:
1116 ret = 15;
1117 break; /* Sierra HiColor */
1118 case 1:
1119 ret = 16;
1120 break; /* XGA HiColor */
1121 default:
1122 #ifdef DEBUG_CIRRUS
1123 printf("cirrus: invalid DAC value %x in 16bpp\n",
1124 (s->cirrus_hidden_dac_data & 0xf));
1125 #endif
1126 ret = 15; /* XXX */
1127 break;
1128 }
1129 return ret;
1130 }
1131
1132 static int cirrus_get_bpp(VGAState *s1)
1133 {
1134 CirrusVGAState * s = (CirrusVGAState *)s1;
1135 uint32_t ret = 8;
1136
1137 if ((s->sr[0x07] & 0x01) != 0) {
1138 /* Cirrus SVGA */
1139 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1140 case CIRRUS_SR7_BPP_8:
1141 ret = 8;
1142 break;
1143 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1144 ret = cirrus_get_bpp16_depth(s);
1145 break;
1146 case CIRRUS_SR7_BPP_24:
1147 ret = 24;
1148 break;
1149 case CIRRUS_SR7_BPP_16:
1150 ret = cirrus_get_bpp16_depth(s);
1151 break;
1152 case CIRRUS_SR7_BPP_32:
1153 ret = 32;
1154 break;
1155 default:
1156 #ifdef DEBUG_CIRRUS
1157 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1158 #endif
1159 ret = 8;
1160 break;
1161 }
1162 } else {
1163 /* VGA */
1164 ret = 0;
1165 }
1166
1167 return ret;
1168 }
1169
1170 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1171 {
1172 int width, height;
1173
1174 width = (s->cr[0x01] + 1) * 8;
1175 height = s->cr[0x12] |
1176 ((s->cr[0x07] & 0x02) << 7) |
1177 ((s->cr[0x07] & 0x40) << 3);
1178 height = (height + 1);
1179 /* interlace support */
1180 if (s->cr[0x1a] & 0x01)
1181 height = height * 2;
1182 *pwidth = width;
1183 *pheight = height;
1184 }
1185
1186 /***************************************
1187 *
1188 * bank memory
1189 *
1190 ***************************************/
1191
1192 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1193 {
1194 unsigned offset;
1195 unsigned limit;
1196
1197 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1198 offset = s->gr[0x09 + bank_index];
1199 else /* single bank */
1200 offset = s->gr[0x09];
1201
1202 if ((s->gr[0x0b] & 0x20) != 0)
1203 offset <<= 14;
1204 else
1205 offset <<= 12;
1206
1207 if (s->real_vram_size <= offset)
1208 limit = 0;
1209 else
1210 limit = s->real_vram_size - offset;
1211
1212 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1213 if (limit > 0x8000) {
1214 offset += 0x8000;
1215 limit -= 0x8000;
1216 } else {
1217 limit = 0;
1218 }
1219 }
1220
1221 if (limit > 0) {
1222 /* Thinking about changing bank base? First, drop the dirty bitmap information
1223 * on the current location, otherwise we lose this pointer forever */
1224 if (s->lfb_vram_mapped) {
1225 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1226 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1227 }
1228 s->cirrus_bank_base[bank_index] = offset;
1229 s->cirrus_bank_limit[bank_index] = limit;
1230 } else {
1231 s->cirrus_bank_base[bank_index] = 0;
1232 s->cirrus_bank_limit[bank_index] = 0;
1233 }
1234 }
1235
1236 /***************************************
1237 *
1238 * I/O access between 0x3c4-0x3c5
1239 *
1240 ***************************************/
1241
1242 static int
1243 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1244 {
1245 switch (reg_index) {
1246 case 0x00: // Standard VGA
1247 case 0x01: // Standard VGA
1248 case 0x02: // Standard VGA
1249 case 0x03: // Standard VGA
1250 case 0x04: // Standard VGA
1251 return CIRRUS_HOOK_NOT_HANDLED;
1252 case 0x06: // Unlock Cirrus extensions
1253 *reg_value = s->sr[reg_index];
1254 break;
1255 case 0x10:
1256 case 0x30:
1257 case 0x50:
1258 case 0x70: // Graphics Cursor X
1259 case 0x90:
1260 case 0xb0:
1261 case 0xd0:
1262 case 0xf0: // Graphics Cursor X
1263 *reg_value = s->sr[0x10];
1264 break;
1265 case 0x11:
1266 case 0x31:
1267 case 0x51:
1268 case 0x71: // Graphics Cursor Y
1269 case 0x91:
1270 case 0xb1:
1271 case 0xd1:
1272 case 0xf1: // Graphics Cursor Y
1273 *reg_value = s->sr[0x11];
1274 break;
1275 case 0x05: // ???
1276 case 0x07: // Extended Sequencer Mode
1277 case 0x08: // EEPROM Control
1278 case 0x09: // Scratch Register 0
1279 case 0x0a: // Scratch Register 1
1280 case 0x0b: // VCLK 0
1281 case 0x0c: // VCLK 1
1282 case 0x0d: // VCLK 2
1283 case 0x0e: // VCLK 3
1284 case 0x0f: // DRAM Control
1285 case 0x12: // Graphics Cursor Attribute
1286 case 0x13: // Graphics Cursor Pattern Address
1287 case 0x14: // Scratch Register 2
1288 case 0x15: // Scratch Register 3
1289 case 0x16: // Performance Tuning Register
1290 case 0x17: // Configuration Readback and Extended Control
1291 case 0x18: // Signature Generator Control
1292 case 0x19: // Signal Generator Result
1293 case 0x1a: // Signal Generator Result
1294 case 0x1b: // VCLK 0 Denominator & Post
1295 case 0x1c: // VCLK 1 Denominator & Post
1296 case 0x1d: // VCLK 2 Denominator & Post
1297 case 0x1e: // VCLK 3 Denominator & Post
1298 case 0x1f: // BIOS Write Enable and MCLK select
1299 #ifdef DEBUG_CIRRUS
1300 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1301 #endif
1302 *reg_value = s->sr[reg_index];
1303 break;
1304 default:
1305 #ifdef DEBUG_CIRRUS
1306 printf("cirrus: inport sr_index %02x\n", reg_index);
1307 #endif
1308 *reg_value = 0xff;
1309 break;
1310 }
1311
1312 return CIRRUS_HOOK_HANDLED;
1313 }
1314
1315 static int
1316 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1317 {
1318 switch (reg_index) {
1319 case 0x00: // Standard VGA
1320 case 0x01: // Standard VGA
1321 case 0x02: // Standard VGA
1322 case 0x03: // Standard VGA
1323 case 0x04: // Standard VGA
1324 return CIRRUS_HOOK_NOT_HANDLED;
1325 case 0x06: // Unlock Cirrus extensions
1326 reg_value &= 0x17;
1327 if (reg_value == 0x12) {
1328 s->sr[reg_index] = 0x12;
1329 } else {
1330 s->sr[reg_index] = 0x0f;
1331 }
1332 break;
1333 case 0x10:
1334 case 0x30:
1335 case 0x50:
1336 case 0x70: // Graphics Cursor X
1337 case 0x90:
1338 case 0xb0:
1339 case 0xd0:
1340 case 0xf0: // Graphics Cursor X
1341 s->sr[0x10] = reg_value;
1342 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1343 break;
1344 case 0x11:
1345 case 0x31:
1346 case 0x51:
1347 case 0x71: // Graphics Cursor Y
1348 case 0x91:
1349 case 0xb1:
1350 case 0xd1:
1351 case 0xf1: // Graphics Cursor Y
1352 s->sr[0x11] = reg_value;
1353 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1354 break;
1355 case 0x07: // Extended Sequencer Mode
1356 cirrus_update_memory_access(s);
1357 case 0x08: // EEPROM Control
1358 case 0x09: // Scratch Register 0
1359 case 0x0a: // Scratch Register 1
1360 case 0x0b: // VCLK 0
1361 case 0x0c: // VCLK 1
1362 case 0x0d: // VCLK 2
1363 case 0x0e: // VCLK 3
1364 case 0x0f: // DRAM Control
1365 case 0x12: // Graphics Cursor Attribute
1366 case 0x13: // Graphics Cursor Pattern Address
1367 case 0x14: // Scratch Register 2
1368 case 0x15: // Scratch Register 3
1369 case 0x16: // Performance Tuning Register
1370 case 0x18: // Signature Generator Control
1371 case 0x19: // Signature Generator Result
1372 case 0x1a: // Signature Generator Result
1373 case 0x1b: // VCLK 0 Denominator & Post
1374 case 0x1c: // VCLK 1 Denominator & Post
1375 case 0x1d: // VCLK 2 Denominator & Post
1376 case 0x1e: // VCLK 3 Denominator & Post
1377 case 0x1f: // BIOS Write Enable and MCLK select
1378 s->sr[reg_index] = reg_value;
1379 #ifdef DEBUG_CIRRUS
1380 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1381 reg_index, reg_value);
1382 #endif
1383 break;
1384 case 0x17: // Configuration Readback and Extended Control
1385 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1386 cirrus_update_memory_access(s);
1387 break;
1388 default:
1389 #ifdef DEBUG_CIRRUS
1390 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1391 reg_value);
1392 #endif
1393 break;
1394 }
1395
1396 return CIRRUS_HOOK_HANDLED;
1397 }
1398
1399 /***************************************
1400 *
1401 * I/O access at 0x3c6
1402 *
1403 ***************************************/
1404
1405 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1406 {
1407 *reg_value = 0xff;
1408 if (++s->cirrus_hidden_dac_lockindex == 5) {
1409 *reg_value = s->cirrus_hidden_dac_data;
1410 s->cirrus_hidden_dac_lockindex = 0;
1411 }
1412 }
1413
1414 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1415 {
1416 if (s->cirrus_hidden_dac_lockindex == 4) {
1417 s->cirrus_hidden_dac_data = reg_value;
1418 #if defined(DEBUG_CIRRUS)
1419 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1420 #endif
1421 }
1422 s->cirrus_hidden_dac_lockindex = 0;
1423 }
1424
1425 /***************************************
1426 *
1427 * I/O access at 0x3c9
1428 *
1429 ***************************************/
1430
1431 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1432 {
1433 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1434 return CIRRUS_HOOK_NOT_HANDLED;
1435 *reg_value =
1436 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1437 s->dac_sub_index];
1438 if (++s->dac_sub_index == 3) {
1439 s->dac_sub_index = 0;
1440 s->dac_read_index++;
1441 }
1442 return CIRRUS_HOOK_HANDLED;
1443 }
1444
1445 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1446 {
1447 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1448 return CIRRUS_HOOK_NOT_HANDLED;
1449 s->dac_cache[s->dac_sub_index] = reg_value;
1450 if (++s->dac_sub_index == 3) {
1451 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1452 s->dac_cache, 3);
1453 /* XXX update cursor */
1454 s->dac_sub_index = 0;
1455 s->dac_write_index++;
1456 }
1457 return CIRRUS_HOOK_HANDLED;
1458 }
1459
1460 /***************************************
1461 *
1462 * I/O access between 0x3ce-0x3cf
1463 *
1464 ***************************************/
1465
1466 static int
1467 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1468 {
1469 switch (reg_index) {
1470 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1471 *reg_value = s->cirrus_shadow_gr0;
1472 return CIRRUS_HOOK_HANDLED;
1473 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1474 *reg_value = s->cirrus_shadow_gr1;
1475 return CIRRUS_HOOK_HANDLED;
1476 case 0x02: // Standard VGA
1477 case 0x03: // Standard VGA
1478 case 0x04: // Standard VGA
1479 case 0x06: // Standard VGA
1480 case 0x07: // Standard VGA
1481 case 0x08: // Standard VGA
1482 return CIRRUS_HOOK_NOT_HANDLED;
1483 case 0x05: // Standard VGA, Cirrus extended mode
1484 default:
1485 break;
1486 }
1487
1488 if (reg_index < 0x3a) {
1489 *reg_value = s->gr[reg_index];
1490 } else {
1491 #ifdef DEBUG_CIRRUS
1492 printf("cirrus: inport gr_index %02x\n", reg_index);
1493 #endif
1494 *reg_value = 0xff;
1495 }
1496
1497 return CIRRUS_HOOK_HANDLED;
1498 }
1499
1500 static int
1501 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1502 {
1503 #if defined(DEBUG_BITBLT) && 0
1504 printf("gr%02x: %02x\n", reg_index, reg_value);
1505 #endif
1506 switch (reg_index) {
1507 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1508 s->cirrus_shadow_gr0 = reg_value;
1509 return CIRRUS_HOOK_NOT_HANDLED;
1510 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1511 s->cirrus_shadow_gr1 = reg_value;
1512 return CIRRUS_HOOK_NOT_HANDLED;
1513 case 0x02: // Standard VGA
1514 case 0x03: // Standard VGA
1515 case 0x04: // Standard VGA
1516 case 0x06: // Standard VGA
1517 case 0x07: // Standard VGA
1518 case 0x08: // Standard VGA
1519 return CIRRUS_HOOK_NOT_HANDLED;
1520 case 0x05: // Standard VGA, Cirrus extended mode
1521 s->gr[reg_index] = reg_value & 0x7f;
1522 cirrus_update_memory_access(s);
1523 break;
1524 case 0x09: // bank offset #0
1525 case 0x0A: // bank offset #1
1526 s->gr[reg_index] = reg_value;
1527 cirrus_update_bank_ptr(s, 0);
1528 cirrus_update_bank_ptr(s, 1);
1529 cirrus_update_memory_access(s);
1530 break;
1531 case 0x0B:
1532 s->gr[reg_index] = reg_value;
1533 cirrus_update_bank_ptr(s, 0);
1534 cirrus_update_bank_ptr(s, 1);
1535 cirrus_update_memory_access(s);
1536 break;
1537 case 0x10: // BGCOLOR 0x0000ff00
1538 case 0x11: // FGCOLOR 0x0000ff00
1539 case 0x12: // BGCOLOR 0x00ff0000
1540 case 0x13: // FGCOLOR 0x00ff0000
1541 case 0x14: // BGCOLOR 0xff000000
1542 case 0x15: // FGCOLOR 0xff000000
1543 case 0x20: // BLT WIDTH 0x0000ff
1544 case 0x22: // BLT HEIGHT 0x0000ff
1545 case 0x24: // BLT DEST PITCH 0x0000ff
1546 case 0x26: // BLT SRC PITCH 0x0000ff
1547 case 0x28: // BLT DEST ADDR 0x0000ff
1548 case 0x29: // BLT DEST ADDR 0x00ff00
1549 case 0x2c: // BLT SRC ADDR 0x0000ff
1550 case 0x2d: // BLT SRC ADDR 0x00ff00
1551 case 0x2f: // BLT WRITEMASK
1552 case 0x30: // BLT MODE
1553 case 0x32: // RASTER OP
1554 case 0x33: // BLT MODEEXT
1555 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1556 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1557 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1558 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1559 s->gr[reg_index] = reg_value;
1560 break;
1561 case 0x21: // BLT WIDTH 0x001f00
1562 case 0x23: // BLT HEIGHT 0x001f00
1563 case 0x25: // BLT DEST PITCH 0x001f00
1564 case 0x27: // BLT SRC PITCH 0x001f00
1565 s->gr[reg_index] = reg_value & 0x1f;
1566 break;
1567 case 0x2a: // BLT DEST ADDR 0x3f0000
1568 s->gr[reg_index] = reg_value & 0x3f;
1569 /* if auto start mode, starts bit blt now */
1570 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1571 cirrus_bitblt_start(s);
1572 }
1573 break;
1574 case 0x2e: // BLT SRC ADDR 0x3f0000
1575 s->gr[reg_index] = reg_value & 0x3f;
1576 break;
1577 case 0x31: // BLT STATUS/START
1578 cirrus_write_bitblt(s, reg_value);
1579 break;
1580 default:
1581 #ifdef DEBUG_CIRRUS
1582 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1583 reg_value);
1584 #endif
1585 break;
1586 }
1587
1588 return CIRRUS_HOOK_HANDLED;
1589 }
1590
1591 /***************************************
1592 *
1593 * I/O access between 0x3d4-0x3d5
1594 *
1595 ***************************************/
1596
1597 static int
1598 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1599 {
1600 switch (reg_index) {
1601 case 0x00: // Standard VGA
1602 case 0x01: // Standard VGA
1603 case 0x02: // Standard VGA
1604 case 0x03: // Standard VGA
1605 case 0x04: // Standard VGA
1606 case 0x05: // Standard VGA
1607 case 0x06: // Standard VGA
1608 case 0x07: // Standard VGA
1609 case 0x08: // Standard VGA
1610 case 0x09: // Standard VGA
1611 case 0x0a: // Standard VGA
1612 case 0x0b: // Standard VGA
1613 case 0x0c: // Standard VGA
1614 case 0x0d: // Standard VGA
1615 case 0x0e: // Standard VGA
1616 case 0x0f: // Standard VGA
1617 case 0x10: // Standard VGA
1618 case 0x11: // Standard VGA
1619 case 0x12: // Standard VGA
1620 case 0x13: // Standard VGA
1621 case 0x14: // Standard VGA
1622 case 0x15: // Standard VGA
1623 case 0x16: // Standard VGA
1624 case 0x17: // Standard VGA
1625 case 0x18: // Standard VGA
1626 return CIRRUS_HOOK_NOT_HANDLED;
1627 case 0x24: // Attribute Controller Toggle Readback (R)
1628 *reg_value = (s->ar_flip_flop << 7);
1629 break;
1630 case 0x19: // Interlace End
1631 case 0x1a: // Miscellaneous Control
1632 case 0x1b: // Extended Display Control
1633 case 0x1c: // Sync Adjust and Genlock
1634 case 0x1d: // Overlay Extended Control
1635 case 0x22: // Graphics Data Latches Readback (R)
1636 case 0x25: // Part Status
1637 case 0x27: // Part ID (R)
1638 *reg_value = s->cr[reg_index];
1639 break;
1640 case 0x26: // Attribute Controller Index Readback (R)
1641 *reg_value = s->ar_index & 0x3f;
1642 break;
1643 default:
1644 #ifdef DEBUG_CIRRUS
1645 printf("cirrus: inport cr_index %02x\n", reg_index);
1646 *reg_value = 0xff;
1647 #endif
1648 break;
1649 }
1650
1651 return CIRRUS_HOOK_HANDLED;
1652 }
1653
1654 static int
1655 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1656 {
1657 switch (reg_index) {
1658 case 0x00: // Standard VGA
1659 case 0x01: // Standard VGA
1660 case 0x02: // Standard VGA
1661 case 0x03: // Standard VGA
1662 case 0x04: // Standard VGA
1663 case 0x05: // Standard VGA
1664 case 0x06: // Standard VGA
1665 case 0x07: // Standard VGA
1666 case 0x08: // Standard VGA
1667 case 0x09: // Standard VGA
1668 case 0x0a: // Standard VGA
1669 case 0x0b: // Standard VGA
1670 case 0x0c: // Standard VGA
1671 case 0x0d: // Standard VGA
1672 case 0x0e: // Standard VGA
1673 case 0x0f: // Standard VGA
1674 case 0x10: // Standard VGA
1675 case 0x11: // Standard VGA
1676 case 0x12: // Standard VGA
1677 case 0x13: // Standard VGA
1678 case 0x14: // Standard VGA
1679 case 0x15: // Standard VGA
1680 case 0x16: // Standard VGA
1681 case 0x17: // Standard VGA
1682 case 0x18: // Standard VGA
1683 return CIRRUS_HOOK_NOT_HANDLED;
1684 case 0x19: // Interlace End
1685 case 0x1a: // Miscellaneous Control
1686 case 0x1b: // Extended Display Control
1687 case 0x1c: // Sync Adjust and Genlock
1688 case 0x1d: // Overlay Extended Control
1689 s->cr[reg_index] = reg_value;
1690 #ifdef DEBUG_CIRRUS
1691 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1692 reg_index, reg_value);
1693 #endif
1694 break;
1695 case 0x22: // Graphics Data Latches Readback (R)
1696 case 0x24: // Attribute Controller Toggle Readback (R)
1697 case 0x26: // Attribute Controller Index Readback (R)
1698 case 0x27: // Part ID (R)
1699 break;
1700 case 0x25: // Part Status
1701 default:
1702 #ifdef DEBUG_CIRRUS
1703 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1704 reg_value);
1705 #endif
1706 break;
1707 }
1708
1709 return CIRRUS_HOOK_HANDLED;
1710 }
1711
1712 /***************************************
1713 *
1714 * memory-mapped I/O (bitblt)
1715 *
1716 ***************************************/
1717
1718 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1719 {
1720 int value = 0xff;
1721
1722 switch (address) {
1723 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1724 cirrus_hook_read_gr(s, 0x00, &value);
1725 break;
1726 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1727 cirrus_hook_read_gr(s, 0x10, &value);
1728 break;
1729 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1730 cirrus_hook_read_gr(s, 0x12, &value);
1731 break;
1732 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1733 cirrus_hook_read_gr(s, 0x14, &value);
1734 break;
1735 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1736 cirrus_hook_read_gr(s, 0x01, &value);
1737 break;
1738 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1739 cirrus_hook_read_gr(s, 0x11, &value);
1740 break;
1741 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1742 cirrus_hook_read_gr(s, 0x13, &value);
1743 break;
1744 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1745 cirrus_hook_read_gr(s, 0x15, &value);
1746 break;
1747 case (CIRRUS_MMIO_BLTWIDTH + 0):
1748 cirrus_hook_read_gr(s, 0x20, &value);
1749 break;
1750 case (CIRRUS_MMIO_BLTWIDTH + 1):
1751 cirrus_hook_read_gr(s, 0x21, &value);
1752 break;
1753 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1754 cirrus_hook_read_gr(s, 0x22, &value);
1755 break;
1756 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1757 cirrus_hook_read_gr(s, 0x23, &value);
1758 break;
1759 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1760 cirrus_hook_read_gr(s, 0x24, &value);
1761 break;
1762 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1763 cirrus_hook_read_gr(s, 0x25, &value);
1764 break;
1765 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1766 cirrus_hook_read_gr(s, 0x26, &value);
1767 break;
1768 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1769 cirrus_hook_read_gr(s, 0x27, &value);
1770 break;
1771 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1772 cirrus_hook_read_gr(s, 0x28, &value);
1773 break;
1774 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1775 cirrus_hook_read_gr(s, 0x29, &value);
1776 break;
1777 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1778 cirrus_hook_read_gr(s, 0x2a, &value);
1779 break;
1780 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1781 cirrus_hook_read_gr(s, 0x2c, &value);
1782 break;
1783 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1784 cirrus_hook_read_gr(s, 0x2d, &value);
1785 break;
1786 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1787 cirrus_hook_read_gr(s, 0x2e, &value);
1788 break;
1789 case CIRRUS_MMIO_BLTWRITEMASK:
1790 cirrus_hook_read_gr(s, 0x2f, &value);
1791 break;
1792 case CIRRUS_MMIO_BLTMODE:
1793 cirrus_hook_read_gr(s, 0x30, &value);
1794 break;
1795 case CIRRUS_MMIO_BLTROP:
1796 cirrus_hook_read_gr(s, 0x32, &value);
1797 break;
1798 case CIRRUS_MMIO_BLTMODEEXT:
1799 cirrus_hook_read_gr(s, 0x33, &value);
1800 break;
1801 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1802 cirrus_hook_read_gr(s, 0x34, &value);
1803 break;
1804 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1805 cirrus_hook_read_gr(s, 0x35, &value);
1806 break;
1807 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1808 cirrus_hook_read_gr(s, 0x38, &value);
1809 break;
1810 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1811 cirrus_hook_read_gr(s, 0x39, &value);
1812 break;
1813 case CIRRUS_MMIO_BLTSTATUS:
1814 cirrus_hook_read_gr(s, 0x31, &value);
1815 break;
1816 default:
1817 #ifdef DEBUG_CIRRUS
1818 printf("cirrus: mmio read - address 0x%04x\n", address);
1819 #endif
1820 break;
1821 }
1822
1823 return (uint8_t) value;
1824 }
1825
1826 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1827 uint8_t value)
1828 {
1829 switch (address) {
1830 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1831 cirrus_hook_write_gr(s, 0x00, value);
1832 break;
1833 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1834 cirrus_hook_write_gr(s, 0x10, value);
1835 break;
1836 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1837 cirrus_hook_write_gr(s, 0x12, value);
1838 break;
1839 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1840 cirrus_hook_write_gr(s, 0x14, value);
1841 break;
1842 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1843 cirrus_hook_write_gr(s, 0x01, value);
1844 break;
1845 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1846 cirrus_hook_write_gr(s, 0x11, value);
1847 break;
1848 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1849 cirrus_hook_write_gr(s, 0x13, value);
1850 break;
1851 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1852 cirrus_hook_write_gr(s, 0x15, value);
1853 break;
1854 case (CIRRUS_MMIO_BLTWIDTH + 0):
1855 cirrus_hook_write_gr(s, 0x20, value);
1856 break;
1857 case (CIRRUS_MMIO_BLTWIDTH + 1):
1858 cirrus_hook_write_gr(s, 0x21, value);
1859 break;
1860 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1861 cirrus_hook_write_gr(s, 0x22, value);
1862 break;
1863 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1864 cirrus_hook_write_gr(s, 0x23, value);
1865 break;
1866 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1867 cirrus_hook_write_gr(s, 0x24, value);
1868 break;
1869 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1870 cirrus_hook_write_gr(s, 0x25, value);
1871 break;
1872 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1873 cirrus_hook_write_gr(s, 0x26, value);
1874 break;
1875 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1876 cirrus_hook_write_gr(s, 0x27, value);
1877 break;
1878 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1879 cirrus_hook_write_gr(s, 0x28, value);
1880 break;
1881 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1882 cirrus_hook_write_gr(s, 0x29, value);
1883 break;
1884 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1885 cirrus_hook_write_gr(s, 0x2a, value);
1886 break;
1887 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1888 /* ignored */
1889 break;
1890 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1891 cirrus_hook_write_gr(s, 0x2c, value);
1892 break;
1893 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1894 cirrus_hook_write_gr(s, 0x2d, value);
1895 break;
1896 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1897 cirrus_hook_write_gr(s, 0x2e, value);
1898 break;
1899 case CIRRUS_MMIO_BLTWRITEMASK:
1900 cirrus_hook_write_gr(s, 0x2f, value);
1901 break;
1902 case CIRRUS_MMIO_BLTMODE:
1903 cirrus_hook_write_gr(s, 0x30, value);
1904 break;
1905 case CIRRUS_MMIO_BLTROP:
1906 cirrus_hook_write_gr(s, 0x32, value);
1907 break;
1908 case CIRRUS_MMIO_BLTMODEEXT:
1909 cirrus_hook_write_gr(s, 0x33, value);
1910 break;
1911 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1912 cirrus_hook_write_gr(s, 0x34, value);
1913 break;
1914 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1915 cirrus_hook_write_gr(s, 0x35, value);
1916 break;
1917 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1918 cirrus_hook_write_gr(s, 0x38, value);
1919 break;
1920 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1921 cirrus_hook_write_gr(s, 0x39, value);
1922 break;
1923 case CIRRUS_MMIO_BLTSTATUS:
1924 cirrus_hook_write_gr(s, 0x31, value);
1925 break;
1926 default:
1927 #ifdef DEBUG_CIRRUS
1928 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1929 address, value);
1930 #endif
1931 break;
1932 }
1933 }
1934
1935 /***************************************
1936 *
1937 * write mode 4/5
1938 *
1939 * assume TARGET_PAGE_SIZE >= 16
1940 *
1941 ***************************************/
1942
1943 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1944 unsigned mode,
1945 unsigned offset,
1946 uint32_t mem_value)
1947 {
1948 int x;
1949 unsigned val = mem_value;
1950 uint8_t *dst;
1951
1952 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1953 for (x = 0; x < 8; x++) {
1954 if (val & 0x80) {
1955 *dst = s->cirrus_shadow_gr1;
1956 } else if (mode == 5) {
1957 *dst = s->cirrus_shadow_gr0;
1958 }
1959 val <<= 1;
1960 dst++;
1961 }
1962 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1963 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1964 }
1965
1966 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1967 unsigned mode,
1968 unsigned offset,
1969 uint32_t mem_value)
1970 {
1971 int x;
1972 unsigned val = mem_value;
1973 uint8_t *dst;
1974
1975 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1976 for (x = 0; x < 8; x++) {
1977 if (val & 0x80) {
1978 *dst = s->cirrus_shadow_gr1;
1979 *(dst + 1) = s->gr[0x11];
1980 } else if (mode == 5) {
1981 *dst = s->cirrus_shadow_gr0;
1982 *(dst + 1) = s->gr[0x10];
1983 }
1984 val <<= 1;
1985 dst += 2;
1986 }
1987 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1988 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1989 }
1990
1991 /***************************************
1992 *
1993 * memory access between 0xa0000-0xbffff
1994 *
1995 ***************************************/
1996
1997 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1998 {
1999 CirrusVGAState *s = opaque;
2000 unsigned bank_index;
2001 unsigned bank_offset;
2002 uint32_t val;
2003
2004 if ((s->sr[0x07] & 0x01) == 0) {
2005 return vga_mem_readb(s, addr);
2006 }
2007
2008 addr &= 0x1ffff;
2009
2010 if (addr < 0x10000) {
2011 /* XXX handle bitblt */
2012 /* video memory */
2013 bank_index = addr >> 15;
2014 bank_offset = addr & 0x7fff;
2015 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2016 bank_offset += s->cirrus_bank_base[bank_index];
2017 if ((s->gr[0x0B] & 0x14) == 0x14) {
2018 bank_offset <<= 4;
2019 } else if (s->gr[0x0B] & 0x02) {
2020 bank_offset <<= 3;
2021 }
2022 bank_offset &= s->cirrus_addr_mask;
2023 val = *(s->vram_ptr + bank_offset);
2024 } else
2025 val = 0xff;
2026 } else if (addr >= 0x18000 && addr < 0x18100) {
2027 /* memory-mapped I/O */
2028 val = 0xff;
2029 if ((s->sr[0x17] & 0x44) == 0x04) {
2030 val = cirrus_mmio_blt_read(s, addr & 0xff);
2031 }
2032 } else {
2033 val = 0xff;
2034 #ifdef DEBUG_CIRRUS
2035 printf("cirrus: mem_readb %06x\n", addr);
2036 #endif
2037 }
2038 return val;
2039 }
2040
2041 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2042 {
2043 uint32_t v;
2044 #ifdef TARGET_WORDS_BIGENDIAN
2045 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2046 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2047 #else
2048 v = cirrus_vga_mem_readb(opaque, addr);
2049 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2050 #endif
2051 return v;
2052 }
2053
2054 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2055 {
2056 uint32_t v;
2057 #ifdef TARGET_WORDS_BIGENDIAN
2058 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2059 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2060 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2061 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2062 #else
2063 v = cirrus_vga_mem_readb(opaque, addr);
2064 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2065 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2066 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2067 #endif
2068 return v;
2069 }
2070
2071 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2072 uint32_t mem_value)
2073 {
2074 CirrusVGAState *s = opaque;
2075 unsigned bank_index;
2076 unsigned bank_offset;
2077 unsigned mode;
2078
2079 if ((s->sr[0x07] & 0x01) == 0) {
2080 vga_mem_writeb(s, addr, mem_value);
2081 return;
2082 }
2083
2084 addr &= 0x1ffff;
2085
2086 if (addr < 0x10000) {
2087 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2088 /* bitblt */
2089 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2090 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2091 cirrus_bitblt_cputovideo_next(s);
2092 }
2093 } else {
2094 /* video memory */
2095 bank_index = addr >> 15;
2096 bank_offset = addr & 0x7fff;
2097 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2098 bank_offset += s->cirrus_bank_base[bank_index];
2099 if ((s->gr[0x0B] & 0x14) == 0x14) {
2100 bank_offset <<= 4;
2101 } else if (s->gr[0x0B] & 0x02) {
2102 bank_offset <<= 3;
2103 }
2104 bank_offset &= s->cirrus_addr_mask;
2105 mode = s->gr[0x05] & 0x7;
2106 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2107 *(s->vram_ptr + bank_offset) = mem_value;
2108 cpu_physical_memory_set_dirty(s->vram_offset +
2109 bank_offset);
2110 } else {
2111 if ((s->gr[0x0B] & 0x14) != 0x14) {
2112 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2113 bank_offset,
2114 mem_value);
2115 } else {
2116 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2117 bank_offset,
2118 mem_value);
2119 }
2120 }
2121 }
2122 }
2123 } else if (addr >= 0x18000 && addr < 0x18100) {
2124 /* memory-mapped I/O */
2125 if ((s->sr[0x17] & 0x44) == 0x04) {
2126 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2127 }
2128 } else {
2129 #ifdef DEBUG_CIRRUS
2130 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2131 #endif
2132 }
2133 }
2134
2135 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2136 {
2137 #ifdef TARGET_WORDS_BIGENDIAN
2138 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2139 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2140 #else
2141 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2142 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2143 #endif
2144 }
2145
2146 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2147 {
2148 #ifdef TARGET_WORDS_BIGENDIAN
2149 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2150 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2151 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2153 #else
2154 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2155 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2156 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2157 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2158 #endif
2159 }
2160
2161 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2162 cirrus_vga_mem_readb,
2163 cirrus_vga_mem_readw,
2164 cirrus_vga_mem_readl,
2165 };
2166
2167 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2168 cirrus_vga_mem_writeb,
2169 cirrus_vga_mem_writew,
2170 cirrus_vga_mem_writel,
2171 };
2172
2173 /***************************************
2174 *
2175 * hardware cursor
2176 *
2177 ***************************************/
2178
2179 static inline void invalidate_cursor1(CirrusVGAState *s)
2180 {
2181 if (s->last_hw_cursor_size) {
2182 vga_invalidate_scanlines((VGAState *)s,
2183 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2184 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2185 }
2186 }
2187
2188 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2189 {
2190 const uint8_t *src;
2191 uint32_t content;
2192 int y, y_min, y_max;
2193
2194 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2195 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2196 src += (s->sr[0x13] & 0x3c) * 256;
2197 y_min = 64;
2198 y_max = -1;
2199 for(y = 0; y < 64; y++) {
2200 content = ((uint32_t *)src)[0] |
2201 ((uint32_t *)src)[1] |
2202 ((uint32_t *)src)[2] |
2203 ((uint32_t *)src)[3];
2204 if (content) {
2205 if (y < y_min)
2206 y_min = y;
2207 if (y > y_max)
2208 y_max = y;
2209 }
2210 src += 16;
2211 }
2212 } else {
2213 src += (s->sr[0x13] & 0x3f) * 256;
2214 y_min = 32;
2215 y_max = -1;
2216 for(y = 0; y < 32; y++) {
2217 content = ((uint32_t *)src)[0] |
2218 ((uint32_t *)(src + 128))[0];
2219 if (content) {
2220 if (y < y_min)
2221 y_min = y;
2222 if (y > y_max)
2223 y_max = y;
2224 }
2225 src += 4;
2226 }
2227 }
2228 if (y_min > y_max) {
2229 s->last_hw_cursor_y_start = 0;
2230 s->last_hw_cursor_y_end = 0;
2231 } else {
2232 s->last_hw_cursor_y_start = y_min;
2233 s->last_hw_cursor_y_end = y_max + 1;
2234 }
2235 }
2236
2237 /* NOTE: we do not currently handle the cursor bitmap change, so we
2238 update the cursor only if it moves. */
2239 static void cirrus_cursor_invalidate(VGAState *s1)
2240 {
2241 CirrusVGAState *s = (CirrusVGAState *)s1;
2242 int size;
2243
2244 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2245 size = 0;
2246 } else {
2247 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2248 size = 64;
2249 else
2250 size = 32;
2251 }
2252 /* invalidate last cursor and new cursor if any change */
2253 if (s->last_hw_cursor_size != size ||
2254 s->last_hw_cursor_x != s->hw_cursor_x ||
2255 s->last_hw_cursor_y != s->hw_cursor_y) {
2256
2257 invalidate_cursor1(s);
2258
2259 s->last_hw_cursor_size = size;
2260 s->last_hw_cursor_x = s->hw_cursor_x;
2261 s->last_hw_cursor_y = s->hw_cursor_y;
2262 /* compute the real cursor min and max y */
2263 cirrus_cursor_compute_yrange(s);
2264 invalidate_cursor1(s);
2265 }
2266 }
2267
2268 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2269 {
2270 CirrusVGAState *s = (CirrusVGAState *)s1;
2271 int w, h, bpp, x1, x2, poffset;
2272 unsigned int color0, color1;
2273 const uint8_t *palette, *src;
2274 uint32_t content;
2275
2276 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2277 return;
2278 /* fast test to see if the cursor intersects with the scan line */
2279 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2280 h = 64;
2281 } else {
2282 h = 32;
2283 }
2284 if (scr_y < s->hw_cursor_y ||
2285 scr_y >= (s->hw_cursor_y + h))
2286 return;
2287
2288 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2289 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2290 src += (s->sr[0x13] & 0x3c) * 256;
2291 src += (scr_y - s->hw_cursor_y) * 16;
2292 poffset = 8;
2293 content = ((uint32_t *)src)[0] |
2294 ((uint32_t *)src)[1] |
2295 ((uint32_t *)src)[2] |
2296 ((uint32_t *)src)[3];
2297 } else {
2298 src += (s->sr[0x13] & 0x3f) * 256;
2299 src += (scr_y - s->hw_cursor_y) * 4;
2300 poffset = 128;
2301 content = ((uint32_t *)src)[0] |
2302 ((uint32_t *)(src + 128))[0];
2303 }
2304 /* if nothing to draw, no need to continue */
2305 if (!content)
2306 return;
2307 w = h;
2308
2309 x1 = s->hw_cursor_x;
2310 if (x1 >= s->last_scr_width)
2311 return;
2312 x2 = s->hw_cursor_x + w;
2313 if (x2 > s->last_scr_width)
2314 x2 = s->last_scr_width;
2315 w = x2 - x1;
2316 palette = s->cirrus_hidden_palette;
2317 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2318 c6_to_8(palette[0x0 * 3 + 1]),
2319 c6_to_8(palette[0x0 * 3 + 2]));
2320 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2321 c6_to_8(palette[0xf * 3 + 1]),
2322 c6_to_8(palette[0xf * 3 + 2]));
2323 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2324 d1 += x1 * bpp;
2325 switch(ds_get_bits_per_pixel(s->ds)) {
2326 default:
2327 break;
2328 case 8:
2329 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2330 break;
2331 case 15:
2332 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2333 break;
2334 case 16:
2335 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2336 break;
2337 case 32:
2338 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2339 break;
2340 }
2341 }
2342
2343 /***************************************
2344 *
2345 * LFB memory access
2346 *
2347 ***************************************/
2348
2349 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2350 {
2351 CirrusVGAState *s = (CirrusVGAState *) opaque;
2352 uint32_t ret;
2353
2354 addr &= s->cirrus_addr_mask;
2355
2356 if (((s->sr[0x17] & 0x44) == 0x44) &&
2357 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2358 /* memory-mapped I/O */
2359 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2360 } else if (0) {
2361 /* XXX handle bitblt */
2362 ret = 0xff;
2363 } else {
2364 /* video memory */
2365 if ((s->gr[0x0B] & 0x14) == 0x14) {
2366 addr <<= 4;
2367 } else if (s->gr[0x0B] & 0x02) {
2368 addr <<= 3;
2369 }
2370 addr &= s->cirrus_addr_mask;
2371 ret = *(s->vram_ptr + addr);
2372 }
2373
2374 return ret;
2375 }
2376
2377 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2378 {
2379 uint32_t v;
2380 #ifdef TARGET_WORDS_BIGENDIAN
2381 v = cirrus_linear_readb(opaque, addr) << 8;
2382 v |= cirrus_linear_readb(opaque, addr + 1);
2383 #else
2384 v = cirrus_linear_readb(opaque, addr);
2385 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2386 #endif
2387 return v;
2388 }
2389
2390 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2391 {
2392 uint32_t v;
2393 #ifdef TARGET_WORDS_BIGENDIAN
2394 v = cirrus_linear_readb(opaque, addr) << 24;
2395 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2396 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2397 v |= cirrus_linear_readb(opaque, addr + 3);
2398 #else
2399 v = cirrus_linear_readb(opaque, addr);
2400 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2401 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2402 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2403 #endif
2404 return v;
2405 }
2406
2407 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2408 uint32_t val)
2409 {
2410 CirrusVGAState *s = (CirrusVGAState *) opaque;
2411 unsigned mode;
2412
2413 addr &= s->cirrus_addr_mask;
2414
2415 if (((s->sr[0x17] & 0x44) == 0x44) &&
2416 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2417 /* memory-mapped I/O */
2418 cirrus_mmio_blt_write(s, addr & 0xff, val);
2419 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2420 /* bitblt */
2421 *s->cirrus_srcptr++ = (uint8_t) val;
2422 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2423 cirrus_bitblt_cputovideo_next(s);
2424 }
2425 } else {
2426 /* video memory */
2427 if ((s->gr[0x0B] & 0x14) == 0x14) {
2428 addr <<= 4;
2429 } else if (s->gr[0x0B] & 0x02) {
2430 addr <<= 3;
2431 }
2432 addr &= s->cirrus_addr_mask;
2433
2434 mode = s->gr[0x05] & 0x7;
2435 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2436 *(s->vram_ptr + addr) = (uint8_t) val;
2437 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2438 } else {
2439 if ((s->gr[0x0B] & 0x14) != 0x14) {
2440 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2441 } else {
2442 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2443 }
2444 }
2445 }
2446 }
2447
2448 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2449 uint32_t val)
2450 {
2451 #ifdef TARGET_WORDS_BIGENDIAN
2452 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2453 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2454 #else
2455 cirrus_linear_writeb(opaque, addr, val & 0xff);
2456 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2457 #endif
2458 }
2459
2460 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2461 uint32_t val)
2462 {
2463 #ifdef TARGET_WORDS_BIGENDIAN
2464 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2465 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2467 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2468 #else
2469 cirrus_linear_writeb(opaque, addr, val & 0xff);
2470 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2471 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2472 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2473 #endif
2474 }
2475
2476
2477 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2478 cirrus_linear_readb,
2479 cirrus_linear_readw,
2480 cirrus_linear_readl,
2481 };
2482
2483 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2484 cirrus_linear_writeb,
2485 cirrus_linear_writew,
2486 cirrus_linear_writel,
2487 };
2488
2489 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2490 uint32_t val)
2491 {
2492 CirrusVGAState *s = (CirrusVGAState *) opaque;
2493
2494 addr &= s->cirrus_addr_mask;
2495 *(s->vram_ptr + addr) = val;
2496 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2497 }
2498
2499 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2500 uint32_t val)
2501 {
2502 CirrusVGAState *s = (CirrusVGAState *) opaque;
2503
2504 addr &= s->cirrus_addr_mask;
2505 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2506 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2507 }
2508
2509 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2510 uint32_t val)
2511 {
2512 CirrusVGAState *s = (CirrusVGAState *) opaque;
2513
2514 addr &= s->cirrus_addr_mask;
2515 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2516 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2517 }
2518
2519 /***************************************
2520 *
2521 * system to screen memory access
2522 *
2523 ***************************************/
2524
2525
2526 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2527 {
2528 uint32_t ret;
2529
2530 /* XXX handle bitblt */
2531 ret = 0xff;
2532 return ret;
2533 }
2534
2535 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2536 {
2537 uint32_t v;
2538 #ifdef TARGET_WORDS_BIGENDIAN
2539 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2540 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2541 #else
2542 v = cirrus_linear_bitblt_readb(opaque, addr);
2543 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2544 #endif
2545 return v;
2546 }
2547
2548 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2549 {
2550 uint32_t v;
2551 #ifdef TARGET_WORDS_BIGENDIAN
2552 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2553 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2554 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2555 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2556 #else
2557 v = cirrus_linear_bitblt_readb(opaque, addr);
2558 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2559 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2560 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2561 #endif
2562 return v;
2563 }
2564
2565 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2566 uint32_t val)
2567 {
2568 CirrusVGAState *s = (CirrusVGAState *) opaque;
2569
2570 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2571 /* bitblt */
2572 *s->cirrus_srcptr++ = (uint8_t) val;
2573 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2574 cirrus_bitblt_cputovideo_next(s);
2575 }
2576 }
2577 }
2578
2579 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2580 uint32_t val)
2581 {
2582 #ifdef TARGET_WORDS_BIGENDIAN
2583 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2584 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2585 #else
2586 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2587 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2588 #endif
2589 }
2590
2591 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2592 uint32_t val)
2593 {
2594 #ifdef TARGET_WORDS_BIGENDIAN
2595 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2596 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2598 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2599 #else
2600 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2601 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2602 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2603 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2604 #endif
2605 }
2606
2607
2608 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2609 cirrus_linear_bitblt_readb,
2610 cirrus_linear_bitblt_readw,
2611 cirrus_linear_bitblt_readl,
2612 };
2613
2614 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2615 cirrus_linear_bitblt_writeb,
2616 cirrus_linear_bitblt_writew,
2617 cirrus_linear_bitblt_writel,
2618 };
2619
2620 static void map_linear_vram(CirrusVGAState *s)
2621 {
2622 vga_dirty_log_stop((VGAState *)s);
2623
2624 vga_dirty_log_stop((VGAState *)s);
2625 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2626 s->map_addr = s->lfb_addr;
2627 s->map_end = s->lfb_end;
2628 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2629 }
2630
2631 if (!s->map_addr)
2632 return;
2633
2634 #ifndef TARGET_IA64
2635 s->lfb_vram_mapped = 0;
2636
2637 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2638 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_UNASSIGNED);
2639 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2640 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_UNASSIGNED);
2641 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2642 && !((s->sr[0x07] & 0x01) == 0)
2643 && !((s->gr[0x0B] & 0x14) == 0x14)
2644 && !(s->gr[0x0B] & 0x02)) {
2645
2646 vga_dirty_log_stop((VGAState *)s);
2647 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2648 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2649 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2650 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2651
2652 s->lfb_vram_mapped = 1;
2653 }
2654 else {
2655 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2656 s->vga_io_memory);
2657 }
2658 #endif
2659
2660 vga_dirty_log_start((VGAState *)s);
2661 }
2662
2663 static void unmap_linear_vram(CirrusVGAState *s)
2664 {
2665 vga_dirty_log_stop((VGAState *)s);
2666 if (s->map_addr && s->lfb_addr && s->lfb_end)
2667 s->map_addr = s->map_end = 0;
2668
2669 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2670 s->vga_io_memory);
2671
2672 vga_dirty_log_start((VGAState *)s);
2673 }
2674
2675 /* Compute the memory access functions */
2676 static void cirrus_update_memory_access(CirrusVGAState *s)
2677 {
2678 unsigned mode;
2679
2680 if ((s->sr[0x17] & 0x44) == 0x44) {
2681 goto generic_io;
2682 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2683 goto generic_io;
2684 } else {
2685 if ((s->gr[0x0B] & 0x14) == 0x14) {
2686 goto generic_io;
2687 } else if (s->gr[0x0B] & 0x02) {
2688 goto generic_io;
2689 }
2690
2691 mode = s->gr[0x05] & 0x7;
2692 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2693 map_linear_vram(s);
2694 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2695 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2696 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2697 } else {
2698 generic_io:
2699 unmap_linear_vram(s);
2700 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2701 s->cirrus_linear_write[1] = cirrus_linear_writew;
2702 s->cirrus_linear_write[2] = cirrus_linear_writel;
2703 }
2704 }
2705 }
2706
2707
2708 /* I/O ports */
2709
2710 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2711 {
2712 CirrusVGAState *s = opaque;
2713 int val, index;
2714
2715 /* check port range access depending on color/monochrome mode */
2716 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2717 || (addr >= 0x3d0 && addr <= 0x3df
2718 && !(s->msr & MSR_COLOR_EMULATION))) {
2719 val = 0xff;
2720 } else {
2721 switch (addr) {
2722 case 0x3c0:
2723 if (s->ar_flip_flop == 0) {
2724 val = s->ar_index;
2725 } else {
2726 val = 0;
2727 }
2728 break;
2729 case 0x3c1:
2730 index = s->ar_index & 0x1f;
2731 if (index < 21)
2732 val = s->ar[index];
2733 else
2734 val = 0;
2735 break;
2736 case 0x3c2:
2737 val = s->st00;
2738 break;
2739 case 0x3c4:
2740 val = s->sr_index;
2741 break;
2742 case 0x3c5:
2743 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2744 break;
2745 val = s->sr[s->sr_index];
2746 #ifdef DEBUG_VGA_REG
2747 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2748 #endif
2749 break;
2750 case 0x3c6:
2751 cirrus_read_hidden_dac(s, &val);
2752 break;
2753 case 0x3c7:
2754 val = s->dac_state;
2755 break;
2756 case 0x3c8:
2757 val = s->dac_write_index;
2758 s->cirrus_hidden_dac_lockindex = 0;
2759 break;
2760 case 0x3c9:
2761 if (cirrus_hook_read_palette(s, &val))
2762 break;
2763 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2764 if (++s->dac_sub_index == 3) {
2765 s->dac_sub_index = 0;
2766 s->dac_read_index++;
2767 }
2768 break;
2769 case 0x3ca:
2770 val = s->fcr;
2771 break;
2772 case 0x3cc:
2773 val = s->msr;
2774 break;
2775 case 0x3ce:
2776 val = s->gr_index;
2777 break;
2778 case 0x3cf:
2779 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2780 break;
2781 val = s->gr[s->gr_index];
2782 #ifdef DEBUG_VGA_REG
2783 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2784 #endif
2785 break;
2786 case 0x3b4:
2787 case 0x3d4:
2788 val = s->cr_index;
2789 break;
2790 case 0x3b5:
2791 case 0x3d5:
2792 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2793 break;
2794 val = s->cr[s->cr_index];
2795 #ifdef DEBUG_VGA_REG
2796 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2797 #endif
2798 break;
2799 case 0x3ba:
2800 case 0x3da:
2801 /* just toggle to fool polling */
2802 val = s->st01 = s->retrace((VGAState *) s);
2803 s->ar_flip_flop = 0;
2804 break;
2805 default:
2806 val = 0x00;
2807 break;
2808 }
2809 }
2810 #if defined(DEBUG_VGA)
2811 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2812 #endif
2813 return val;
2814 }
2815
2816 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2817 {
2818 CirrusVGAState *s = opaque;
2819 int index;
2820
2821 /* check port range access depending on color/monochrome mode */
2822 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2823 || (addr >= 0x3d0 && addr <= 0x3df
2824 && !(s->msr & MSR_COLOR_EMULATION)))
2825 return;
2826
2827 #ifdef DEBUG_VGA
2828 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2829 #endif
2830
2831 switch (addr) {
2832 case 0x3c0:
2833 if (s->ar_flip_flop == 0) {
2834 val &= 0x3f;
2835 s->ar_index = val;
2836 } else {
2837 index = s->ar_index & 0x1f;
2838 switch (index) {
2839 case 0x00 ... 0x0f:
2840 s->ar[index] = val & 0x3f;
2841 break;
2842 case 0x10:
2843 s->ar[index] = val & ~0x10;
2844 break;
2845 case 0x11:
2846 s->ar[index] = val;
2847 break;
2848 case 0x12:
2849 s->ar[index] = val & ~0xc0;
2850 break;
2851 case 0x13:
2852 s->ar[index] = val & ~0xf0;
2853 break;
2854 case 0x14:
2855 s->ar[index] = val & ~0xf0;
2856 break;
2857 default:
2858 break;
2859 }
2860 }
2861 s->ar_flip_flop ^= 1;
2862 break;
2863 case 0x3c2:
2864 s->msr = val & ~0x10;
2865 s->update_retrace_info((VGAState *) s);
2866 break;
2867 case 0x3c4:
2868 s->sr_index = val;
2869 break;
2870 case 0x3c5:
2871 if (cirrus_hook_write_sr(s, s->sr_index, val))
2872 break;
2873 #ifdef DEBUG_VGA_REG
2874 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2875 #endif
2876 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2877 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2878 break;
2879 case 0x3c6:
2880 cirrus_write_hidden_dac(s, val);
2881 break;
2882 case 0x3c7:
2883 s->dac_read_index = val;
2884 s->dac_sub_index = 0;
2885 s->dac_state = 3;
2886 break;
2887 case 0x3c8:
2888 s->dac_write_index = val;
2889 s->dac_sub_index = 0;
2890 s->dac_state = 0;
2891 break;
2892 case 0x3c9:
2893 if (cirrus_hook_write_palette(s, val))
2894 break;
2895 s->dac_cache[s->dac_sub_index] = val;
2896 if (++s->dac_sub_index == 3) {
2897 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2898 s->dac_sub_index = 0;
2899 s->dac_write_index++;
2900 }
2901 break;
2902 case 0x3ce:
2903 s->gr_index = val;
2904 break;
2905 case 0x3cf:
2906 if (cirrus_hook_write_gr(s, s->gr_index, val))
2907 break;
2908 #ifdef DEBUG_VGA_REG
2909 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2910 #endif
2911 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2912 break;
2913 case 0x3b4:
2914 case 0x3d4:
2915 s->cr_index = val;
2916 break;
2917 case 0x3b5:
2918 case 0x3d5:
2919 if (cirrus_hook_write_cr(s, s->cr_index, val))
2920 break;
2921 #ifdef DEBUG_VGA_REG
2922 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2923 #endif
2924 /* handle CR0-7 protection */
2925 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2926 /* can always write bit 4 of CR7 */
2927 if (s->cr_index == 7)
2928 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2929 return;
2930 }
2931 switch (s->cr_index) {
2932 case 0x01: /* horizontal display end */
2933 case 0x07:
2934 case 0x09:
2935 case 0x0c:
2936 case 0x0d:
2937 case 0x12: /* vertical display end */
2938 s->cr[s->cr_index] = val;
2939 break;
2940
2941 default:
2942 s->cr[s->cr_index] = val;
2943 break;
2944 }
2945
2946 switch(s->cr_index) {
2947 case 0x00:
2948 case 0x04:
2949 case 0x05:
2950 case 0x06:
2951 case 0x07:
2952 case 0x11:
2953 case 0x17:
2954 s->update_retrace_info((VGAState *) s);
2955 break;
2956 }
2957 break;
2958 case 0x3ba:
2959 case 0x3da:
2960 s->fcr = val & 0x10;
2961 break;
2962 }
2963 }
2964
2965 /***************************************
2966 *
2967 * memory-mapped I/O access
2968 *
2969 ***************************************/
2970
2971 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2972 {
2973 CirrusVGAState *s = (CirrusVGAState *) opaque;
2974
2975 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2976
2977 if (addr >= 0x100) {
2978 return cirrus_mmio_blt_read(s, addr - 0x100);
2979 } else {
2980 return vga_ioport_read(s, addr + 0x3c0);
2981 }
2982 }
2983
2984 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2985 {
2986 uint32_t v;
2987 #ifdef TARGET_WORDS_BIGENDIAN
2988 v = cirrus_mmio_readb(opaque, addr) << 8;
2989 v |= cirrus_mmio_readb(opaque, addr + 1);
2990 #else
2991 v = cirrus_mmio_readb(opaque, addr);
2992 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2993 #endif
2994 return v;
2995 }
2996
2997 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2998 {
2999 uint32_t v;
3000 #ifdef TARGET_WORDS_BIGENDIAN
3001 v = cirrus_mmio_readb(opaque, addr) << 24;
3002 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3003 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3004 v |= cirrus_mmio_readb(opaque, addr + 3);
3005 #else
3006 v = cirrus_mmio_readb(opaque, addr);
3007 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3008 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3009 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3010 #endif
3011 return v;
3012 }
3013
3014 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3015 uint32_t val)
3016 {
3017 CirrusVGAState *s = (CirrusVGAState *) opaque;
3018
3019 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3020
3021 if (addr >= 0x100) {
3022 cirrus_mmio_blt_write(s, addr - 0x100, val);
3023 } else {
3024 vga_ioport_write(s, addr + 0x3c0, val);
3025 }
3026 }
3027
3028 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3029 uint32_t val)
3030 {
3031 #ifdef TARGET_WORDS_BIGENDIAN
3032 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3033 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3034 #else
3035 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3036 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3037 #endif
3038 }
3039
3040 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3041 uint32_t val)
3042 {
3043 #ifdef TARGET_WORDS_BIGENDIAN
3044 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3045 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3046 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3047 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3048 #else
3049 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3050 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3051 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3052 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3053 #endif
3054 }
3055
3056
3057 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3058 cirrus_mmio_readb,
3059 cirrus_mmio_readw,
3060 cirrus_mmio_readl,
3061 };
3062
3063 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3064 cirrus_mmio_writeb,
3065 cirrus_mmio_writew,
3066 cirrus_mmio_writel,
3067 };
3068
3069 /* load/save state */
3070
3071 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3072 {
3073 CirrusVGAState *s = opaque;
3074
3075 if (s->pci_dev)
3076 pci_device_save(s->pci_dev, f);
3077
3078 qemu_put_be32s(f, &s->latch);
3079 qemu_put_8s(f, &s->sr_index);
3080 qemu_put_buffer(f, s->sr, 256);
3081 qemu_put_8s(f, &s->gr_index);
3082 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3083 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3084 qemu_put_buffer(f, s->gr + 2, 254);
3085 qemu_put_8s(f, &s->ar_index);
3086 qemu_put_buffer(f, s->ar, 21);
3087 qemu_put_be32(f, s->ar_flip_flop);
3088 qemu_put_8s(f, &s->cr_index);
3089 qemu_put_buffer(f, s->cr, 256);
3090 qemu_put_8s(f, &s->msr);
3091 qemu_put_8s(f, &s->fcr);
3092 qemu_put_8s(f, &s->st00);
3093 qemu_put_8s(f, &s->st01);
3094
3095 qemu_put_8s(f, &s->dac_state);
3096 qemu_put_8s(f, &s->dac_sub_index);
3097 qemu_put_8s(f, &s->dac_read_index);
3098 qemu_put_8s(f, &s->dac_write_index);
3099 qemu_put_buffer(f, s->dac_cache, 3);
3100 qemu_put_buffer(f, s->palette, 768);
3101
3102 qemu_put_be32(f, s->bank_offset);
3103
3104 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3105 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3106
3107 qemu_put_be32s(f, &s->hw_cursor_x);
3108 qemu_put_be32s(f, &s->hw_cursor_y);
3109 /* XXX: we do not save the bitblt state - we assume we do not save
3110 the state when the blitter is active */
3111 }
3112
3113 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3114 {
3115 CirrusVGAState *s = opaque;
3116 int ret;
3117
3118 if (version_id > 2)
3119 return -EINVAL;
3120
3121 if (s->pci_dev && version_id >= 2) {
3122 ret = pci_device_load(s->pci_dev, f);
3123 if (ret < 0)
3124 return ret;
3125 }
3126
3127 qemu_get_be32s(f, &s->latch);
3128 qemu_get_8s(f, &s->sr_index);
3129 qemu_get_buffer(f, s->sr, 256);
3130 qemu_get_8s(f, &s->gr_index);
3131 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3132 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3133 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3134 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3135 qemu_get_buffer(f, s->gr + 2, 254);
3136 qemu_get_8s(f, &s->ar_index);
3137 qemu_get_buffer(f, s->ar, 21);
3138 s->ar_flip_flop=qemu_get_be32(f);
3139 qemu_get_8s(f, &s->cr_index);
3140 qemu_get_buffer(f, s->cr, 256);
3141 qemu_get_8s(f, &s->msr);
3142 qemu_get_8s(f, &s->fcr);
3143 qemu_get_8s(f, &s->st00);
3144 qemu_get_8s(f, &s->st01);
3145
3146 qemu_get_8s(f, &s->dac_state);
3147 qemu_get_8s(f, &s->dac_sub_index);
3148 qemu_get_8s(f, &s->dac_read_index);
3149 qemu_get_8s(f, &s->dac_write_index);
3150 qemu_get_buffer(f, s->dac_cache, 3);
3151 qemu_get_buffer(f, s->palette, 768);
3152
3153 s->bank_offset=qemu_get_be32(f);
3154
3155 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3156 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3157
3158 qemu_get_be32s(f, &s->hw_cursor_x);
3159 qemu_get_be32s(f, &s->hw_cursor_y);
3160
3161 cirrus_update_memory_access(s);
3162 /* force refresh */
3163 s->graphic_mode = -1;
3164 cirrus_update_bank_ptr(s, 0);
3165 cirrus_update_bank_ptr(s, 1);
3166 return 0;
3167 }
3168
3169 /***************************************
3170 *
3171 * initialize
3172 *
3173 ***************************************/
3174
3175 static void cirrus_reset(void *opaque)
3176 {
3177 CirrusVGAState *s = opaque;
3178
3179 vga_reset(s);
3180 unmap_linear_vram(s);
3181 s->sr[0x06] = 0x0f;
3182 if (s->device_id == CIRRUS_ID_CLGD5446) {
3183 /* 4MB 64 bit memory config, always PCI */
3184 s->sr[0x1F] = 0x2d; // MemClock
3185 s->gr[0x18] = 0x0f; // fastest memory configuration
3186 s->sr[0x0f] = 0x98;
3187 s->sr[0x17] = 0x20;
3188 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3189 } else {
3190 s->sr[0x1F] = 0x22; // MemClock
3191 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3192 s->sr[0x17] = s->bustype;
3193 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3194 }
3195 s->cr[0x27] = s->device_id;
3196
3197 /* Win2K seems to assume that the pattern buffer is at 0xff
3198 initially ! */
3199 memset(s->vram_ptr, 0xff, s->real_vram_size);
3200
3201 s->cirrus_hidden_dac_lockindex = 5;
3202 s->cirrus_hidden_dac_data = 0;
3203 }
3204
3205 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3206 {
3207 int i;
3208 static int inited;
3209
3210 if (!inited) {
3211 inited = 1;
3212 for(i = 0;i < 256; i++)
3213 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3214 rop_to_index[CIRRUS_ROP_0] = 0;
3215 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3216 rop_to_index[CIRRUS_ROP_NOP] = 2;
3217 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3218 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3219 rop_to_index[CIRRUS_ROP_SRC] = 5;
3220 rop_to_index[CIRRUS_ROP_1] = 6;
3221 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3222 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3223 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3224 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3225 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3226 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3227 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3228 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3229 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3230 s->device_id = device_id;
3231 if (is_pci)
3232 s->bustype = CIRRUS_BUSTYPE_PCI;
3233 else
3234 s->bustype = CIRRUS_BUSTYPE_ISA;
3235 }
3236
3237 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3238
3239 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3240 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3241 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3242 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3243
3244 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3245
3246 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3247 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3248 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3249 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3250
3251 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3252 cirrus_vga_mem_write, s);
3253 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3254 s->vga_io_memory);
3255 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3256
3257 /* I/O handler for LFB */
3258 s->cirrus_linear_io_addr =
3259 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s);
3260 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3261
3262 /* I/O handler for LFB */
3263 s->cirrus_linear_bitblt_io_addr =
3264 cpu_register_io_memory(0, cirrus_linear_bitblt_read,
3265 cirrus_linear_bitblt_write, s);
3266
3267 /* I/O handler for memory-mapped I/O */
3268 s->cirrus_mmio_io_addr =
3269 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3270
3271 s->real_vram_size =
3272 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3273
3274 /* XXX: s->vram_size must be a power of two */
3275 s->cirrus_addr_mask = s->real_vram_size - 1;
3276 s->linear_mmio_mask = s->real_vram_size - 256;
3277
3278 s->get_bpp = cirrus_get_bpp;
3279 s->get_offsets = cirrus_get_offsets;
3280 s->get_resolution = cirrus_get_resolution;
3281 s->cursor_invalidate = cirrus_cursor_invalidate;
3282 s->cursor_draw_line = cirrus_cursor_draw_line;
3283
3284 qemu_register_reset(cirrus_reset, s);
3285 cirrus_reset(s);
3286 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3287 }
3288
3289 /***************************************
3290 *
3291 * ISA bus support
3292 *
3293 ***************************************/
3294
3295 void isa_cirrus_vga_init(uint8_t *vga_ram_base,
3296 ram_addr_t vga_ram_offset, int vga_ram_size)
3297 {
3298 CirrusVGAState *s;
3299
3300 s = qemu_mallocz(sizeof(CirrusVGAState));
3301
3302 vga_common_init((VGAState *)s,
3303 vga_ram_base, vga_ram_offset, vga_ram_size);
3304 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3305 s->ds = graphic_console_init(s->update, s->invalidate,
3306 s->screen_dump, s->text_update, s);
3307 /* XXX ISA-LFB support */
3308 }
3309
3310 /***************************************
3311 *
3312 * PCI bus support
3313 *
3314 ***************************************/
3315
3316 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3317 uint32_t addr, uint32_t size, int type)
3318 {
3319 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3320
3321 vga_dirty_log_stop((VGAState *)s);
3322
3323 /* XXX: add byte swapping apertures */
3324 cpu_register_physical_memory(addr, s->vram_size,
3325 s->cirrus_linear_io_addr);
3326 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3327 s->cirrus_linear_bitblt_io_addr);
3328
3329 s->map_addr = s->map_end = 0;
3330 s->lfb_addr = addr & TARGET_PAGE_MASK;
3331 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3332 /* account for overflow */
3333 if (s->lfb_end < addr + VGA_RAM_SIZE)
3334 s->lfb_end = addr + VGA_RAM_SIZE;
3335
3336 vga_dirty_log_start((VGAState *)s);
3337 }
3338
3339 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3340 uint32_t addr, uint32_t size, int type)
3341 {
3342 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3343
3344 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3345 s->cirrus_mmio_io_addr);
3346 }
3347
3348 static void pci_cirrus_write_config(PCIDevice *d,
3349 uint32_t address, uint32_t val, int len)
3350 {
3351 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3352 CirrusVGAState *s = &pvs->cirrus_vga;
3353
3354 vga_dirty_log_stop((VGAState *)s);
3355
3356 pci_default_write_config(d, address, val, len);
3357 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
3358 s->map_addr = 0;
3359 cirrus_update_memory_access(s);
3360
3361 vga_dirty_log_start((VGAState *)s);
3362 }
3363
3364 void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
3365 ram_addr_t vga_ram_offset, int vga_ram_size)
3366 {
3367 PCICirrusVGAState *d;
3368 uint8_t *pci_conf;
3369 CirrusVGAState *s;
3370 int device_id;
3371
3372 device_id = CIRRUS_ID_CLGD5446;
3373
3374 /* setup PCI configuration registers */
3375 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3376 sizeof(PCICirrusVGAState),
3377 -1, NULL, pci_cirrus_write_config);
3378 pci_conf = d->dev.config;
3379 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3380 pci_config_set_device_id(pci_conf, device_id);
3381 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3382 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3383 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3384
3385 /* setup VGA */
3386 s = &d->cirrus_vga;
3387 vga_common_init((VGAState *)s,
3388 vga_ram_base, vga_ram_offset, vga_ram_size);
3389 cirrus_init_common(s, device_id, 1);
3390
3391 s->ds = graphic_console_init(s->update, s->invalidate,
3392 s->screen_dump, s->text_update, s);
3393
3394 s->pci_dev = (PCIDevice *)d;
3395
3396 /* setup memory space */
3397 /* memory #0 LFB */
3398 /* memory #1 memory-mapped I/O */
3399 /* XXX: s->vram_size must be a power of two */
3400 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3401 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3402 if (device_id == CIRRUS_ID_CLGD5446) {
3403 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3404 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3405 }
3406 /* XXX: ROM BIOS */
3407 }
Patches shipped by Fedora