hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 #include "qemu-kvm.h"
  31
  32 /* debug PIC */
  33 //#define DEBUG_PIC
  34
  35 //#define DEBUG_IRQ_LATENCY
  36 //#define DEBUG_IRQ_COUNT
  37
  38 typedef struct PicState {
  39     uint8_t last_irr; /* edge detection */
  40     uint8_t irr; /* interrupt request register */
  41     uint8_t imr; /* interrupt mask register */
  42     uint8_t isr; /* interrupt service register */
  43     uint8_t priority_add; /* highest irq priority */
  44     uint8_t irq_base;
  45     uint8_t read_reg_select;
  46     uint8_t poll;
  47     uint8_t special_mask;
  48     uint8_t init_state;
  49     uint8_t auto_eoi;
  50     uint8_t rotate_on_auto_eoi;
  51     uint8_t special_fully_nested_mode;
  52     uint8_t init4; /* true if 4 byte init */
  53     uint8_t single_mode; /* true if slave pic is not initialized */
  54     uint8_t elcr; /* PIIX edge/trigger selection*/
  55     uint8_t elcr_mask;
  56     PicState2 *pics_state;
  57 } PicState;
  58
  59 struct PicState2 {
  60     /* 0 is master pic, 1 is slave pic */
  61     /* XXX: better separation between the two pics */
  62     PicState pics[2];
  63     qemu_irq parent_irq;
  64     void *irq_request_opaque;
  65     /* IOAPIC callback support */
  66     SetIRQFunc *alt_irq_func;
  67     void *alt_irq_opaque;
  68 };
  69
  70 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  71 static int irq_level[16];
  72 #endif
  73 #ifdef DEBUG_IRQ_COUNT
  74 static uint64_t irq_count[16];
  75 #endif
  76
  77 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  78 static inline void pic_set_irq1(PicState *s, int irq, int level)
  79 {
  80     int mask;
  81     mask = 1 << irq;
  82     if (s->elcr & mask) {
  83         /* level triggered */
  84         if (level) {
  85             s->irr |= mask;
  86             s->last_irr |= mask;
  87         } else {
  88             s->irr &= ~mask;
  89             s->last_irr &= ~mask;
  90         }
  91     } else {
  92         /* edge triggered */
  93         if (level) {
  94             if ((s->last_irr & mask) == 0)
  95                 s->irr |= mask;
  96             s->last_irr |= mask;
  97         } else {
  98             s->last_irr &= ~mask;
  99         }
 100     }
 101 }
 102
 103 /* return the highest priority found in mask (highest = smallest
 104    number). Return 8 if no irq */
 105 static inline int get_priority(PicState *s, int mask)
 106 {
 107     int priority;
 108     if (mask == 0)
 109         return 8;
 110     priority = 0;
 111     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 112         priority++;
 113     return priority;
 114 }
 115
 116 /* return the pic wanted interrupt. return -1 if none */
 117 static int pic_get_irq(PicState *s)
 118 {
 119     int mask, cur_priority, priority;
 120
 121     mask = s->irr & ~s->imr;
 122     priority = get_priority(s, mask);
 123     if (priority == 8)
 124         return -1;
 125     /* compute current priority. If special fully nested mode on the
 126        master, the IRQ coming from the slave is not taken into account
 127        for the priority computation. */
 128     mask = s->isr;
 129     if (s->special_mask)
 130         mask &= ~s->imr;
 131     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 132         mask &= ~(1 << 2);
 133     cur_priority = get_priority(s, mask);
 134     if (priority < cur_priority) {
 135         /* higher priority found: an irq should be generated */
 136         return (priority + s->priority_add) & 7;
 137     } else {
 138         return -1;
 139     }
 140 }
 141
 142 /* raise irq to CPU if necessary. must be called every time the active
 143    irq may change */
 144 /* XXX: should not export it, but it is needed for an APIC kludge */
 145 void pic_update_irq(PicState2 *s)
 146 {
 147     int irq2, irq;
 148
 149     /* first look at slave pic */
 150     irq2 = pic_get_irq(&s->pics[1]);
 151     if (irq2 >= 0) {
 152         /* if irq request by slave pic, signal master PIC */
 153         pic_set_irq1(&s->pics[0], 2, 1);
 154         pic_set_irq1(&s->pics[0], 2, 0);
 155     }
 156     /* look at requested irq */
 157     irq = pic_get_irq(&s->pics[0]);
 158     if (irq >= 0) {
 159 #if defined(DEBUG_PIC)
 160         {
 161             int i;
 162             for(i = 0; i < 2; i++) {
 163                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 164                        i, s->pics[i].imr, s->pics[i].irr,
 165                        s->pics[i].priority_add);
 166
 167             }
 168         }
 169         printf("pic: cpu_interrupt\n");
 170 #endif
 171         qemu_irq_raise(s->parent_irq);
 172     }
 173
 174 /* all targets should do this rather than acking the IRQ in the cpu */
 175 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
 176     else {
 177         qemu_irq_lower(s->parent_irq);
 178     }
 179 #endif
 180 }
 181
 182 #ifdef DEBUG_IRQ_LATENCY
 183 int64_t irq_time[16];
 184 #endif
 185
 186 static void i8259_set_irq(void *opaque, int irq, int level)
 187 {
 188     PicState2 *s = opaque;
 189 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 190     if (level != irq_level[irq]) {
 191 #if defined(DEBUG_PIC)
 192         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 193 #endif
 194         irq_level[irq] = level;
 195 #ifdef DEBUG_IRQ_COUNT
 196         if (level == 1)
 197             irq_count[irq]++;
 198 #endif
 199     }
 200 #endif
 201 #ifdef DEBUG_IRQ_LATENCY
 202     if (level) {
 203         irq_time[irq] = qemu_get_clock(vm_clock);
 204     }
 205 #endif
 206     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 207     /* used for IOAPIC irqs */
 208     if (s->alt_irq_func)
 209         s->alt_irq_func(s->alt_irq_opaque, irq, level);
 210     pic_update_irq(s);
 211 }
 212
 213 /* acknowledge interrupt 'irq' */
 214 static inline void pic_intack(PicState *s, int irq)
 215 {
 216     if (s->auto_eoi) {
 217         if (s->rotate_on_auto_eoi)
 218             s->priority_add = (irq + 1) & 7;
 219     } else {
 220         s->isr |= (1 << irq);
 221     }
 222
 223     /* We don't clear a level sensitive interrupt here */
 224     if (!(s->elcr & (1 << irq)))
 225         s->irr &= ~(1 << irq);
 226
 227 }
 228
 229 extern int time_drift_fix;
 230
 231 int pic_read_irq(PicState2 *s)
 232 {
 233     int irq, irq2, intno;
 234
 235     irq = pic_get_irq(&s->pics[0]);
 236     if (irq >= 0) {
 237
 238         pic_intack(&s->pics[0], irq);
 239 #ifndef TARGET_IA64
 240         if (time_drift_fix && irq == 0) {
 241             extern int64_t timer_acks, timer_ints_to_push;
 242             timer_acks++;
 243             if (timer_ints_to_push > 0) {
 244                 timer_ints_to_push--;
 245                 /* simulate an edge irq0, like the one generated by i8254 */
 246                 pic_set_irq1(&s->pics[0], 0, 0);
 247                 pic_set_irq1(&s->pics[0], 0, 1);
 248             }
 249         }
 250 #endif
 251         if (irq == 2) {
 252             irq2 = pic_get_irq(&s->pics[1]);
 253             if (irq2 >= 0) {
 254                 pic_intack(&s->pics[1], irq2);
 255             } else {
 256                 /* spurious IRQ on slave controller */
 257                 irq2 = 7;
 258             }
 259             intno = s->pics[1].irq_base + irq2;
 260             irq = irq2 + 8;
 261         } else {
 262             intno = s->pics[0].irq_base + irq;
 263         }
 264     } else {
 265         /* spurious IRQ on host controller */
 266         irq = 7;
 267         intno = s->pics[0].irq_base + irq;
 268     }
 269     pic_update_irq(s);
 270
 271 #ifdef DEBUG_IRQ_LATENCY
 272     printf("IRQ%d latency=%0.3fus\n",
 273            irq,
 274            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 275 #endif
 276 #if defined(DEBUG_PIC)
 277     printf("pic_interrupt: irq=%d\n", irq);
 278 #endif
 279     return intno;
 280 }
 281
 282 static void pic_reset(void *opaque)
 283 {
 284     PicState *s = opaque;
 285
 286     s->last_irr = 0;
 287     s->irr = 0;
 288     s->imr = 0;
 289     s->isr = 0;
 290     s->priority_add = 0;
 291     s->irq_base = 0;
 292     s->read_reg_select = 0;
 293     s->poll = 0;
 294     s->special_mask = 0;
 295     s->init_state = 0;
 296     s->auto_eoi = 0;
 297     s->rotate_on_auto_eoi = 0;
 298     s->special_fully_nested_mode = 0;
 299     s->init4 = 0;
 300     s->single_mode = 0;
 301     /* Note: ELCR is not reset */
 302 }
 303
 304 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 305 {
 306     PicState *s = opaque;
 307     int priority, cmd, irq;
 308
 309 #ifdef DEBUG_PIC
 310     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 311 #endif
 312     addr &= 1;
 313     if (addr == 0) {
 314         if (val & 0x10) {
 315             /* init */
 316             pic_reset(s);
 317             /* deassert a pending interrupt */
 318             qemu_irq_lower(s->pics_state->parent_irq);
 319             s->init_state = 1;
 320             s->init4 = val & 1;
 321             s->single_mode = val & 2;
 322             if (val & 0x08)
 323                 hw_error("level sensitive irq not supported");
 324         } else if (val & 0x08) {
 325             if (val & 0x04)
 326                 s->poll = 1;
 327             if (val & 0x02)
 328                 s->read_reg_select = val & 1;
 329             if (val & 0x40)
 330                 s->special_mask = (val >> 5) & 1;
 331         } else {
 332             cmd = val >> 5;
 333             switch(cmd) {
 334             case 0:
 335             case 4:
 336                 s->rotate_on_auto_eoi = cmd >> 2;
 337                 break;
 338             case 1: /* end of interrupt */
 339             case 5:
 340                 priority = get_priority(s, s->isr);
 341                 if (priority != 8) {
 342                     irq = (priority + s->priority_add) & 7;
 343                     s->isr &= ~(1 << irq);
 344                     if (cmd == 5)
 345                         s->priority_add = (irq + 1) & 7;
 346                     pic_update_irq(s->pics_state);
 347                 }
 348                 break;
 349             case 3:
 350                 irq = val & 7;
 351                 s->isr &= ~(1 << irq);
 352                 pic_update_irq(s->pics_state);
 353                 break;
 354             case 6:
 355                 s->priority_add = (val + 1) & 7;
 356                 pic_update_irq(s->pics_state);
 357                 break;
 358             case 7:
 359                 irq = val & 7;
 360                 s->isr &= ~(1 << irq);
 361                 s->priority_add = (irq + 1) & 7;
 362                 pic_update_irq(s->pics_state);
 363                 break;
 364             default:
 365                 /* no operation */
 366                 break;
 367             }
 368         }
 369     } else {
 370         switch(s->init_state) {
 371         case 0:
 372             /* normal mode */
 373             s->imr = val;
 374             pic_update_irq(s->pics_state);
 375             break;
 376         case 1:
 377             s->irq_base = val & 0xf8;
 378             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 379             break;
 380         case 2:
 381             if (s->init4) {
 382                 s->init_state = 3;
 383             } else {
 384                 s->init_state = 0;
 385             }
 386             break;
 387         case 3:
 388             s->special_fully_nested_mode = (val >> 4) & 1;
 389             s->auto_eoi = (val >> 1) & 1;
 390             s->init_state = 0;
 391             break;
 392         }
 393     }
 394 }
 395
 396 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 397 {
 398     int ret;
 399
 400     ret = pic_get_irq(s);
 401     if (ret >= 0) {
 402         if (addr1 >> 7) {
 403             s->pics_state->pics[0].isr &= ~(1 << 2);
 404             s->pics_state->pics[0].irr &= ~(1 << 2);
 405         }
 406         s->irr &= ~(1 << ret);
 407         s->isr &= ~(1 << ret);
 408         if (addr1 >> 7 || ret != 2)
 409             pic_update_irq(s->pics_state);
 410     } else {
 411         ret = 0x07;
 412         pic_update_irq(s->pics_state);
 413     }
 414
 415     return ret;
 416 }
 417
 418 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 419 {
 420     PicState *s = opaque;
 421     unsigned int addr;
 422     int ret;
 423
 424     addr = addr1;
 425     addr &= 1;
 426     if (s->poll) {
 427         ret = pic_poll_read(s, addr1);
 428         s->poll = 0;
 429     } else {
 430         if (addr == 0) {
 431             if (s->read_reg_select)
 432                 ret = s->isr;
 433             else
 434                 ret = s->irr;
 435         } else {
 436             ret = s->imr;
 437         }
 438     }
 439 #ifdef DEBUG_PIC
 440     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 441 #endif
 442     return ret;
 443 }
 444
 445 /* memory mapped interrupt status */
 446 /* XXX: may be the same than pic_read_irq() */
 447 uint32_t pic_intack_read(PicState2 *s)
 448 {
 449     int ret;
 450
 451     ret = pic_poll_read(&s->pics[0], 0x00);
 452     if (ret == 2)
 453         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 454     /* Prepare for ISR read */
 455     s->pics[0].read_reg_select = 1;
 456
 457     return ret;
 458 }
 459
 460 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 461 {
 462     PicState *s = opaque;
 463     s->elcr = val & s->elcr_mask;
 464 }
 465
 466 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 467 {
 468     PicState *s = opaque;
 469     return s->elcr;
 470 }
 471
 472 static void pic_save_common(QEMUFile *f, void *opaque)
 473 {
 474     PicState *s = opaque;
 475
 476     qemu_put_8s(f, &s->last_irr);
 477     qemu_put_8s(f, &s->irr);
 478     qemu_put_8s(f, &s->imr);
 479     qemu_put_8s(f, &s->isr);
 480     qemu_put_8s(f, &s->priority_add);
 481     qemu_put_8s(f, &s->irq_base);
 482     qemu_put_8s(f, &s->read_reg_select);
 483     qemu_put_8s(f, &s->poll);
 484     qemu_put_8s(f, &s->special_mask);
 485     qemu_put_8s(f, &s->init_state);
 486     qemu_put_8s(f, &s->auto_eoi);
 487     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 488     qemu_put_8s(f, &s->special_fully_nested_mode);
 489     qemu_put_8s(f, &s->init4);
 490     qemu_put_8s(f, &s->single_mode);
 491     qemu_put_8s(f, &s->elcr);
 492 }
 493
 494 static void pic_save(QEMUFile *f, void *opaque)
 495 {
 496     pic_save_common(f, opaque);
 497 }
 498
 499 static int pic_load_common(QEMUFile *f, void *opaque, int version_id)
 500 {
 501     PicState *s = opaque;
 502
 503     if (version_id != 1)
 504         return -EINVAL;
 505
 506     qemu_get_8s(f, &s->last_irr);
 507     qemu_get_8s(f, &s->irr);
 508     qemu_get_8s(f, &s->imr);
 509     qemu_get_8s(f, &s->isr);
 510     qemu_get_8s(f, &s->priority_add);
 511     qemu_get_8s(f, &s->irq_base);
 512     qemu_get_8s(f, &s->read_reg_select);
 513     qemu_get_8s(f, &s->poll);
 514     qemu_get_8s(f, &s->special_mask);
 515     qemu_get_8s(f, &s->init_state);
 516     qemu_get_8s(f, &s->auto_eoi);
 517     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 518     qemu_get_8s(f, &s->special_fully_nested_mode);
 519     qemu_get_8s(f, &s->init4);
 520     qemu_get_8s(f, &s->single_mode);
 521     qemu_get_8s(f, &s->elcr);
 522
 523     return 0;
 524 }
 525
 526 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 527 {
 528     return pic_load_common(f, opaque, version_id);
 529 }
 530
 531 /* XXX: add generic master/slave system */
 532 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 533 {
 534     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 535     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 536     if (elcr_addr >= 0) {
 537         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 538         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 539     }
 540     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 541     qemu_register_reset(pic_reset, s);
 542 }
 543
 544 void pic_info(Monitor *mon)
 545 {
 546     int i;
 547     PicState *s;
 548
 549     if (!isa_pic)
 550         return;
 551
 552     for(i=0;i<2;i++) {
 553         s = &isa_pic->pics[i];
 554         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 555                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 556                        i, s->irr, s->imr, s->isr, s->priority_add,
 557                        s->irq_base, s->read_reg_select, s->elcr,
 558                        s->special_fully_nested_mode);
 559     }
 560 }
 561
 562 void irq_info(Monitor *mon)
 563 {
 564 #ifndef DEBUG_IRQ_COUNT
 565     monitor_printf(mon, "irq statistic code not compiled.\n");
 566 #else
 567     int i;
 568     int64_t count;
 569
 570     monitor_printf(mon, "IRQ statistics:\n");
 571     for (i = 0; i < 16; i++) {
 572         count = irq_count[i];
 573         if (count > 0)
 574             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 575     }
 576 #endif
 577 }
 578
 579 qemu_irq *i8259_init(qemu_irq parent_irq)
 580 {
 581     PicState2 *s;
 582
 583     s = qemu_mallocz(sizeof(PicState2));
 584     pic_init1(0x20, 0x4d0, &s->pics[0]);
 585     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 586     s->pics[0].elcr_mask = 0xf8;
 587     s->pics[1].elcr_mask = 0xde;
 588     s->parent_irq = parent_irq;
 589     s->pics[0].pics_state = s;
 590     s->pics[1].pics_state = s;
 591     isa_pic = s;
 592     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 593 }
 594
 595 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 596                           void *alt_irq_opaque)
 597 {
 598     s->alt_irq_func = alt_irq_func;
 599     s->alt_irq_opaque = alt_irq_opaque;
 600 }
 601
 602 #ifdef KVM_CAP_IRQCHIP
 603 static void kvm_kernel_pic_save_to_user(PicState *s)
 604 {
 605 #if defined(TARGET_I386)
 606     struct kvm_irqchip chip;
 607     struct kvm_pic_state *kpic;
 608
 609     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 610                    KVM_IRQCHIP_PIC_MASTER :
 611                    KVM_IRQCHIP_PIC_SLAVE;
 612     kvm_get_irqchip(kvm_context, &chip);
 613     kpic = &chip.chip.pic;
 614
 615     s->last_irr = kpic->last_irr;
 616     s->irr = kpic->irr;
 617     s->imr = kpic->imr;
 618     s->isr = kpic->isr;
 619     s->priority_add = kpic->priority_add;
 620     s->irq_base = kpic->irq_base;
 621     s->read_reg_select = kpic->read_reg_select;
 622     s->poll = kpic->poll;
 623     s->special_mask = kpic->special_mask;
 624     s->init_state = kpic->init_state;
 625     s->auto_eoi = kpic->auto_eoi;
 626     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 627     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 628     s->init4 = kpic->init4;
 629     s->elcr = kpic->elcr;
 630     s->elcr_mask = kpic->elcr_mask;
 631 #endif
 632 }
 633
 634 static void kvm_kernel_pic_load_from_user(PicState *s)
 635 {
 636 #if defined(TARGET_I386)
 637     struct kvm_irqchip chip;
 638     struct kvm_pic_state *kpic;
 639
 640     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 641                    KVM_IRQCHIP_PIC_MASTER :
 642                    KVM_IRQCHIP_PIC_SLAVE;
 643     kpic = &chip.chip.pic;
 644
 645     kpic->last_irr = s->last_irr;
 646     kpic->irr = s->irr;
 647     kpic->imr = s->imr;
 648     kpic->isr = s->isr;
 649     kpic->priority_add = s->priority_add;
 650     kpic->irq_base = s->irq_base;
 651     kpic->read_reg_select = s->read_reg_select;
 652     kpic->poll = s->poll;
 653     kpic->special_mask = s->special_mask;
 654     kpic->init_state = s->init_state;
 655     kpic->auto_eoi = s->auto_eoi;
 656     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 657     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 658     kpic->init4 = s->init4;
 659     kpic->elcr = s->elcr;
 660     kpic->elcr_mask = s->elcr_mask;
 661
 662     kvm_set_irqchip(kvm_context, &chip);
 663 #endif
 664 }
 665
 666 static void kvm_i8259_set_irq(void *opaque, int irq, int level)
 667 {
 668     int pic_ret;
 669     if (kvm_set_irq(irq, level, &pic_ret)) {
 670         if (pic_ret != 0)
 671             apic_set_irq_delivered();
 672         return;
 673     }
 674 }
 675
 676 static void kvm_pic_save(QEMUFile *f, void *opaque)
 677 {
 678     PicState *s = opaque;
 679
 680     kvm_kernel_pic_save_to_user(s);
 681     pic_save_common(f, opaque);
 682 }
 683
 684 static int kvm_pic_load(QEMUFile *f, void *opaque, int version_id)
 685 {
 686     PicState *s = opaque;
 687     int r = pic_load_common(f, s, version_id);
 688     if (r == 0)
 689         kvm_kernel_pic_load_from_user(s);
 690     return r;
 691 }
 692
 693 static void kvm_pic_init1(int io_addr, PicState *s)
 694 {
 695     register_savevm("i8259", io_addr, 1, kvm_pic_save, kvm_pic_load, s);
 696     qemu_register_reset(pic_reset, s);
 697 }
 698
 699 qemu_irq *kvm_i8259_init(qemu_irq parent_irq)
 700 {
 701     PicState2 *s;
 702
 703     s = qemu_mallocz(sizeof(PicState2));
 704
 705     kvm_pic_init1(0x20, &s->pics[0]);
 706     kvm_pic_init1(0xa0, &s->pics[1]);
 707     s->parent_irq = parent_irq;
 708     s->pics[0].pics_state = s;
 709     s->pics[1].pics_state = s;
 710     isa_pic = s;
 711     return qemu_allocate_irqs(kvm_i8259_set_irq, s, 16);
 712 }
 713 #endif
 714
 715