hw/ipf.c

   1 /*
   2  * Itanium Platform Emulator derived from QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Copyright (c) 2007 Intel
   7  * Ported for IA64 Platform Zhang Xiantao <xiantao.zhang@intel.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "hw.h"
  29 #include "pc.h"
  30 #include "fdc.h"
  31 #include "pci.h"
  32 #include "block.h"
  33 #include "sysemu.h"
  34 #include "audio/audio.h"
  35 #include "net.h"
  36 #include "smbus.h"
  37 #include "boards.h"
  38 #include "firmware.h"
  39 #include "ia64intrin.h"
  40 #include <unistd.h>
  41 #include "device-assignment.h"
  42 #include "virtio-blk.h"
  43
  44 #include "qemu-kvm.h"
  45
  46 #define FW_FILENAME "Flash.fd"
  47
  48 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  49 #define ACPI_DATA_SIZE       0x10000
  50
  51 #define MAX_IDE_BUS 2
  52
  53 static fdctrl_t *floppy_controller;
  54 static RTCState *rtc_state;
  55 static PCIDevice *i440fx_state;
  56
  57 static uint32_t ipf_to_legacy_io(target_phys_addr_t addr)
  58 {
  59     return (uint32_t)(((addr&0x3ffffff) >> 12 << 2)|((addr) & 0x3));
  60 }
  61
  62 static void ipf_legacy_io_writeb(void *opaque, target_phys_addr_t addr,
  63                                  uint32_t val) {
  64     uint32_t port = ipf_to_legacy_io(addr);
  65
  66     cpu_outb(0, port, val);
  67 }
  68
  69 static void ipf_legacy_io_writew(void *opaque, target_phys_addr_t addr,
  70                                  uint32_t val) {
  71     uint32_t port = ipf_to_legacy_io(addr);
  72
  73     cpu_outw(0, port, val);
  74 }
  75
  76 static void ipf_legacy_io_writel(void *opaque, target_phys_addr_t addr,
  77                                  uint32_t val) {
  78     uint32_t port = ipf_to_legacy_io(addr);
  79
  80     cpu_outl(0, port, val);
  81 }
  82
  83 static uint32_t ipf_legacy_io_readb(void *opaque, target_phys_addr_t addr)
  84 {
  85     uint32_t port = ipf_to_legacy_io(addr);
  86
  87     return cpu_inb(0, port);
  88 }
  89
  90 static uint32_t ipf_legacy_io_readw(void *opaque, target_phys_addr_t addr)
  91 {
  92     uint32_t port = ipf_to_legacy_io(addr);
  93
  94     return cpu_inw(0, port);
  95 }
  96
  97 static uint32_t ipf_legacy_io_readl(void *opaque, target_phys_addr_t addr)
  98 {
  99     uint32_t port = ipf_to_legacy_io(addr);
 100
 101     return cpu_inl(0, port);
 102 }
 103
 104 static CPUReadMemoryFunc *ipf_legacy_io_read[3] = {
 105     ipf_legacy_io_readb,
 106     ipf_legacy_io_readw,
 107     ipf_legacy_io_readl,
 108 };
 109
 110 static CPUWriteMemoryFunc *ipf_legacy_io_write[3] = {
 111     ipf_legacy_io_writeb,
 112     ipf_legacy_io_writew,
 113     ipf_legacy_io_writel,
 114 };
 115
 116 static void pic_irq_request(void *opaque, int irq, int level)
 117 {
 118     fprintf(stderr,"pic_irq_request called!\n");
 119 }
 120
 121 /* PC cmos mappings */
 122
 123 #define REG_EQUIPMENT_BYTE          0x14
 124
 125 static int cmos_get_fd_drive_type(int fd0)
 126 {
 127     int val;
 128
 129     switch (fd0) {
 130     case 0:
 131         /* 1.44 Mb 3"5 drive */
 132         val = 4;
 133         break;
 134     case 1:
 135         /* 2.88 Mb 3"5 drive */
 136         val = 5;
 137         break;
 138     case 2:
 139         /* 1.2 Mb 5"5 drive */
 140         val = 2;
 141         break;
 142     default:
 143         val = 0;
 144         break;
 145     }
 146     return val;
 147 }
 148
 149 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 150 {
 151     RTCState *s = rtc_state;
 152     int cylinders, heads, sectors;
 153
 154     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 155     rtc_set_memory(s, type_ofs, 47);
 156     rtc_set_memory(s, info_ofs, cylinders);
 157     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 158     rtc_set_memory(s, info_ofs + 2, heads);
 159     rtc_set_memory(s, info_ofs + 3, 0xff);
 160     rtc_set_memory(s, info_ofs + 4, 0xff);
 161     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 162     rtc_set_memory(s, info_ofs + 6, cylinders);
 163     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 164     rtc_set_memory(s, info_ofs + 8, sectors);
 165 }
 166
 167 /* convert boot_device letter to something recognizable by the bios */
 168 static int boot_device2nibble(char boot_device)
 169 {
 170     switch(boot_device) {
 171     case 'a':
 172     case 'b':
 173         return 0x01; /* floppy boot */
 174     case 'c':
 175         return 0x02; /* hard drive boot */
 176     case 'd':
 177         return 0x03; /* CD-ROM boot */
 178     case 'n':
 179         return 0x04; /* Network boot */
 180     }
 181     return 0;
 182 }
 183
 184 /* hd_table must contain 4 block drivers */
 185 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 186                       const char *boot_device, BlockDriverState **hd_table)
 187 {
 188     RTCState *s = rtc_state;
 189     int nbds, bds[3] = { 0, };
 190     int val;
 191     int fd0, fd1, nb;
 192     int i;
 193
 194     /* various important CMOS locations needed by PC/Bochs bios */
 195
 196     /* memory size */
 197     val = 640; /* base memory in K */
 198     rtc_set_memory(s, 0x15, val);
 199     rtc_set_memory(s, 0x16, val >> 8);
 200
 201     val = (ram_size / 1024) - 1024;
 202     if (val > 65535)
 203         val = 65535;
 204     rtc_set_memory(s, 0x17, val);
 205     rtc_set_memory(s, 0x18, val >> 8);
 206     rtc_set_memory(s, 0x30, val);
 207     rtc_set_memory(s, 0x31, val >> 8);
 208
 209     if (above_4g_mem_size) {
 210         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 211         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 212         rtc_set_memory(s, 0x5d, above_4g_mem_size >> 32);
 213     }
 214     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 215
 216     if (ram_size > (16 * 1024 * 1024))
 217         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 218     else
 219         val = 0;
 220     if (val > 65535)
 221         val = 65535;
 222     rtc_set_memory(s, 0x34, val);
 223     rtc_set_memory(s, 0x35, val >> 8);
 224
 225     /* set boot devices, and disable floppy signature check if requested */
 226 #define PC_MAX_BOOT_DEVICES 3
 227     nbds = strlen(boot_device);
 228
 229     if (nbds > PC_MAX_BOOT_DEVICES) {
 230         fprintf(stderr, "Too many boot devices for PC\n");
 231         exit(1);
 232     }
 233
 234     for (i = 0; i < nbds; i++) {
 235         bds[i] = boot_device2nibble(boot_device[i]);
 236         if (bds[i] == 0) {
 237             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 238                     boot_device[i]);
 239             exit(1);
 240         }
 241     }
 242
 243     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 244     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 245
 246     /* floppy type */
 247
 248     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 249     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 250
 251     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 252     rtc_set_memory(s, 0x10, val);
 253
 254     val = 0;
 255     nb = 0;
 256     if (fd0 < 3)
 257         nb++;
 258     if (fd1 < 3)
 259         nb++;
 260
 261     switch (nb) {
 262     case 0:
 263         break;
 264     case 1:
 265         val |= 0x01; /* 1 drive, ready for boot */
 266         break;
 267     case 2:
 268         val |= 0x41; /* 2 drives, ready for boot */
 269         break;
 270     }
 271
 272     val |= 0x02; /* FPU is there */
 273     val |= 0x04; /* PS/2 mouse installed */
 274     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 275
 276     /* hard drives */
 277
 278     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 279     if (hd_table[0])
 280         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 281     if (hd_table[1])
 282         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 283
 284     val = 0;
 285     for (i = 0; i < 4; i++) {
 286         if (hd_table[i]) {
 287             int cylinders, heads, sectors, translation;
 288             /* NOTE: bdrv_get_geometry_hint() returns the physical
 289                geometry.  It is always such that: 1 <= sects <= 63, 1
 290                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 291                geometry can be different if a translation is done. */
 292             translation = bdrv_get_translation_hint(hd_table[i]);
 293             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 294                 bdrv_get_geometry_hint(hd_table[i], &cylinders,
 295                                        &heads, &sectors);
 296                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 297                     /* No translation. */
 298                     translation = 0;
 299                 } else {
 300                     /* LBA translation. */
 301                     translation = 1;
 302                 }
 303             } else {
 304                 translation--;
 305             }
 306             val |= translation << (i * 2);
 307         }
 308     }
 309     rtc_set_memory(s, 0x39, val);
 310 }
 311
 312 static void main_cpu_reset(void *opaque)
 313 {
 314     CPUState *env = opaque;
 315     cpu_reset(env);
 316 }
 317
 318 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 319 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 320 static const int ide_irq[2] = { 14, 15 };
 321
 322 #define NE2000_NB_MAX 6
 323
 324 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340,
 325                                         0x360, 0x280, 0x380 };
 326 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 327
 328 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 329 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 330
 331 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 332 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 333
 334 #ifdef HAS_AUDIO
 335 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 336 {
 337     struct soundhw *c;
 338     int audio_enabled = 0;
 339
 340     for (c = soundhw; !audio_enabled && c->name; ++c) {
 341         audio_enabled = c->enabled;
 342     }
 343
 344     if (audio_enabled) {
 345         AudioState *s;
 346
 347         s = AUD_init ();
 348         if (s) {
 349             for (c = soundhw; c->name; ++c) {
 350                 if (c->enabled) {
 351                     if (c->isa) {
 352                         c->init.init_isa (s, pic);
 353                     } else {
 354                         if (pci_bus) {
 355                             c->init.init_pci (pci_bus, s);
 356                         }
 357                     }
 358                 }
 359             }
 360         }
 361     }
 362 }
 363 #endif
 364
 365 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 366 {
 367     static int nb_ne2k = 0;
 368
 369     if (nb_ne2k == NE2000_NB_MAX)
 370         return;
 371     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 372     nb_ne2k++;
 373 }
 374
 375 /* Itanium hardware initialisation */
 376 static void ipf_init1(ram_addr_t ram_size,
 377                       const char *boot_device, DisplayState *ds,
 378                       const char *kernel_filename, const char *kernel_cmdline,
 379                       const char *initrd_filename,
 380                       int pci_enabled, const char *cpu_model)
 381 {
 382     char buf[1024];
 383     int i;
 384     ram_addr_t ram_addr;
 385     ram_addr_t above_4g_mem_size = 0;
 386     PCIBus *pci_bus;
 387     PCIDevice *pci_dev;
 388     int piix3_devfn = -1;
 389     CPUState *env;
 390     qemu_irq *cpu_irq;
 391     qemu_irq *i8259;
 392     int page_size;
 393     int index;
 394     unsigned long ipf_legacy_io_base, ipf_legacy_io_mem;
 395     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 396     BlockDriverState *fd[MAX_FD];
 397
 398     page_size = getpagesize();
 399     if (page_size != TARGET_PAGE_SIZE) {
 400         fprintf(stderr,"Error! Host page size != qemu target page size,"
 401                 " you may need to change TARGET_PAGE_BITS in qemu!"
 402                 "host page size:0x%x\n", page_size);
 403         exit(-1);
 404     };
 405
 406     if (ram_size >= 0xc0000000 ) {
 407         above_4g_mem_size = ram_size - 0xc0000000;
 408         ram_size = 0xc0000000;
 409     }
 410
 411     /* init CPUs */
 412     if (cpu_model == NULL) {
 413         cpu_model = "IA64";
 414     }
 415
 416     for(i = 0; i < smp_cpus; i++) {
 417         env = cpu_init(cpu_model);
 418         if (!env) {
 419             fprintf(stderr, "Unable to find CPU definition\n");
 420             exit(1);
 421         }
 422         if (i != 0)
 423             env->hflags |= HF_HALTED_MASK;
 424         register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
 425         qemu_register_reset(main_cpu_reset, 0, env);
 426     }
 427
 428     /* allocate RAM */
 429     if (kvm_enabled()) {
 430         ram_addr = qemu_ram_alloc(0xa0000);
 431         cpu_register_physical_memory(0, 0xa0000, ram_addr);
 432
 433         ram_addr = qemu_ram_alloc(0x20000); // Workaround 0xa0000-0xc0000
 434
 435         ram_addr = qemu_ram_alloc(0x40000);
 436         cpu_register_physical_memory(0xc0000, 0x40000, ram_addr);
 437
 438         ram_addr = qemu_ram_alloc(ram_size - 0x100000);
 439         cpu_register_physical_memory(0x100000, ram_size - 0x100000, ram_addr);
 440     } else {
 441         ram_addr = qemu_ram_alloc(ram_size);
 442         cpu_register_physical_memory(0, ram_size, ram_addr);
 443     }
 444
 445     /* above 4giga memory allocation */
 446     if (above_4g_mem_size > 0) {
 447         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 448         cpu_register_physical_memory(0x100000000, above_4g_mem_size, ram_addr);
 449     }
 450
 451     /*Load firware to its proper position.*/
 452     if (kvm_enabled()) {
 453         unsigned long  image_size;
 454         uint8_t *image = NULL;
 455         unsigned long nvram_addr;
 456         unsigned long nvram_fd = 0;
 457         unsigned long type = READ_FROM_NVRAM;
 458         unsigned long i = 0;
 459         unsigned long fw_offset;
 460         ram_addr_t fw_mem = qemu_ram_alloc(GFW_SIZE);
 461
 462         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, FW_FILENAME);
 463         image = read_image(buf, &image_size );
 464         if (NULL == image || !image_size) {
 465             fprintf(stderr, "Error when reading Guest Firmware!\n");
 466             fprintf(stderr, "Please check Guest firmware at %s\n", buf);
 467             exit(1);
 468         }
 469         fw_offset = GFW_START + GFW_SIZE - image_size;
 470
 471         cpu_register_physical_memory(GFW_START, GFW_SIZE, fw_mem);
 472         cpu_physical_memory_write(fw_offset, image, image_size);
 473
 474         free(image);
 475
 476         if (nvram) {
 477             nvram_addr = NVRAM_START;
 478             nvram_fd = kvm_ia64_nvram_init(type);
 479             if (nvram_fd != -1) {
 480                 kvm_ia64_copy_from_nvram_to_GFW(nvram_fd);
 481                 close(nvram_fd);
 482             }
 483             i = atexit((void *)kvm_ia64_copy_from_GFW_to_nvram);
 484             if (i != 0)
 485                 fprintf(stderr, "cannot set exit function\n");
 486         } else
 487             nvram_addr = 0;
 488
 489         kvm_ia64_build_hob(ram_size + above_4g_mem_size, smp_cpus, nvram_addr);
 490     }
 491
 492     /*Register legacy io address space, size:64M*/
 493     ipf_legacy_io_base = 0xE0000000;
 494     ipf_legacy_io_mem = cpu_register_io_memory(0, ipf_legacy_io_read,
 495                                                ipf_legacy_io_write, NULL);
 496     cpu_register_physical_memory(ipf_legacy_io_base, 64*1024*1024,
 497                                  ipf_legacy_io_mem);
 498
 499     cpu_irq = qemu_allocate_irqs(pic_irq_request, first_cpu, 1);
 500     i8259 = kvm_i8259_init(cpu_irq[0]);
 501
 502     if (pci_enabled) {
 503         pci_bus = i440fx_init(&i440fx_state, i8259);
 504         piix3_devfn = piix3_init(pci_bus, -1);
 505     } else {
 506         pci_bus = NULL;
 507     }
 508
 509     if (cirrus_vga_enabled) {
 510         if (pci_enabled)
 511             pci_cirrus_vga_init(pci_bus);
 512         else
 513             isa_cirrus_vga_init();
 514     } else {
 515         if (pci_enabled)
 516             pci_vga_init(pci_bus, 0, 0);
 517         else
 518             isa_vga_init();
 519     }
 520
 521     rtc_state = rtc_init(0x70, i8259[8], 2000);
 522
 523     if (pci_enabled) {
 524         pic_set_alt_irq_func(isa_pic, NULL, NULL);
 525     }
 526
 527     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 528         if (serial_hds[i]) {
 529             serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
 530                         serial_hds[i]);
 531         }
 532     }
 533
 534     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 535         if (parallel_hds[i]) {
 536             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
 537                           parallel_hds[i]);
 538         }
 539     }
 540
 541     for(i = 0; i < nb_nics; i++) {
 542         NICInfo *nd = &nd_table[i];
 543
 544         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
 545             pc_init_ne2k_isa(nd, i8259);
 546         else
 547             pci_nic_init(nd, "e1000", NULL);
 548     }
 549
 550 #undef USE_HYPERCALL  //Disable it now, need to implement later!
 551 #ifdef USE_HYPERCALL
 552     pci_hypercall_init(pci_bus);
 553 #endif
 554
 555     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 556         fprintf(stderr, "qemu: too many IDE bus\n");
 557         exit(1);
 558     }
 559
 560     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 561         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 562         if (index != -1)
 563             hd[i] = drives_table[index].bdrv;
 564         else
 565             hd[i] = NULL;
 566     }
 567
 568     if (pci_enabled) {
 569         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
 570     } else {
 571         for(i = 0; i < MAX_IDE_BUS; i++) {
 572             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 573                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
 574         }
 575     }
 576
 577     i8042_init(i8259[1], i8259[12], 0x60);
 578     DMA_init(0);
 579 #ifdef HAS_AUDIO
 580     audio_init(pci_enabled ? pci_bus : NULL, i8259);
 581 #endif
 582
 583     for(i = 0; i < MAX_FD; i++) {
 584         index = drive_get_index(IF_FLOPPY, 0, i);
 585         if (index != -1)
 586             fd[i] = drives_table[index].bdrv;
 587         else
 588             fd[i] = NULL;
 589     }
 590     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
 591
 592     cmos_init(ram_size, above_4g_mem_size, boot_device, hd);
 593
 594     if (pci_enabled && usb_enabled) {
 595         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
 596     }
 597
 598     if (pci_enabled && acpi_enabled) {
 599         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
 600         i2c_bus *smbus;
 601
 602         /* TODO: Populate SPD eeprom data.  */
 603         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
 604         for (i = 0; i < 8; i++) {
 605             DeviceState *eeprom;
 606             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
 607             qdev_set_prop_int(eeprom, "address", 0x50 + i);
 608             qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
 609             qdev_init(eeprom);
 610         }
 611     }
 612
 613     if (i440fx_state) {
 614         i440fx_init_memory_mappings(i440fx_state);
 615     }
 616
 617     if (pci_enabled) {
 618         int max_bus;
 619         int bus;
 620
 621         max_bus = drive_get_max_bus(IF_SCSI);
 622         for (bus = 0; bus <= max_bus; bus++) {
 623             pci_create_simple(pci_bus, -1, "lsi53c895a");
 624         }
 625     }
 626     /* Add virtio block devices */
 627     if (pci_enabled) {
 628         int index;
 629         int unit_id = 0;
 630
 631         while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
 632             pci_dev = pci_create("virtio-blk-pci",
 633                                  drives_table[index].devaddr);
 634             qdev_init(&pci_dev->qdev);
 635             unit_id++;
 636         }
 637     }
 638
 639 #ifdef USE_KVM_DEVICE_ASSIGNMENT
 640     if (kvm_enabled())
 641         add_assigned_devices(pci_bus, assigned_devices, assigned_devices_index);
 642 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
 643
 644 }
 645
 646 static void ipf_init_pci(ram_addr_t ram_size,
 647                          const char *boot_device, DisplayState *ds,
 648                          const char *kernel_filename,
 649                          const char *kernel_cmdline,
 650                          const char *initrd_filename,
 651                          const char *cpu_model)
 652 {
 653     ipf_init1(ram_size, boot_device, ds, kernel_filename,
 654               kernel_cmdline, initrd_filename, 1, cpu_model);
 655 }
 656
 657 QEMUMachine ipf_machine = {
 658     .name = "itanium",
 659     .desc = "Itanium Platform",
 660     .init = (QEMUMachineInitFunc *)ipf_init_pci,
 661     .max_cpus = 255,
 662     .is_default = 1,
 663 };
 664
 665 static void ipf_machine_init(void)
 666 {
 667     qemu_register_machine(&ipf_machine);
 668 }
 669
 670 machine_init(ipf_machine_init);
 671
 672 #define IOAPIC_NUM_PINS 48
 673
 674 static int ioapic_irq_count[IOAPIC_NUM_PINS];
 675
 676 static int ioapic_map_irq(int devfn, int irq_num)
 677 {
 678     int irq, dev;
 679     dev = devfn >> 3;
 680     irq = ((((dev << 2) + (dev >> 3) + irq_num) & 31) + 16);
 681     return irq;
 682 }
 683
 684 /*
 685  * Dummy function to provide match for call from hw/apic.c
 686  */
 687 void apic_set_irq_delivered(void) {
 688 }
 689
 690 void ioapic_set_irq(void *opaque, int irq_num, int level)
 691 {
 692     int vector, pic_ret;
 693
 694     PCIDevice *pci_dev = (PCIDevice *)opaque;
 695     vector = ioapic_map_irq(pci_dev->devfn, irq_num);
 696
 697     if (level)
 698         ioapic_irq_count[vector] += 1;
 699     else
 700         ioapic_irq_count[vector] -= 1;
 701
 702     if (kvm_enabled()) {
 703         if (kvm_set_irq(vector, ioapic_irq_count[vector] == 0, &pic_ret))
 704             if (pic_ret != 0)
 705                 apic_set_irq_delivered();
 706             return;
 707     }
 708 }
 709
 710 int ipf_map_irq(PCIDevice *pci_dev, int irq_num)
 711 {
 712         return ioapic_map_irq(pci_dev->devfn, irq_num);
 713 }