hw/twl92230.c

   1 /*
   2  * TI TWL92230C energy-management companion device for the OMAP24xx.
   3  * Aka. Menelaus (N4200 MENELAUS1_V2.2)
   4  *
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Written by Andrzej Zaborowski <andrew@openedhand.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) version 3 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "hw.h"
  23 #include "qemu-timer.h"
  24 #include "i2c.h"
  25 #include "sysemu.h"
  26 #include "console.h"
  27
  28 #define VERBOSE 1
  29
  30 typedef struct {
  31     i2c_slave i2c;
  32
  33     int firstbyte;
  34     uint8_t reg;
  35
  36     uint8_t vcore[5];
  37     uint8_t dcdc[3];
  38     uint8_t ldo[8];
  39     uint8_t sleep[2];
  40     uint8_t osc;
  41     uint8_t detect;
  42     uint16_t mask;
  43     uint16_t status;
  44     uint8_t dir;
  45     uint8_t inputs;
  46     uint8_t outputs;
  47     uint8_t bbsms;
  48     uint8_t pull[4];
  49     uint8_t mmc_ctrl[3];
  50     uint8_t mmc_debounce;
  51     struct {
  52         uint8_t ctrl;
  53         uint16_t comp;
  54         QEMUTimer *hz_tm;
  55         int64_t next;
  56         struct tm tm;
  57         struct tm new;
  58         struct tm alm;
  59         int sec_offset;
  60         int alm_sec;
  61         int next_comp;
  62     } rtc;
  63     qemu_irq out[4];
  64     qemu_irq *in;
  65     int pwrbtn_state;
  66     qemu_irq pwrbtn;
  67 } MenelausState;
  68
  69 static inline void menelaus_update(MenelausState *s)
  70 {
  71     qemu_set_irq(s->out[3], s->status & ~s->mask);
  72 }
  73
  74 static inline void menelaus_rtc_start(MenelausState *s)
  75 {
  76     s->rtc.next =+ qemu_get_clock(rt_clock);
  77     qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
  78 }
  79
  80 static inline void menelaus_rtc_stop(MenelausState *s)
  81 {
  82     qemu_del_timer(s->rtc.hz_tm);
  83     s->rtc.next =- qemu_get_clock(rt_clock);
  84     if (s->rtc.next < 1)
  85         s->rtc.next = 1;
  86 }
  87
  88 static void menelaus_rtc_update(MenelausState *s)
  89 {
  90     qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
  91 }
  92
  93 static void menelaus_alm_update(MenelausState *s)
  94 {
  95     if ((s->rtc.ctrl & 3) == 3)
  96         s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
  97 }
  98
  99 static void menelaus_rtc_hz(void *opaque)
 100 {
 101     MenelausState *s = (MenelausState *) opaque;
 102
 103     s->rtc.next_comp --;
 104     s->rtc.alm_sec --;
 105     s->rtc.next += 1000;
 106     qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
 107     if ((s->rtc.ctrl >> 3) & 3) {                               /* EVERY */
 108         menelaus_rtc_update(s);
 109         if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
 110             s->status |= 1 << 8;                                /* RTCTMR */
 111         else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
 112             s->status |= 1 << 8;                                /* RTCTMR */
 113         else if (!s->rtc.tm.tm_hour)
 114             s->status |= 1 << 8;                                /* RTCTMR */
 115     } else
 116         s->status |= 1 << 8;                                    /* RTCTMR */
 117     if ((s->rtc.ctrl >> 1) & 1) {                               /* RTC_AL_EN */
 118         if (s->rtc.alm_sec == 0)
 119             s->status |= 1 << 9;                                /* RTCALM */
 120         /* TODO: wake-up */
 121     }
 122     if (s->rtc.next_comp <= 0) {
 123         s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
 124         s->rtc.next_comp = 3600;
 125     }
 126     menelaus_update(s);
 127 }
 128
 129 static void menelaus_reset(i2c_slave *i2c)
 130 {
 131     MenelausState *s = (MenelausState *) i2c;
 132     s->reg = 0x00;
 133
 134     s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check!  */
 135     s->vcore[1] = 0x05;
 136     s->vcore[2] = 0x02;
 137     s->vcore[3] = 0x0c;
 138     s->vcore[4] = 0x03;
 139     s->dcdc[0] = 0x33;  /* Depends on wiring */
 140     s->dcdc[1] = 0x03;
 141     s->dcdc[2] = 0x00;
 142     s->ldo[0] = 0x95;
 143     s->ldo[1] = 0x7e;
 144     s->ldo[2] = 0x00;
 145     s->ldo[3] = 0x00;   /* Depends on wiring */
 146     s->ldo[4] = 0x03;   /* Depends on wiring */
 147     s->ldo[5] = 0x00;
 148     s->ldo[6] = 0x00;
 149     s->ldo[7] = 0x00;
 150     s->sleep[0] = 0x00;
 151     s->sleep[1] = 0x00;
 152     s->osc = 0x01;
 153     s->detect = 0x09;
 154     s->mask = 0x0fff;
 155     s->status = 0;
 156     s->dir = 0x07;
 157     s->outputs = 0x00;
 158     s->bbsms = 0x00;
 159     s->pull[0] = 0x00;
 160     s->pull[1] = 0x00;
 161     s->pull[2] = 0x00;
 162     s->pull[3] = 0x00;
 163     s->mmc_ctrl[0] = 0x03;
 164     s->mmc_ctrl[1] = 0xc0;
 165     s->mmc_ctrl[2] = 0x00;
 166     s->mmc_debounce = 0x05;
 167
 168     if (s->rtc.ctrl & 1)
 169         menelaus_rtc_stop(s);
 170     s->rtc.ctrl = 0x00;
 171     s->rtc.comp = 0x0000;
 172     s->rtc.next = 1000;
 173     s->rtc.sec_offset = 0;
 174     s->rtc.next_comp = 1800;
 175     s->rtc.alm_sec = 1800;
 176     s->rtc.alm.tm_sec = 0x00;
 177     s->rtc.alm.tm_min = 0x00;
 178     s->rtc.alm.tm_hour = 0x00;
 179     s->rtc.alm.tm_mday = 0x01;
 180     s->rtc.alm.tm_mon = 0x00;
 181     s->rtc.alm.tm_year = 2004;
 182     menelaus_update(s);
 183 }
 184
 185 static inline uint8_t to_bcd(int val)
 186 {
 187     return ((val / 10) << 4) | (val % 10);
 188 }
 189
 190 static inline int from_bcd(uint8_t val)
 191 {
 192     return ((val >> 4) * 10) + (val & 0x0f);
 193 }
 194
 195 static void menelaus_gpio_set(void *opaque, int line, int level)
 196 {
 197     MenelausState *s = (MenelausState *) opaque;
 198
 199     /* No interrupt generated */
 200     s->inputs &= ~(1 << line);
 201     s->inputs |= level << line;
 202 }
 203
 204 static void menelaus_pwrbtn_set(void *opaque, int line, int level)
 205 {
 206     MenelausState *s = (MenelausState *) opaque;
 207
 208     if (!s->pwrbtn_state && level) {
 209         s->status |= 1 << 11;                                   /* PSHBTN */
 210         menelaus_update(s);
 211     }
 212     s->pwrbtn_state = level;
 213 }
 214
 215 #define MENELAUS_REV            0x01
 216 #define MENELAUS_VCORE_CTRL1    0x02
 217 #define MENELAUS_VCORE_CTRL2    0x03
 218 #define MENELAUS_VCORE_CTRL3    0x04
 219 #define MENELAUS_VCORE_CTRL4    0x05
 220 #define MENELAUS_VCORE_CTRL5    0x06
 221 #define MENELAUS_DCDC_CTRL1     0x07
 222 #define MENELAUS_DCDC_CTRL2     0x08
 223 #define MENELAUS_DCDC_CTRL3     0x09
 224 #define MENELAUS_LDO_CTRL1      0x0a
 225 #define MENELAUS_LDO_CTRL2      0x0b
 226 #define MENELAUS_LDO_CTRL3      0x0c
 227 #define MENELAUS_LDO_CTRL4      0x0d
 228 #define MENELAUS_LDO_CTRL5      0x0e
 229 #define MENELAUS_LDO_CTRL6      0x0f
 230 #define MENELAUS_LDO_CTRL7      0x10
 231 #define MENELAUS_LDO_CTRL8      0x11
 232 #define MENELAUS_SLEEP_CTRL1    0x12
 233 #define MENELAUS_SLEEP_CTRL2    0x13
 234 #define MENELAUS_DEVICE_OFF     0x14
 235 #define MENELAUS_OSC_CTRL       0x15
 236 #define MENELAUS_DETECT_CTRL    0x16
 237 #define MENELAUS_INT_MASK1      0x17
 238 #define MENELAUS_INT_MASK2      0x18
 239 #define MENELAUS_INT_STATUS1    0x19
 240 #define MENELAUS_INT_STATUS2    0x1a
 241 #define MENELAUS_INT_ACK1       0x1b
 242 #define MENELAUS_INT_ACK2       0x1c
 243 #define MENELAUS_GPIO_CTRL      0x1d
 244 #define MENELAUS_GPIO_IN        0x1e
 245 #define MENELAUS_GPIO_OUT       0x1f
 246 #define MENELAUS_BBSMS          0x20
 247 #define MENELAUS_RTC_CTRL       0x21
 248 #define MENELAUS_RTC_UPDATE     0x22
 249 #define MENELAUS_RTC_SEC        0x23
 250 #define MENELAUS_RTC_MIN        0x24
 251 #define MENELAUS_RTC_HR         0x25
 252 #define MENELAUS_RTC_DAY        0x26
 253 #define MENELAUS_RTC_MON        0x27
 254 #define MENELAUS_RTC_YR         0x28
 255 #define MENELAUS_RTC_WKDAY      0x29
 256 #define MENELAUS_RTC_AL_SEC     0x2a
 257 #define MENELAUS_RTC_AL_MIN     0x2b
 258 #define MENELAUS_RTC_AL_HR      0x2c
 259 #define MENELAUS_RTC_AL_DAY     0x2d
 260 #define MENELAUS_RTC_AL_MON     0x2e
 261 #define MENELAUS_RTC_AL_YR      0x2f
 262 #define MENELAUS_RTC_COMP_MSB   0x30
 263 #define MENELAUS_RTC_COMP_LSB   0x31
 264 #define MENELAUS_S1_PULL_EN     0x32
 265 #define MENELAUS_S1_PULL_DIR    0x33
 266 #define MENELAUS_S2_PULL_EN     0x34
 267 #define MENELAUS_S2_PULL_DIR    0x35
 268 #define MENELAUS_MCT_CTRL1      0x36
 269 #define MENELAUS_MCT_CTRL2      0x37
 270 #define MENELAUS_MCT_CTRL3      0x38
 271 #define MENELAUS_MCT_PIN_ST     0x39
 272 #define MENELAUS_DEBOUNCE1      0x3a
 273
 274 static uint8_t menelaus_read(void *opaque, uint8_t addr)
 275 {
 276     MenelausState *s = (MenelausState *) opaque;
 277     int reg = 0;
 278
 279     switch (addr) {
 280     case MENELAUS_REV:
 281         return 0x22;
 282
 283     case MENELAUS_VCORE_CTRL5: reg ++;
 284     case MENELAUS_VCORE_CTRL4: reg ++;
 285     case MENELAUS_VCORE_CTRL3: reg ++;
 286     case MENELAUS_VCORE_CTRL2: reg ++;
 287     case MENELAUS_VCORE_CTRL1:
 288         return s->vcore[reg];
 289
 290     case MENELAUS_DCDC_CTRL3: reg ++;
 291     case MENELAUS_DCDC_CTRL2: reg ++;
 292     case MENELAUS_DCDC_CTRL1:
 293         return s->dcdc[reg];
 294
 295     case MENELAUS_LDO_CTRL8: reg ++;
 296     case MENELAUS_LDO_CTRL7: reg ++;
 297     case MENELAUS_LDO_CTRL6: reg ++;
 298     case MENELAUS_LDO_CTRL5: reg ++;
 299     case MENELAUS_LDO_CTRL4: reg ++;
 300     case MENELAUS_LDO_CTRL3: reg ++;
 301     case MENELAUS_LDO_CTRL2: reg ++;
 302     case MENELAUS_LDO_CTRL1:
 303         return s->ldo[reg];
 304
 305     case MENELAUS_SLEEP_CTRL2: reg ++;
 306     case MENELAUS_SLEEP_CTRL1:
 307         return s->sleep[reg];
 308
 309     case MENELAUS_DEVICE_OFF:
 310         return 0;
 311
 312     case MENELAUS_OSC_CTRL:
 313         return s->osc | (1 << 7);                       /* CLK32K_GOOD */
 314
 315     case MENELAUS_DETECT_CTRL:
 316         return s->detect;
 317
 318     case MENELAUS_INT_MASK1:
 319         return (s->mask >> 0) & 0xff;
 320     case MENELAUS_INT_MASK2:
 321         return (s->mask >> 8) & 0xff;
 322
 323     case MENELAUS_INT_STATUS1:
 324         return (s->status >> 0) & 0xff;
 325     case MENELAUS_INT_STATUS2:
 326         return (s->status >> 8) & 0xff;
 327
 328     case MENELAUS_INT_ACK1:
 329     case MENELAUS_INT_ACK2:
 330         return 0;
 331
 332     case MENELAUS_GPIO_CTRL:
 333         return s->dir;
 334     case MENELAUS_GPIO_IN:
 335         return s->inputs | (~s->dir & s->outputs);
 336     case MENELAUS_GPIO_OUT:
 337         return s->outputs;
 338
 339     case MENELAUS_BBSMS:
 340         return s->bbsms;
 341
 342     case MENELAUS_RTC_CTRL:
 343         return s->rtc.ctrl;
 344     case MENELAUS_RTC_UPDATE:
 345         return 0x00;
 346     case MENELAUS_RTC_SEC:
 347         menelaus_rtc_update(s);
 348         return to_bcd(s->rtc.tm.tm_sec);
 349     case MENELAUS_RTC_MIN:
 350         menelaus_rtc_update(s);
 351         return to_bcd(s->rtc.tm.tm_min);
 352     case MENELAUS_RTC_HR:
 353         menelaus_rtc_update(s);
 354         if ((s->rtc.ctrl >> 2) & 1)                     /* MODE12_n24 */
 355             return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
 356                     (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
 357         else
 358             return to_bcd(s->rtc.tm.tm_hour);
 359     case MENELAUS_RTC_DAY:
 360         menelaus_rtc_update(s);
 361         return to_bcd(s->rtc.tm.tm_mday);
 362     case MENELAUS_RTC_MON:
 363         menelaus_rtc_update(s);
 364         return to_bcd(s->rtc.tm.tm_mon + 1);
 365     case MENELAUS_RTC_YR:
 366         menelaus_rtc_update(s);
 367         return to_bcd(s->rtc.tm.tm_year - 2000);
 368     case MENELAUS_RTC_WKDAY:
 369         menelaus_rtc_update(s);
 370         return to_bcd(s->rtc.tm.tm_wday);
 371     case MENELAUS_RTC_AL_SEC:
 372         return to_bcd(s->rtc.alm.tm_sec);
 373     case MENELAUS_RTC_AL_MIN:
 374         return to_bcd(s->rtc.alm.tm_min);
 375     case MENELAUS_RTC_AL_HR:
 376         if ((s->rtc.ctrl >> 2) & 1)                     /* MODE12_n24 */
 377             return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
 378                     (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
 379         else
 380             return to_bcd(s->rtc.alm.tm_hour);
 381     case MENELAUS_RTC_AL_DAY:
 382         return to_bcd(s->rtc.alm.tm_mday);
 383     case MENELAUS_RTC_AL_MON:
 384         return to_bcd(s->rtc.alm.tm_mon + 1);
 385     case MENELAUS_RTC_AL_YR:
 386         return to_bcd(s->rtc.alm.tm_year - 2000);
 387     case MENELAUS_RTC_COMP_MSB:
 388         return (s->rtc.comp >> 8) & 0xff;
 389     case MENELAUS_RTC_COMP_LSB:
 390         return (s->rtc.comp >> 0) & 0xff;
 391
 392     case MENELAUS_S1_PULL_EN:
 393         return s->pull[0];
 394     case MENELAUS_S1_PULL_DIR:
 395         return s->pull[1];
 396     case MENELAUS_S2_PULL_EN:
 397         return s->pull[2];
 398     case MENELAUS_S2_PULL_DIR:
 399         return s->pull[3];
 400
 401     case MENELAUS_MCT_CTRL3: reg ++;
 402     case MENELAUS_MCT_CTRL2: reg ++;
 403     case MENELAUS_MCT_CTRL1:
 404         return s->mmc_ctrl[reg];
 405     case MENELAUS_MCT_PIN_ST:
 406         /* TODO: return the real Card Detect */
 407         return 0;
 408     case MENELAUS_DEBOUNCE1:
 409         return s->mmc_debounce;
 410
 411     default:
 412 #ifdef VERBOSE
 413         printf("%s: unknown register %02x\n", __FUNCTION__, addr);
 414 #endif
 415         break;
 416     }
 417     return 0;
 418 }
 419
 420 static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
 421 {
 422     MenelausState *s = (MenelausState *) opaque;
 423     int line;
 424     int reg = 0;
 425     struct tm tm;
 426
 427     switch (addr) {
 428     case MENELAUS_VCORE_CTRL1:
 429         s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
 430         break;
 431     case MENELAUS_VCORE_CTRL2:
 432         s->vcore[1] = value;
 433         break;
 434     case MENELAUS_VCORE_CTRL3:
 435         s->vcore[2] = MIN(value & 0x1f, 0x12);
 436         break;
 437     case MENELAUS_VCORE_CTRL4:
 438         s->vcore[3] = MIN(value & 0x1f, 0x12);
 439         break;
 440     case MENELAUS_VCORE_CTRL5:
 441         s->vcore[4] = value & 3;
 442         /* XXX
 443          * auto set to 3 on M_Active, nRESWARM
 444          * auto set to 0 on M_WaitOn, M_Backup
 445          */
 446         break;
 447
 448     case MENELAUS_DCDC_CTRL1:
 449         s->dcdc[0] = value & 0x3f;
 450         break;
 451     case MENELAUS_DCDC_CTRL2:
 452         s->dcdc[1] = value & 0x07;
 453         /* XXX
 454          * auto set to 3 on M_Active, nRESWARM
 455          * auto set to 0 on M_WaitOn, M_Backup
 456          */
 457         break;
 458     case MENELAUS_DCDC_CTRL3:
 459         s->dcdc[2] = value & 0x07;
 460         break;
 461
 462     case MENELAUS_LDO_CTRL1:
 463         s->ldo[0] = value;
 464         break;
 465     case MENELAUS_LDO_CTRL2:
 466         s->ldo[1] = value & 0x7f;
 467         /* XXX
 468          * auto set to 0x7e on M_WaitOn, M_Backup
 469          */
 470         break;
 471     case MENELAUS_LDO_CTRL3:
 472         s->ldo[2] = value & 3;
 473         /* XXX
 474          * auto set to 3 on M_Active, nRESWARM
 475          * auto set to 0 on M_WaitOn, M_Backup
 476          */
 477         break;
 478     case MENELAUS_LDO_CTRL4:
 479         s->ldo[3] = value & 3;
 480         /* XXX
 481          * auto set to 3 on M_Active, nRESWARM
 482          * auto set to 0 on M_WaitOn, M_Backup
 483          */
 484         break;
 485     case MENELAUS_LDO_CTRL5:
 486         s->ldo[4] = value & 3;
 487         /* XXX
 488          * auto set to 3 on M_Active, nRESWARM
 489          * auto set to 0 on M_WaitOn, M_Backup
 490          */
 491         break;
 492     case MENELAUS_LDO_CTRL6:
 493         s->ldo[5] = value & 3;
 494         break;
 495     case MENELAUS_LDO_CTRL7:
 496         s->ldo[6] = value & 3;
 497         break;
 498     case MENELAUS_LDO_CTRL8:
 499         s->ldo[7] = value & 3;
 500         break;
 501
 502     case MENELAUS_SLEEP_CTRL2: reg ++;
 503     case MENELAUS_SLEEP_CTRL1:
 504         s->sleep[reg] = value;
 505         break;
 506
 507     case MENELAUS_DEVICE_OFF:
 508         if (value & 1)
 509             menelaus_reset(&s->i2c);
 510         break;
 511
 512     case MENELAUS_OSC_CTRL:
 513         s->osc = value & 7;
 514         break;
 515
 516     case MENELAUS_DETECT_CTRL:
 517         s->detect = value & 0x7f;
 518         break;
 519
 520     case MENELAUS_INT_MASK1:
 521         s->mask &= 0xf00;
 522         s->mask |= value << 0;
 523         menelaus_update(s);
 524         break;
 525     case MENELAUS_INT_MASK2:
 526         s->mask &= 0x0ff;
 527         s->mask |= value << 8;
 528         menelaus_update(s);
 529         break;
 530
 531     case MENELAUS_INT_ACK1:
 532         s->status &= ~(((uint16_t) value) << 0);
 533         menelaus_update(s);
 534         break;
 535     case MENELAUS_INT_ACK2:
 536         s->status &= ~(((uint16_t) value) << 8);
 537         menelaus_update(s);
 538         break;
 539
 540     case MENELAUS_GPIO_CTRL:
 541         for (line = 0; line < 3; line ++) {
 542             if (((s->dir ^ value) >> line) & 1) {
 543                 qemu_set_irq(s->out[line],
 544                              ((s->outputs & ~s->dir) >> line) & 1);
 545             }
 546         }
 547         s->dir = value & 0x67;
 548         break;
 549     case MENELAUS_GPIO_OUT:
 550         for (line = 0; line < 3; line ++) {
 551             if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
 552                 qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
 553             }
 554         }
 555         s->outputs = value & 0x07;
 556         break;
 557
 558     case MENELAUS_BBSMS:
 559         s->bbsms = 0x0d;
 560         break;
 561
 562     case MENELAUS_RTC_CTRL:
 563         if ((s->rtc.ctrl ^ value) & 1) {                        /* RTC_EN */
 564             if (value & 1)
 565                 menelaus_rtc_start(s);
 566             else
 567                 menelaus_rtc_stop(s);
 568         }
 569         s->rtc.ctrl = value & 0x1f;
 570         menelaus_alm_update(s);
 571         break;
 572     case MENELAUS_RTC_UPDATE:
 573         menelaus_rtc_update(s);
 574         memcpy(&tm, &s->rtc.tm, sizeof(tm));
 575         switch (value & 0xf) {
 576         case 0:
 577             break;
 578         case 1:
 579             tm.tm_sec = s->rtc.new.tm_sec;
 580             break;
 581         case 2:
 582             tm.tm_min = s->rtc.new.tm_min;
 583             break;
 584         case 3:
 585             if (s->rtc.new.tm_hour > 23)
 586                 goto rtc_badness;
 587             tm.tm_hour = s->rtc.new.tm_hour;
 588             break;
 589         case 4:
 590             if (s->rtc.new.tm_mday < 1)
 591                 goto rtc_badness;
 592             /* TODO check range */
 593             tm.tm_mday = s->rtc.new.tm_mday;
 594             break;
 595         case 5:
 596             if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
 597                 goto rtc_badness;
 598             tm.tm_mon = s->rtc.new.tm_mon;
 599             break;
 600         case 6:
 601             tm.tm_year = s->rtc.new.tm_year;
 602             break;
 603         case 7:
 604             /* TODO set .tm_mday instead */
 605             tm.tm_wday = s->rtc.new.tm_wday;
 606             break;
 607         case 8:
 608             if (s->rtc.new.tm_hour > 23)
 609                 goto rtc_badness;
 610             if (s->rtc.new.tm_mday < 1)
 611                 goto rtc_badness;
 612             if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
 613                 goto rtc_badness;
 614             tm.tm_sec = s->rtc.new.tm_sec;
 615             tm.tm_min = s->rtc.new.tm_min;
 616             tm.tm_hour = s->rtc.new.tm_hour;
 617             tm.tm_mday = s->rtc.new.tm_mday;
 618             tm.tm_mon = s->rtc.new.tm_mon;
 619             tm.tm_year = s->rtc.new.tm_year;
 620             break;
 621         rtc_badness:
 622         default:
 623             fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
 624                             __FUNCTION__, value);
 625             s->status |= 1 << 10;                               /* RTCERR */
 626             menelaus_update(s);
 627         }
 628         s->rtc.sec_offset = qemu_timedate_diff(&tm);
 629         break;
 630     case MENELAUS_RTC_SEC:
 631         s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
 632         break;
 633     case MENELAUS_RTC_MIN:
 634         s->rtc.tm.tm_min = from_bcd(value & 0x7f);
 635         break;
 636     case MENELAUS_RTC_HR:
 637         s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ?  /* MODE12_n24 */
 638                 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
 639                 from_bcd(value & 0x3f);
 640         break;
 641     case MENELAUS_RTC_DAY:
 642         s->rtc.tm.tm_mday = from_bcd(value);
 643         break;
 644     case MENELAUS_RTC_MON:
 645         s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
 646         break;
 647     case MENELAUS_RTC_YR:
 648         s->rtc.tm.tm_year = 2000 + from_bcd(value);
 649         break;
 650     case MENELAUS_RTC_WKDAY:
 651         s->rtc.tm.tm_mday = from_bcd(value);
 652         break;
 653     case MENELAUS_RTC_AL_SEC:
 654         s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
 655         menelaus_alm_update(s);
 656         break;
 657     case MENELAUS_RTC_AL_MIN:
 658         s->rtc.alm.tm_min = from_bcd(value & 0x7f);
 659         menelaus_alm_update(s);
 660         break;
 661     case MENELAUS_RTC_AL_HR:
 662         s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
 663                 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
 664                 from_bcd(value & 0x3f);
 665         menelaus_alm_update(s);
 666         break;
 667     case MENELAUS_RTC_AL_DAY:
 668         s->rtc.alm.tm_mday = from_bcd(value);
 669         menelaus_alm_update(s);
 670         break;
 671     case MENELAUS_RTC_AL_MON:
 672         s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
 673         menelaus_alm_update(s);
 674         break;
 675     case MENELAUS_RTC_AL_YR:
 676         s->rtc.alm.tm_year = 2000 + from_bcd(value);
 677         menelaus_alm_update(s);
 678         break;
 679     case MENELAUS_RTC_COMP_MSB:
 680         s->rtc.comp &= 0xff;
 681         s->rtc.comp |= value << 8;
 682         break;
 683     case MENELAUS_RTC_COMP_LSB:
 684         s->rtc.comp &= 0xff << 8;
 685         s->rtc.comp |= value;
 686         break;
 687
 688     case MENELAUS_S1_PULL_EN:
 689         s->pull[0] = value;
 690         break;
 691     case MENELAUS_S1_PULL_DIR:
 692         s->pull[1] = value & 0x1f;
 693         break;
 694     case MENELAUS_S2_PULL_EN:
 695         s->pull[2] = value;
 696         break;
 697     case MENELAUS_S2_PULL_DIR:
 698         s->pull[3] = value & 0x1f;
 699         break;
 700
 701     case MENELAUS_MCT_CTRL1:
 702         s->mmc_ctrl[0] = value & 0x7f;
 703         break;
 704     case MENELAUS_MCT_CTRL2:
 705         s->mmc_ctrl[1] = value;
 706         /* TODO update Card Detect interrupts */
 707         break;
 708     case MENELAUS_MCT_CTRL3:
 709         s->mmc_ctrl[2] = value & 0xf;
 710         break;
 711     case MENELAUS_DEBOUNCE1:
 712         s->mmc_debounce = value & 0x3f;
 713         break;
 714
 715     default:
 716 #ifdef VERBOSE
 717         printf("%s: unknown register %02x\n", __FUNCTION__, addr);
 718 #endif
 719     }
 720 }
 721
 722 static void menelaus_event(i2c_slave *i2c, enum i2c_event event)
 723 {
 724     MenelausState *s = (MenelausState *) i2c;
 725
 726     if (event == I2C_START_SEND)
 727         s->firstbyte = 1;
 728 }
 729
 730 static int menelaus_tx(i2c_slave *i2c, uint8_t data)
 731 {
 732     MenelausState *s = (MenelausState *) i2c;
 733     /* Interpret register address byte */
 734     if (s->firstbyte) {
 735         s->reg = data;
 736         s->firstbyte = 0;
 737     } else
 738         menelaus_write(s, s->reg ++, data);
 739
 740     return 0;
 741 }
 742
 743 static int menelaus_rx(i2c_slave *i2c)
 744 {
 745     MenelausState *s = (MenelausState *) i2c;
 746
 747     return menelaus_read(s, s->reg ++);
 748 }
 749
 750 static void tm_put(QEMUFile *f, struct tm *tm) {
 751     qemu_put_be16(f, tm->tm_sec);
 752     qemu_put_be16(f, tm->tm_min);
 753     qemu_put_be16(f, tm->tm_hour);
 754     qemu_put_be16(f, tm->tm_mday);
 755     qemu_put_be16(f, tm->tm_min);
 756     qemu_put_be16(f, tm->tm_year);
 757 }
 758
 759 static void tm_get(QEMUFile *f, struct tm *tm) {
 760     tm->tm_sec = qemu_get_be16(f);
 761     tm->tm_min = qemu_get_be16(f);
 762     tm->tm_hour = qemu_get_be16(f);
 763     tm->tm_mday = qemu_get_be16(f);
 764     tm->tm_min = qemu_get_be16(f);
 765     tm->tm_year = qemu_get_be16(f);
 766 }
 767
 768 static void menelaus_save(QEMUFile *f, void *opaque)
 769 {
 770     MenelausState *s = (MenelausState *) opaque;
 771
 772     qemu_put_be32(f, s->firstbyte);
 773     qemu_put_8s(f, &s->reg);
 774
 775     qemu_put_8s(f, &s->vcore[0]);
 776     qemu_put_8s(f, &s->vcore[1]);
 777     qemu_put_8s(f, &s->vcore[2]);
 778     qemu_put_8s(f, &s->vcore[3]);
 779     qemu_put_8s(f, &s->vcore[4]);
 780     qemu_put_8s(f, &s->dcdc[0]);
 781     qemu_put_8s(f, &s->dcdc[1]);
 782     qemu_put_8s(f, &s->dcdc[2]);
 783     qemu_put_8s(f, &s->ldo[0]);
 784     qemu_put_8s(f, &s->ldo[1]);
 785     qemu_put_8s(f, &s->ldo[2]);
 786     qemu_put_8s(f, &s->ldo[3]);
 787     qemu_put_8s(f, &s->ldo[4]);
 788     qemu_put_8s(f, &s->ldo[5]);
 789     qemu_put_8s(f, &s->ldo[6]);
 790     qemu_put_8s(f, &s->ldo[7]);
 791     qemu_put_8s(f, &s->sleep[0]);
 792     qemu_put_8s(f, &s->sleep[1]);
 793     qemu_put_8s(f, &s->osc);
 794     qemu_put_8s(f, &s->detect);
 795     qemu_put_be16s(f, &s->mask);
 796     qemu_put_be16s(f, &s->status);
 797     qemu_put_8s(f, &s->dir);
 798     qemu_put_8s(f, &s->inputs);
 799     qemu_put_8s(f, &s->outputs);
 800     qemu_put_8s(f, &s->bbsms);
 801     qemu_put_8s(f, &s->pull[0]);
 802     qemu_put_8s(f, &s->pull[1]);
 803     qemu_put_8s(f, &s->pull[2]);
 804     qemu_put_8s(f, &s->pull[3]);
 805     qemu_put_8s(f, &s->mmc_ctrl[0]);
 806     qemu_put_8s(f, &s->mmc_ctrl[1]);
 807     qemu_put_8s(f, &s->mmc_ctrl[2]);
 808     qemu_put_8s(f, &s->mmc_debounce);
 809     qemu_put_8s(f, &s->rtc.ctrl);
 810     qemu_put_be16s(f, &s->rtc.comp);
 811     /* Should be <= 1000 */
 812     qemu_put_be16(f, s->rtc.next - qemu_get_clock(rt_clock));
 813     tm_put(f, &s->rtc.new);
 814     tm_put(f, &s->rtc.alm);
 815     qemu_put_byte(f, s->pwrbtn_state);
 816
 817     i2c_slave_save(f, &s->i2c);
 818 }
 819
 820 static int menelaus_load(QEMUFile *f, void *opaque, int version_id)
 821 {
 822     MenelausState *s = (MenelausState *) opaque;
 823
 824     s->firstbyte = qemu_get_be32(f);
 825     qemu_get_8s(f, &s->reg);
 826
 827     if (s->rtc.ctrl & 1)                                        /* RTC_EN */
 828         menelaus_rtc_stop(s);
 829     qemu_get_8s(f, &s->vcore[0]);
 830     qemu_get_8s(f, &s->vcore[1]);
 831     qemu_get_8s(f, &s->vcore[2]);
 832     qemu_get_8s(f, &s->vcore[3]);
 833     qemu_get_8s(f, &s->vcore[4]);
 834     qemu_get_8s(f, &s->dcdc[0]);
 835     qemu_get_8s(f, &s->dcdc[1]);
 836     qemu_get_8s(f, &s->dcdc[2]);
 837     qemu_get_8s(f, &s->ldo[0]);
 838     qemu_get_8s(f, &s->ldo[1]);
 839     qemu_get_8s(f, &s->ldo[2]);
 840     qemu_get_8s(f, &s->ldo[3]);
 841     qemu_get_8s(f, &s->ldo[4]);
 842     qemu_get_8s(f, &s->ldo[5]);
 843     qemu_get_8s(f, &s->ldo[6]);
 844     qemu_get_8s(f, &s->ldo[7]);
 845     qemu_get_8s(f, &s->sleep[0]);
 846     qemu_get_8s(f, &s->sleep[1]);
 847     qemu_get_8s(f, &s->osc);
 848     qemu_get_8s(f, &s->detect);
 849     qemu_get_be16s(f, &s->mask);
 850     qemu_get_be16s(f, &s->status);
 851     qemu_get_8s(f, &s->dir);
 852     qemu_get_8s(f, &s->inputs);
 853     qemu_get_8s(f, &s->outputs);
 854     qemu_get_8s(f, &s->bbsms);
 855     qemu_get_8s(f, &s->pull[0]);
 856     qemu_get_8s(f, &s->pull[1]);
 857     qemu_get_8s(f, &s->pull[2]);
 858     qemu_get_8s(f, &s->pull[3]);
 859     qemu_get_8s(f, &s->mmc_ctrl[0]);
 860     qemu_get_8s(f, &s->mmc_ctrl[1]);
 861     qemu_get_8s(f, &s->mmc_ctrl[2]);
 862     qemu_get_8s(f, &s->mmc_debounce);
 863     qemu_get_8s(f, &s->rtc.ctrl);
 864     qemu_get_be16s(f, &s->rtc.comp);
 865     s->rtc.next = qemu_get_be16(f);
 866     tm_get(f, &s->rtc.new);
 867     tm_get(f, &s->rtc.alm);
 868     s->pwrbtn_state = qemu_get_byte(f);
 869     menelaus_alm_update(s);
 870     menelaus_update(s);
 871     if (s->rtc.ctrl & 1)                                        /* RTC_EN */
 872         menelaus_rtc_start(s);
 873
 874     i2c_slave_load(f, &s->i2c);
 875     return 0;
 876 }
 877
 878 static void twl92230_init(i2c_slave *i2c)
 879 {
 880     MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c);
 881
 882     s->rtc.hz_tm = qemu_new_timer(rt_clock, menelaus_rtc_hz, s);
 883     /* Three output pins plus one interrupt pin.  */
 884     qdev_init_gpio_out(&i2c->qdev, s->out, 4);
 885     qdev_init_gpio_in(&i2c->qdev, menelaus_gpio_set, 3);
 886     s->pwrbtn = qemu_allocate_irqs(menelaus_pwrbtn_set, s, 1)[0];
 887
 888     menelaus_reset(&s->i2c);
 889
 890     register_savevm("menelaus", -1, 0, menelaus_save, menelaus_load, s);
 891 }
 892
 893 static I2CSlaveInfo twl92230_info = {
 894     .qdev.name ="twl92230",
 895     .qdev.size = sizeof(MenelausState),
 896     .init = twl92230_init,
 897     .event = menelaus_event,
 898     .recv = menelaus_rx,
 899     .send = menelaus_tx
 900 };
 901
 902 static void twl92230_register_devices(void)
 903 {
 904     i2c_register_slave(&twl92230_info);
 905 }
 906
 907 device_init(twl92230_register_devices)