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Disable preadv/pwritev support
[qemu-kvm/fedora.git] / hw / vga.c
blobec7a7c3a5dd78b5a9ad239a76926fceee862a2f8
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "console.h"
26 #include "pc.h"
27 #include "pci.h"
28 #include "vga_int.h"
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
31 #include "kvm.h"
32 #include "qemu-kvm.h"
33
34 //#define DEBUG_VGA
35 //#define DEBUG_VGA_MEM
36 //#define DEBUG_VGA_REG
37
38 //#define DEBUG_BOCHS_VBE
39
40 /* force some bits to zero */
41 const uint8_t sr_mask[8] = {
42 0x03,
43 0x3d,
44 0x0f,
45 0x3f,
46 0x0e,
47 0x00,
48 0x00,
49 0xff,
50 };
51
52 const uint8_t gr_mask[16] = {
53 0x0f, /* 0x00 */
54 0x0f, /* 0x01 */
55 0x0f, /* 0x02 */
56 0x1f, /* 0x03 */
57 0x03, /* 0x04 */
58 0x7b, /* 0x05 */
59 0x0f, /* 0x06 */
60 0x0f, /* 0x07 */
61 0xff, /* 0x08 */
62 0x00, /* 0x09 */
63 0x00, /* 0x0a */
64 0x00, /* 0x0b */
65 0x00, /* 0x0c */
66 0x00, /* 0x0d */
67 0x00, /* 0x0e */
68 0x00, /* 0x0f */
69 };
70
71 #define cbswap_32(__x) \
72 ((uint32_t)( \
73 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
74 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
75 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
76 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
77
78 #ifdef WORDS_BIGENDIAN
79 #define PAT(x) cbswap_32(x)
80 #else
81 #define PAT(x) (x)
82 #endif
83
84 #ifdef WORDS_BIGENDIAN
85 #define BIG 1
86 #else
87 #define BIG 0
88 #endif
89
90 #ifdef WORDS_BIGENDIAN
91 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
92 #else
93 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
94 #endif
95
96 static const uint32_t mask16[16] = {
97 PAT(0x00000000),
98 PAT(0x000000ff),
99 PAT(0x0000ff00),
100 PAT(0x0000ffff),
101 PAT(0x00ff0000),
102 PAT(0x00ff00ff),
103 PAT(0x00ffff00),
104 PAT(0x00ffffff),
105 PAT(0xff000000),
106 PAT(0xff0000ff),
107 PAT(0xff00ff00),
108 PAT(0xff00ffff),
109 PAT(0xffff0000),
110 PAT(0xffff00ff),
111 PAT(0xffffff00),
112 PAT(0xffffffff),
113 };
114
115 #undef PAT
116
117 #ifdef WORDS_BIGENDIAN
118 #define PAT(x) (x)
119 #else
120 #define PAT(x) cbswap_32(x)
121 #endif
122
123 static const uint32_t dmask16[16] = {
124 PAT(0x00000000),
125 PAT(0x000000ff),
126 PAT(0x0000ff00),
127 PAT(0x0000ffff),
128 PAT(0x00ff0000),
129 PAT(0x00ff00ff),
130 PAT(0x00ffff00),
131 PAT(0x00ffffff),
132 PAT(0xff000000),
133 PAT(0xff0000ff),
134 PAT(0xff00ff00),
135 PAT(0xff00ffff),
136 PAT(0xffff0000),
137 PAT(0xffff00ff),
138 PAT(0xffffff00),
139 PAT(0xffffffff),
140 };
141
142 static const uint32_t dmask4[4] = {
143 PAT(0x00000000),
144 PAT(0x0000ffff),
145 PAT(0xffff0000),
146 PAT(0xffffffff),
147 };
148
149 static uint32_t expand4[256];
150 static uint16_t expand2[256];
151 static uint8_t expand4to8[16];
152
153 static void vga_screen_dump(void *opaque, const char *filename);
154 static char *screen_dump_filename;
155 static DisplayChangeListener *screen_dump_dcl;
156
157 static void vga_dumb_update_retrace_info(VGAState *s)
158 {
159 (void) s;
160 }
161
162 static void vga_precise_update_retrace_info(VGAState *s)
163 {
164 int htotal_chars;
165 int hretr_start_char;
166 int hretr_skew_chars;
167 int hretr_end_char;
168
169 int vtotal_lines;
170 int vretr_start_line;
171 int vretr_end_line;
172
173 int div2, sldiv2, dots;
174 int clocking_mode;
175 int clock_sel;
176 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
177 int64_t chars_per_sec;
178 struct vga_precise_retrace *r = &s->retrace_info.precise;
179
180 htotal_chars = s->cr[0x00] + 5;
181 hretr_start_char = s->cr[0x04];
182 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
183 hretr_end_char = s->cr[0x05] & 0x1f;
184
185 vtotal_lines = (s->cr[0x06]
186 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
187 ;
188 vretr_start_line = s->cr[0x10]
189 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
190 ;
191 vretr_end_line = s->cr[0x11] & 0xf;
192
193
194 div2 = (s->cr[0x17] >> 2) & 1;
195 sldiv2 = (s->cr[0x17] >> 3) & 1;
196
197 clocking_mode = (s->sr[0x01] >> 3) & 1;
198 clock_sel = (s->msr >> 2) & 3;
199 dots = (s->msr & 1) ? 8 : 9;
200
201 chars_per_sec = clk_hz[clock_sel] / dots;
202
203 htotal_chars <<= clocking_mode;
204
205 r->total_chars = vtotal_lines * htotal_chars;
206 if (r->freq) {
207 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
208 } else {
209 r->ticks_per_char = ticks_per_sec / chars_per_sec;
210 }
211
212 r->vstart = vretr_start_line;
213 r->vend = r->vstart + vretr_end_line + 1;
214
215 r->hstart = hretr_start_char + hretr_skew_chars;
216 r->hend = r->hstart + hretr_end_char + 1;
217 r->htotal = htotal_chars;
218
219 #if 0
220 printf (
221 "hz=%f\n"
222 "htotal = %d\n"
223 "hretr_start = %d\n"
224 "hretr_skew = %d\n"
225 "hretr_end = %d\n"
226 "vtotal = %d\n"
227 "vretr_start = %d\n"
228 "vretr_end = %d\n"
229 "div2 = %d sldiv2 = %d\n"
230 "clocking_mode = %d\n"
231 "clock_sel = %d %d\n"
232 "dots = %d\n"
233 "ticks/char = %lld\n"
234 "\n",
235 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
236 htotal_chars,
237 hretr_start_char,
238 hretr_skew_chars,
239 hretr_end_char,
240 vtotal_lines,
241 vretr_start_line,
242 vretr_end_line,
243 div2, sldiv2,
244 clocking_mode,
245 clock_sel,
246 clk_hz[clock_sel],
247 dots,
248 r->ticks_per_char
249 );
250 #endif
251 }
252
253 static uint8_t vga_precise_retrace(VGAState *s)
254 {
255 struct vga_precise_retrace *r = &s->retrace_info.precise;
256 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
257
258 if (r->total_chars) {
259 int cur_line, cur_line_char, cur_char;
260 int64_t cur_tick;
261
262 cur_tick = qemu_get_clock(vm_clock);
263
264 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
265 cur_line = cur_char / r->htotal;
266
267 if (cur_line >= r->vstart && cur_line <= r->vend) {
268 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
269 } else {
270 cur_line_char = cur_char % r->htotal;
271 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
272 val |= ST01_DISP_ENABLE;
273 }
274 }
275
276 return val;
277 } else {
278 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
279 }
280 }
281
282 static uint8_t vga_dumb_retrace(VGAState *s)
283 {
284 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
285 }
286
287 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
288 {
289 VGAState *s = opaque;
290 int val, index;
291
292 /* check port range access depending on color/monochrome mode */
293 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
294 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
295 val = 0xff;
296 } else {
297 switch(addr) {
298 case 0x3c0:
299 if (s->ar_flip_flop == 0) {
300 val = s->ar_index;
301 } else {
302 val = 0;
303 }
304 break;
305 case 0x3c1:
306 index = s->ar_index & 0x1f;
307 if (index < 21)
308 val = s->ar[index];
309 else
310 val = 0;
311 break;
312 case 0x3c2:
313 val = s->st00;
314 break;
315 case 0x3c4:
316 val = s->sr_index;
317 break;
318 case 0x3c5:
319 val = s->sr[s->sr_index];
320 #ifdef DEBUG_VGA_REG
321 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
322 #endif
323 break;
324 case 0x3c7:
325 val = s->dac_state;
326 break;
327 case 0x3c8:
328 val = s->dac_write_index;
329 break;
330 case 0x3c9:
331 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
332 if (++s->dac_sub_index == 3) {
333 s->dac_sub_index = 0;
334 s->dac_read_index++;
335 }
336 break;
337 case 0x3ca:
338 val = s->fcr;
339 break;
340 case 0x3cc:
341 val = s->msr;
342 break;
343 case 0x3ce:
344 val = s->gr_index;
345 break;
346 case 0x3cf:
347 val = s->gr[s->gr_index];
348 #ifdef DEBUG_VGA_REG
349 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
350 #endif
351 break;
352 case 0x3b4:
353 case 0x3d4:
354 val = s->cr_index;
355 break;
356 case 0x3b5:
357 case 0x3d5:
358 val = s->cr[s->cr_index];
359 #ifdef DEBUG_VGA_REG
360 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
361 #endif
362 break;
363 case 0x3ba:
364 case 0x3da:
365 /* just toggle to fool polling */
366 val = s->st01 = s->retrace(s);
367 s->ar_flip_flop = 0;
368 break;
369 default:
370 val = 0x00;
371 break;
372 }
373 }
374 #if defined(DEBUG_VGA)
375 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
376 #endif
377 return val;
378 }
379
380 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
381 {
382 VGAState *s = opaque;
383 int index;
384
385 /* check port range access depending on color/monochrome mode */
386 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
387 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
388 return;
389
390 #ifdef DEBUG_VGA
391 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
392 #endif
393
394 switch(addr) {
395 case 0x3c0:
396 if (s->ar_flip_flop == 0) {
397 val &= 0x3f;
398 s->ar_index = val;
399 } else {
400 index = s->ar_index & 0x1f;
401 switch(index) {
402 case 0x00 ... 0x0f:
403 s->ar[index] = val & 0x3f;
404 break;
405 case 0x10:
406 s->ar[index] = val & ~0x10;
407 break;
408 case 0x11:
409 s->ar[index] = val;
410 break;
411 case 0x12:
412 s->ar[index] = val & ~0xc0;
413 break;
414 case 0x13:
415 s->ar[index] = val & ~0xf0;
416 break;
417 case 0x14:
418 s->ar[index] = val & ~0xf0;
419 break;
420 default:
421 break;
422 }
423 }
424 s->ar_flip_flop ^= 1;
425 break;
426 case 0x3c2:
427 s->msr = val & ~0x10;
428 s->update_retrace_info(s);
429 break;
430 case 0x3c4:
431 s->sr_index = val & 7;
432 break;
433 case 0x3c5:
434 #ifdef DEBUG_VGA_REG
435 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
436 #endif
437 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
438 if (s->sr_index == 1) s->update_retrace_info(s);
439 break;
440 case 0x3c7:
441 s->dac_read_index = val;
442 s->dac_sub_index = 0;
443 s->dac_state = 3;
444 break;
445 case 0x3c8:
446 s->dac_write_index = val;
447 s->dac_sub_index = 0;
448 s->dac_state = 0;
449 break;
450 case 0x3c9:
451 s->dac_cache[s->dac_sub_index] = val;
452 if (++s->dac_sub_index == 3) {
453 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
454 s->dac_sub_index = 0;
455 s->dac_write_index++;
456 }
457 break;
458 case 0x3ce:
459 s->gr_index = val & 0x0f;
460 break;
461 case 0x3cf:
462 #ifdef DEBUG_VGA_REG
463 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
464 #endif
465 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
466 break;
467 case 0x3b4:
468 case 0x3d4:
469 s->cr_index = val;
470 break;
471 case 0x3b5:
472 case 0x3d5:
473 #ifdef DEBUG_VGA_REG
474 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
475 #endif
476 /* handle CR0-7 protection */
477 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
478 /* can always write bit 4 of CR7 */
479 if (s->cr_index == 7)
480 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
481 return;
482 }
483 switch(s->cr_index) {
484 case 0x01: /* horizontal display end */
485 case 0x07:
486 case 0x09:
487 case 0x0c:
488 case 0x0d:
489 case 0x12: /* vertical display end */
490 s->cr[s->cr_index] = val;
491 break;
492 default:
493 s->cr[s->cr_index] = val;
494 break;
495 }
496
497 switch(s->cr_index) {
498 case 0x00:
499 case 0x04:
500 case 0x05:
501 case 0x06:
502 case 0x07:
503 case 0x11:
504 case 0x17:
505 s->update_retrace_info(s);
506 break;
507 }
508 break;
509 case 0x3ba:
510 case 0x3da:
511 s->fcr = val & 0x10;
512 break;
513 }
514 }
515
516 #ifdef CONFIG_BOCHS_VBE
517 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
518 {
519 VGAState *s = opaque;
520 uint32_t val;
521 val = s->vbe_index;
522 return val;
523 }
524
525 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
526 {
527 VGAState *s = opaque;
528 uint32_t val;
529
530 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
531 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
532 switch(s->vbe_index) {
533 /* XXX: do not hardcode ? */
534 case VBE_DISPI_INDEX_XRES:
535 val = VBE_DISPI_MAX_XRES;
536 break;
537 case VBE_DISPI_INDEX_YRES:
538 val = VBE_DISPI_MAX_YRES;
539 break;
540 case VBE_DISPI_INDEX_BPP:
541 val = VBE_DISPI_MAX_BPP;
542 break;
543 default:
544 val = s->vbe_regs[s->vbe_index];
545 break;
546 }
547 } else {
548 val = s->vbe_regs[s->vbe_index];
549 }
550 } else {
551 val = 0;
552 }
553 #ifdef DEBUG_BOCHS_VBE
554 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
555 #endif
556 return val;
557 }
558
559 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
560 {
561 VGAState *s = opaque;
562 s->vbe_index = val;
563 }
564
565 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
566 {
567 VGAState *s = opaque;
568
569 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
570 #ifdef DEBUG_BOCHS_VBE
571 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
572 #endif
573 switch(s->vbe_index) {
574 case VBE_DISPI_INDEX_ID:
575 if (val == VBE_DISPI_ID0 ||
576 val == VBE_DISPI_ID1 ||
577 val == VBE_DISPI_ID2 ||
578 val == VBE_DISPI_ID3 ||
579 val == VBE_DISPI_ID4) {
580 s->vbe_regs[s->vbe_index] = val;
581 }
582 break;
583 case VBE_DISPI_INDEX_XRES:
584 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
585 s->vbe_regs[s->vbe_index] = val;
586 }
587 break;
588 case VBE_DISPI_INDEX_YRES:
589 if (val <= VBE_DISPI_MAX_YRES) {
590 s->vbe_regs[s->vbe_index] = val;
591 }
592 break;
593 case VBE_DISPI_INDEX_BPP:
594 if (val == 0)
595 val = 8;
596 if (val == 4 || val == 8 || val == 15 ||
597 val == 16 || val == 24 || val == 32) {
598 s->vbe_regs[s->vbe_index] = val;
599 }
600 break;
601 case VBE_DISPI_INDEX_BANK:
602 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
603 val &= (s->vbe_bank_mask >> 2);
604 } else {
605 val &= s->vbe_bank_mask;
606 }
607 s->vbe_regs[s->vbe_index] = val;
608 s->bank_offset = (val << 16);
609 break;
610 case VBE_DISPI_INDEX_ENABLE:
611 if ((val & VBE_DISPI_ENABLED) &&
612 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
613 int h, shift_control;
614
615 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
616 s->vbe_regs[VBE_DISPI_INDEX_XRES];
617 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
618 s->vbe_regs[VBE_DISPI_INDEX_YRES];
619 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
620 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
621
622 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
623 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
624 else
625 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
626 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
627 s->vbe_start_addr = 0;
628
629 /* clear the screen (should be done in BIOS) */
630 if (!(val & VBE_DISPI_NOCLEARMEM)) {
631 memset(s->vram_ptr, 0,
632 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
633 }
634
635 /* we initialize the VGA graphic mode (should be done
636 in BIOS) */
637 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
638 s->cr[0x17] |= 3; /* no CGA modes */
639 s->cr[0x13] = s->vbe_line_offset >> 3;
640 /* width */
641 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
642 /* height (only meaningful if < 1024) */
643 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
644 s->cr[0x12] = h;
645 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
646 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
647 /* line compare to 1023 */
648 s->cr[0x18] = 0xff;
649 s->cr[0x07] |= 0x10;
650 s->cr[0x09] |= 0x40;
651
652 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
653 shift_control = 0;
654 s->sr[0x01] &= ~8; /* no double line */
655 } else {
656 shift_control = 2;
657 s->sr[4] |= 0x08; /* set chain 4 mode */
658 s->sr[2] |= 0x0f; /* activate all planes */
659 }
660 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
661 s->cr[0x09] &= ~0x9f; /* no double scan */
662 } else {
663 /* XXX: the bios should do that */
664 s->bank_offset = 0;
665 }
666 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
667 s->vbe_regs[s->vbe_index] = val;
668 break;
669 case VBE_DISPI_INDEX_VIRT_WIDTH:
670 {
671 int w, h, line_offset;
672
673 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
674 return;
675 w = val;
676 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
677 line_offset = w >> 1;
678 else
679 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
680 h = s->vram_size / line_offset;
681 /* XXX: support weird bochs semantics ? */
682 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
683 return;
684 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
685 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
686 s->vbe_line_offset = line_offset;
687 }
688 break;
689 case VBE_DISPI_INDEX_X_OFFSET:
690 case VBE_DISPI_INDEX_Y_OFFSET:
691 {
692 int x;
693 s->vbe_regs[s->vbe_index] = val;
694 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
695 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
696 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
697 s->vbe_start_addr += x >> 1;
698 else
699 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
700 s->vbe_start_addr >>= 2;
701 }
702 break;
703 default:
704 break;
705 }
706 }
707 }
708 #endif
709
710 /* called for accesses between 0xa0000 and 0xc0000 */
711 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
712 {
713 VGAState *s = opaque;
714 int memory_map_mode, plane;
715 uint32_t ret;
716
717 /* convert to VGA memory offset */
718 memory_map_mode = (s->gr[6] >> 2) & 3;
719 addr &= 0x1ffff;
720 switch(memory_map_mode) {
721 case 0:
722 break;
723 case 1:
724 if (addr >= 0x10000)
725 return 0xff;
726 addr += s->bank_offset;
727 break;
728 case 2:
729 addr -= 0x10000;
730 if (addr >= 0x8000)
731 return 0xff;
732 break;
733 default:
734 case 3:
735 addr -= 0x18000;
736 if (addr >= 0x8000)
737 return 0xff;
738 break;
739 }
740
741 if (s->sr[4] & 0x08) {
742 /* chain 4 mode : simplest access */
743 ret = s->vram_ptr[addr];
744 } else if (s->gr[5] & 0x10) {
745 /* odd/even mode (aka text mode mapping) */
746 plane = (s->gr[4] & 2) | (addr & 1);
747 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
748 } else {
749 /* standard VGA latched access */
750 s->latch = ((uint32_t *)s->vram_ptr)[addr];
751
752 if (!(s->gr[5] & 0x08)) {
753 /* read mode 0 */
754 plane = s->gr[4];
755 ret = GET_PLANE(s->latch, plane);
756 } else {
757 /* read mode 1 */
758 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
759 ret |= ret >> 16;
760 ret |= ret >> 8;
761 ret = (~ret) & 0xff;
762 }
763 }
764 return ret;
765 }
766
767 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
768 {
769 uint32_t v;
770 #ifdef TARGET_WORDS_BIGENDIAN
771 v = vga_mem_readb(opaque, addr) << 8;
772 v |= vga_mem_readb(opaque, addr + 1);
773 #else
774 v = vga_mem_readb(opaque, addr);
775 v |= vga_mem_readb(opaque, addr + 1) << 8;
776 #endif
777 return v;
778 }
779
780 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
781 {
782 uint32_t v;
783 #ifdef TARGET_WORDS_BIGENDIAN
784 v = vga_mem_readb(opaque, addr) << 24;
785 v |= vga_mem_readb(opaque, addr + 1) << 16;
786 v |= vga_mem_readb(opaque, addr + 2) << 8;
787 v |= vga_mem_readb(opaque, addr + 3);
788 #else
789 v = vga_mem_readb(opaque, addr);
790 v |= vga_mem_readb(opaque, addr + 1) << 8;
791 v |= vga_mem_readb(opaque, addr + 2) << 16;
792 v |= vga_mem_readb(opaque, addr + 3) << 24;
793 #endif
794 return v;
795 }
796
797 /* called for accesses between 0xa0000 and 0xc0000 */
798 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
799 {
800 VGAState *s = opaque;
801 int memory_map_mode, plane, write_mode, b, func_select, mask;
802 uint32_t write_mask, bit_mask, set_mask;
803
804 #ifdef DEBUG_VGA_MEM
805 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
806 #endif
807 /* convert to VGA memory offset */
808 memory_map_mode = (s->gr[6] >> 2) & 3;
809 addr &= 0x1ffff;
810 switch(memory_map_mode) {
811 case 0:
812 break;
813 case 1:
814 if (addr >= 0x10000)
815 return;
816 addr += s->bank_offset;
817 break;
818 case 2:
819 addr -= 0x10000;
820 if (addr >= 0x8000)
821 return;
822 break;
823 default:
824 case 3:
825 addr -= 0x18000;
826 if (addr >= 0x8000)
827 return;
828 break;
829 }
830
831 if (s->sr[4] & 0x08) {
832 /* chain 4 mode : simplest access */
833 plane = addr & 3;
834 mask = (1 << plane);
835 if (s->sr[2] & mask) {
836 s->vram_ptr[addr] = val;
837 #ifdef DEBUG_VGA_MEM
838 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
839 #endif
840 s->plane_updated |= mask; /* only used to detect font change */
841 cpu_physical_memory_set_dirty(s->vram_offset + addr);
842 }
843 } else if (s->gr[5] & 0x10) {
844 /* odd/even mode (aka text mode mapping) */
845 plane = (s->gr[4] & 2) | (addr & 1);
846 mask = (1 << plane);
847 if (s->sr[2] & mask) {
848 addr = ((addr & ~1) << 1) | plane;
849 s->vram_ptr[addr] = val;
850 #ifdef DEBUG_VGA_MEM
851 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
852 #endif
853 s->plane_updated |= mask; /* only used to detect font change */
854 cpu_physical_memory_set_dirty(s->vram_offset + addr);
855 }
856 } else {
857 /* standard VGA latched access */
858 write_mode = s->gr[5] & 3;
859 switch(write_mode) {
860 default:
861 case 0:
862 /* rotate */
863 b = s->gr[3] & 7;
864 val = ((val >> b) | (val << (8 - b))) & 0xff;
865 val |= val << 8;
866 val |= val << 16;
867
868 /* apply set/reset mask */
869 set_mask = mask16[s->gr[1]];
870 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
871 bit_mask = s->gr[8];
872 break;
873 case 1:
874 val = s->latch;
875 goto do_write;
876 case 2:
877 val = mask16[val & 0x0f];
878 bit_mask = s->gr[8];
879 break;
880 case 3:
881 /* rotate */
882 b = s->gr[3] & 7;
883 val = (val >> b) | (val << (8 - b));
884
885 bit_mask = s->gr[8] & val;
886 val = mask16[s->gr[0]];
887 break;
888 }
889
890 /* apply logical operation */
891 func_select = s->gr[3] >> 3;
892 switch(func_select) {
893 case 0:
894 default:
895 /* nothing to do */
896 break;
897 case 1:
898 /* and */
899 val &= s->latch;
900 break;
901 case 2:
902 /* or */
903 val |= s->latch;
904 break;
905 case 3:
906 /* xor */
907 val ^= s->latch;
908 break;
909 }
910
911 /* apply bit mask */
912 bit_mask |= bit_mask << 8;
913 bit_mask |= bit_mask << 16;
914 val = (val & bit_mask) | (s->latch & ~bit_mask);
915
916 do_write:
917 /* mask data according to sr[2] */
918 mask = s->sr[2];
919 s->plane_updated |= mask; /* only used to detect font change */
920 write_mask = mask16[mask];
921 ((uint32_t *)s->vram_ptr)[addr] =
922 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
923 (val & write_mask);
924 #ifdef DEBUG_VGA_MEM
925 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
926 addr * 4, write_mask, val);
927 #endif
928 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
929 }
930 }
931
932 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
933 {
934 #ifdef TARGET_WORDS_BIGENDIAN
935 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
936 vga_mem_writeb(opaque, addr + 1, val & 0xff);
937 #else
938 vga_mem_writeb(opaque, addr, val & 0xff);
939 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
940 #endif
941 }
942
943 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
944 {
945 #ifdef TARGET_WORDS_BIGENDIAN
946 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
947 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
948 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
949 vga_mem_writeb(opaque, addr + 3, val & 0xff);
950 #else
951 vga_mem_writeb(opaque, addr, val & 0xff);
952 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
953 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
954 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
955 #endif
956 }
957
958 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
959 const uint8_t *font_ptr, int h,
960 uint32_t fgcol, uint32_t bgcol);
961 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
962 const uint8_t *font_ptr, int h,
963 uint32_t fgcol, uint32_t bgcol, int dup9);
964 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
965 const uint8_t *s, int width);
966
967 #define DEPTH 8
968 #include "vga_template.h"
969
970 #define DEPTH 15
971 #include "vga_template.h"
972
973 #define BGR_FORMAT
974 #define DEPTH 15
975 #include "vga_template.h"
976
977 #define DEPTH 16
978 #include "vga_template.h"
979
980 #define BGR_FORMAT
981 #define DEPTH 16
982 #include "vga_template.h"
983
984 #define DEPTH 32
985 #include "vga_template.h"
986
987 #define BGR_FORMAT
988 #define DEPTH 32
989 #include "vga_template.h"
990
991 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
992 {
993 unsigned int col;
994 col = rgb_to_pixel8(r, g, b);
995 col |= col << 8;
996 col |= col << 16;
997 return col;
998 }
999
1000 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1001 {
1002 unsigned int col;
1003 col = rgb_to_pixel15(r, g, b);
1004 col |= col << 16;
1005 return col;
1006 }
1007
1008 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1009 unsigned int b)
1010 {
1011 unsigned int col;
1012 col = rgb_to_pixel15bgr(r, g, b);
1013 col |= col << 16;
1014 return col;
1015 }
1016
1017 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1018 {
1019 unsigned int col;
1020 col = rgb_to_pixel16(r, g, b);
1021 col |= col << 16;
1022 return col;
1023 }
1024
1025 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1026 unsigned int b)
1027 {
1028 unsigned int col;
1029 col = rgb_to_pixel16bgr(r, g, b);
1030 col |= col << 16;
1031 return col;
1032 }
1033
1034 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1035 {
1036 unsigned int col;
1037 col = rgb_to_pixel32(r, g, b);
1038 return col;
1039 }
1040
1041 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1042 {
1043 unsigned int col;
1044 col = rgb_to_pixel32bgr(r, g, b);
1045 return col;
1046 }
1047
1048 /* return true if the palette was modified */
1049 static int update_palette16(VGAState *s)
1050 {
1051 int full_update, i;
1052 uint32_t v, col, *palette;
1053
1054 full_update = 0;
1055 palette = s->last_palette;
1056 for(i = 0; i < 16; i++) {
1057 v = s->ar[i];
1058 if (s->ar[0x10] & 0x80)
1059 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1060 else
1061 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1062 v = v * 3;
1063 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1064 c6_to_8(s->palette[v + 1]),
1065 c6_to_8(s->palette[v + 2]));
1066 if (col != palette[i]) {
1067 full_update = 1;
1068 palette[i] = col;
1069 }
1070 }
1071 return full_update;
1072 }
1073
1074 /* return true if the palette was modified */
1075 static int update_palette256(VGAState *s)
1076 {
1077 int full_update, i;
1078 uint32_t v, col, *palette;
1079
1080 full_update = 0;
1081 palette = s->last_palette;
1082 v = 0;
1083 for(i = 0; i < 256; i++) {
1084 if (s->dac_8bit) {
1085 col = s->rgb_to_pixel(s->palette[v],
1086 s->palette[v + 1],
1087 s->palette[v + 2]);
1088 } else {
1089 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1090 c6_to_8(s->palette[v + 1]),
1091 c6_to_8(s->palette[v + 2]));
1092 }
1093 if (col != palette[i]) {
1094 full_update = 1;
1095 palette[i] = col;
1096 }
1097 v += 3;
1098 }
1099 return full_update;
1100 }
1101
1102 static void vga_get_offsets(VGAState *s,
1103 uint32_t *pline_offset,
1104 uint32_t *pstart_addr,
1105 uint32_t *pline_compare)
1106 {
1107 uint32_t start_addr, line_offset, line_compare;
1108 #ifdef CONFIG_BOCHS_VBE
1109 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1110 line_offset = s->vbe_line_offset;
1111 start_addr = s->vbe_start_addr;
1112 line_compare = 65535;
1113 } else
1114 #endif
1115 {
1116 /* compute line_offset in bytes */
1117 line_offset = s->cr[0x13];
1118 line_offset <<= 3;
1119
1120 /* starting address */
1121 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1122
1123 /* line compare */
1124 line_compare = s->cr[0x18] |
1125 ((s->cr[0x07] & 0x10) << 4) |
1126 ((s->cr[0x09] & 0x40) << 3);
1127 }
1128 *pline_offset = line_offset;
1129 *pstart_addr = start_addr;
1130 *pline_compare = line_compare;
1131 }
1132
1133 /* update start_addr and line_offset. Return TRUE if modified */
1134 static int update_basic_params(VGAState *s)
1135 {
1136 int full_update;
1137 uint32_t start_addr, line_offset, line_compare;
1138
1139 full_update = 0;
1140
1141 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1142
1143 if (line_offset != s->line_offset ||
1144 start_addr != s->start_addr ||
1145 line_compare != s->line_compare) {
1146 s->line_offset = line_offset;
1147 s->start_addr = start_addr;
1148 s->line_compare = line_compare;
1149 full_update = 1;
1150 }
1151 return full_update;
1152 }
1153
1154 #define NB_DEPTHS 7
1155
1156 static inline int get_depth_index(DisplayState *s)
1157 {
1158 switch(ds_get_bits_per_pixel(s)) {
1159 default:
1160 case 8:
1161 return 0;
1162 case 15:
1163 return 1;
1164 case 16:
1165 return 2;
1166 case 32:
1167 if (is_surface_bgr(s->surface))
1168 return 4;
1169 else
1170 return 3;
1171 }
1172 }
1173
1174 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1175 vga_draw_glyph8_8,
1176 vga_draw_glyph8_16,
1177 vga_draw_glyph8_16,
1178 vga_draw_glyph8_32,
1179 vga_draw_glyph8_32,
1180 vga_draw_glyph8_16,
1181 vga_draw_glyph8_16,
1182 };
1183
1184 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1185 vga_draw_glyph16_8,
1186 vga_draw_glyph16_16,
1187 vga_draw_glyph16_16,
1188 vga_draw_glyph16_32,
1189 vga_draw_glyph16_32,
1190 vga_draw_glyph16_16,
1191 vga_draw_glyph16_16,
1192 };
1193
1194 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1195 vga_draw_glyph9_8,
1196 vga_draw_glyph9_16,
1197 vga_draw_glyph9_16,
1198 vga_draw_glyph9_32,
1199 vga_draw_glyph9_32,
1200 vga_draw_glyph9_16,
1201 vga_draw_glyph9_16,
1202 };
1203
1204 static const uint8_t cursor_glyph[32 * 4] = {
1205 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1206 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1207 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1208 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1217 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1218 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1219 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1220 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1221 };
1222
1223 static void vga_get_text_resolution(VGAState *s, int *pwidth, int *pheight,
1224 int *pcwidth, int *pcheight)
1225 {
1226 int width, cwidth, height, cheight;
1227
1228 /* total width & height */
1229 cheight = (s->cr[9] & 0x1f) + 1;
1230 cwidth = 8;
1231 if (!(s->sr[1] & 0x01))
1232 cwidth = 9;
1233 if (s->sr[1] & 0x08)
1234 cwidth = 16; /* NOTE: no 18 pixel wide */
1235 width = (s->cr[0x01] + 1);
1236 if (s->cr[0x06] == 100) {
1237 /* ugly hack for CGA 160x100x16 - explain me the logic */
1238 height = 100;
1239 } else {
1240 height = s->cr[0x12] |
1241 ((s->cr[0x07] & 0x02) << 7) |
1242 ((s->cr[0x07] & 0x40) << 3);
1243 height = (height + 1) / cheight;
1244 }
1245
1246 *pwidth = width;
1247 *pheight = height;
1248 *pcwidth = cwidth;
1249 *pcheight = cheight;
1250 }
1251
1252 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1253
1254 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1255 rgb_to_pixel8_dup,
1256 rgb_to_pixel15_dup,
1257 rgb_to_pixel16_dup,
1258 rgb_to_pixel32_dup,
1259 rgb_to_pixel32bgr_dup,
1260 rgb_to_pixel15bgr_dup,
1261 rgb_to_pixel16bgr_dup,
1262 };
1263
1264 /*
1265 * Text mode update
1266 * Missing:
1267 * - double scan
1268 * - double width
1269 * - underline
1270 * - flashing
1271 */
1272 static void vga_draw_text(VGAState *s, int full_update)
1273 {
1274 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1275 int cx_min, cx_max, linesize, x_incr;
1276 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1277 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1278 const uint8_t *font_ptr, *font_base[2];
1279 int dup9, line_offset, depth_index;
1280 uint32_t *palette;
1281 uint32_t *ch_attr_ptr;
1282 vga_draw_glyph8_func *vga_draw_glyph8;
1283 vga_draw_glyph9_func *vga_draw_glyph9;
1284
1285 vga_dirty_log_stop(s);
1286
1287 /* compute font data address (in plane 2) */
1288 v = s->sr[3];
1289 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1290 if (offset != s->font_offsets[0]) {
1291 s->font_offsets[0] = offset;
1292 full_update = 1;
1293 }
1294 font_base[0] = s->vram_ptr + offset;
1295
1296 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1297 font_base[1] = s->vram_ptr + offset;
1298 if (offset != s->font_offsets[1]) {
1299 s->font_offsets[1] = offset;
1300 full_update = 1;
1301 }
1302 if (s->plane_updated & (1 << 2)) {
1303 /* if the plane 2 was modified since the last display, it
1304 indicates the font may have been modified */
1305 s->plane_updated = 0;
1306 full_update = 1;
1307 }
1308 full_update |= update_basic_params(s);
1309
1310 line_offset = s->line_offset;
1311 s1 = s->vram_ptr + (s->start_addr * 4);
1312
1313 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1314 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1315 if ((height * width) > CH_ATTR_SIZE) {
1316 /* better than nothing: exit if transient size is too big */
1317 return;
1318 }
1319
1320 if (width != s->last_width || height != s->last_height ||
1321 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1322 s->last_scr_width = width * cw;
1323 s->last_scr_height = height * cheight;
1324 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1325 s->last_depth = 0;
1326 s->last_width = width;
1327 s->last_height = height;
1328 s->last_ch = cheight;
1329 s->last_cw = cw;
1330 full_update = 1;
1331 }
1332 s->rgb_to_pixel =
1333 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1334 full_update |= update_palette16(s);
1335 palette = s->last_palette;
1336 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1337
1338 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1339 if (cursor_offset != s->cursor_offset ||
1340 s->cr[0xa] != s->cursor_start ||
1341 s->cr[0xb] != s->cursor_end) {
1342 /* if the cursor position changed, we update the old and new
1343 chars */
1344 if (s->cursor_offset < CH_ATTR_SIZE)
1345 s->last_ch_attr[s->cursor_offset] = -1;
1346 if (cursor_offset < CH_ATTR_SIZE)
1347 s->last_ch_attr[cursor_offset] = -1;
1348 s->cursor_offset = cursor_offset;
1349 s->cursor_start = s->cr[0xa];
1350 s->cursor_end = s->cr[0xb];
1351 }
1352 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1353
1354 depth_index = get_depth_index(s->ds);
1355 if (cw == 16)
1356 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1357 else
1358 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1359 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1360
1361 dest = ds_get_data(s->ds);
1362 linesize = ds_get_linesize(s->ds);
1363 ch_attr_ptr = s->last_ch_attr;
1364 for(cy = 0; cy < height; cy++) {
1365 d1 = dest;
1366 src = s1;
1367 cx_min = width;
1368 cx_max = -1;
1369 for(cx = 0; cx < width; cx++) {
1370 ch_attr = *(uint16_t *)src;
1371 if (full_update || ch_attr != *ch_attr_ptr) {
1372 if (cx < cx_min)
1373 cx_min = cx;
1374 if (cx > cx_max)
1375 cx_max = cx;
1376 *ch_attr_ptr = ch_attr;
1377 #ifdef WORDS_BIGENDIAN
1378 ch = ch_attr >> 8;
1379 cattr = ch_attr & 0xff;
1380 #else
1381 ch = ch_attr & 0xff;
1382 cattr = ch_attr >> 8;
1383 #endif
1384 font_ptr = font_base[(cattr >> 3) & 1];
1385 font_ptr += 32 * 4 * ch;
1386 bgcol = palette[cattr >> 4];
1387 fgcol = palette[cattr & 0x0f];
1388 if (cw != 9) {
1389 vga_draw_glyph8(d1, linesize,
1390 font_ptr, cheight, fgcol, bgcol);
1391 } else {
1392 dup9 = 0;
1393 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1394 dup9 = 1;
1395 vga_draw_glyph9(d1, linesize,
1396 font_ptr, cheight, fgcol, bgcol, dup9);
1397 }
1398 if (src == cursor_ptr &&
1399 !(s->cr[0x0a] & 0x20)) {
1400 int line_start, line_last, h;
1401 /* draw the cursor */
1402 line_start = s->cr[0x0a] & 0x1f;
1403 line_last = s->cr[0x0b] & 0x1f;
1404 /* XXX: check that */
1405 if (line_last > cheight - 1)
1406 line_last = cheight - 1;
1407 if (line_last >= line_start && line_start < cheight) {
1408 h = line_last - line_start + 1;
1409 d = d1 + linesize * line_start;
1410 if (cw != 9) {
1411 vga_draw_glyph8(d, linesize,
1412 cursor_glyph, h, fgcol, bgcol);
1413 } else {
1414 vga_draw_glyph9(d, linesize,
1415 cursor_glyph, h, fgcol, bgcol, 1);
1416 }
1417 }
1418 }
1419 }
1420 d1 += x_incr;
1421 src += 4;
1422 ch_attr_ptr++;
1423 }
1424 if (cx_max != -1) {
1425 dpy_update(s->ds, cx_min * cw, cy * cheight,
1426 (cx_max - cx_min + 1) * cw, cheight);
1427 }
1428 dest += linesize * cheight;
1429 s1 += line_offset;
1430 }
1431 }
1432
1433 enum {
1434 VGA_DRAW_LINE2,
1435 VGA_DRAW_LINE2D2,
1436 VGA_DRAW_LINE4,
1437 VGA_DRAW_LINE4D2,
1438 VGA_DRAW_LINE8D2,
1439 VGA_DRAW_LINE8,
1440 VGA_DRAW_LINE15,
1441 VGA_DRAW_LINE16,
1442 VGA_DRAW_LINE24,
1443 VGA_DRAW_LINE32,
1444 VGA_DRAW_LINE_NB,
1445 };
1446
1447 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1448 vga_draw_line2_8,
1449 vga_draw_line2_16,
1450 vga_draw_line2_16,
1451 vga_draw_line2_32,
1452 vga_draw_line2_32,
1453 vga_draw_line2_16,
1454 vga_draw_line2_16,
1455
1456 vga_draw_line2d2_8,
1457 vga_draw_line2d2_16,
1458 vga_draw_line2d2_16,
1459 vga_draw_line2d2_32,
1460 vga_draw_line2d2_32,
1461 vga_draw_line2d2_16,
1462 vga_draw_line2d2_16,
1463
1464 vga_draw_line4_8,
1465 vga_draw_line4_16,
1466 vga_draw_line4_16,
1467 vga_draw_line4_32,
1468 vga_draw_line4_32,
1469 vga_draw_line4_16,
1470 vga_draw_line4_16,
1471
1472 vga_draw_line4d2_8,
1473 vga_draw_line4d2_16,
1474 vga_draw_line4d2_16,
1475 vga_draw_line4d2_32,
1476 vga_draw_line4d2_32,
1477 vga_draw_line4d2_16,
1478 vga_draw_line4d2_16,
1479
1480 vga_draw_line8d2_8,
1481 vga_draw_line8d2_16,
1482 vga_draw_line8d2_16,
1483 vga_draw_line8d2_32,
1484 vga_draw_line8d2_32,
1485 vga_draw_line8d2_16,
1486 vga_draw_line8d2_16,
1487
1488 vga_draw_line8_8,
1489 vga_draw_line8_16,
1490 vga_draw_line8_16,
1491 vga_draw_line8_32,
1492 vga_draw_line8_32,
1493 vga_draw_line8_16,
1494 vga_draw_line8_16,
1495
1496 vga_draw_line15_8,
1497 vga_draw_line15_15,
1498 vga_draw_line15_16,
1499 vga_draw_line15_32,
1500 vga_draw_line15_32bgr,
1501 vga_draw_line15_15bgr,
1502 vga_draw_line15_16bgr,
1503
1504 vga_draw_line16_8,
1505 vga_draw_line16_15,
1506 vga_draw_line16_16,
1507 vga_draw_line16_32,
1508 vga_draw_line16_32bgr,
1509 vga_draw_line16_15bgr,
1510 vga_draw_line16_16bgr,
1511
1512 vga_draw_line24_8,
1513 vga_draw_line24_15,
1514 vga_draw_line24_16,
1515 vga_draw_line24_32,
1516 vga_draw_line24_32bgr,
1517 vga_draw_line24_15bgr,
1518 vga_draw_line24_16bgr,
1519
1520 vga_draw_line32_8,
1521 vga_draw_line32_15,
1522 vga_draw_line32_16,
1523 vga_draw_line32_32,
1524 vga_draw_line32_32bgr,
1525 vga_draw_line32_15bgr,
1526 vga_draw_line32_16bgr,
1527 };
1528
1529 static int vga_get_bpp(VGAState *s)
1530 {
1531 int ret;
1532 #ifdef CONFIG_BOCHS_VBE
1533 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1534 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1535 } else
1536 #endif
1537 {
1538 ret = 0;
1539 }
1540 return ret;
1541 }
1542
1543 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1544 {
1545 int width, height;
1546
1547 #ifdef CONFIG_BOCHS_VBE
1548 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1549 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1550 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1551 } else
1552 #endif
1553 {
1554 width = (s->cr[0x01] + 1) * 8;
1555 height = s->cr[0x12] |
1556 ((s->cr[0x07] & 0x02) << 7) |
1557 ((s->cr[0x07] & 0x40) << 3);
1558 height = (height + 1);
1559 }
1560 *pwidth = width;
1561 *pheight = height;
1562 }
1563
1564 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1565 {
1566 int y;
1567 if (y1 >= VGA_MAX_HEIGHT)
1568 return;
1569 if (y2 >= VGA_MAX_HEIGHT)
1570 y2 = VGA_MAX_HEIGHT;
1571 for(y = y1; y < y2; y++) {
1572 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1573 }
1574 }
1575
1576 static void vga_sync_dirty_bitmap(VGAState *s)
1577 {
1578 if (s->map_addr)
1579 cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
1580
1581 if (s->lfb_vram_mapped) {
1582 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
1583 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
1584 }
1585 vga_dirty_log_start(s);
1586 }
1587
1588 /*
1589 * graphic modes
1590 */
1591 static void vga_draw_graphic(VGAState *s, int full_update)
1592 {
1593 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1594 int width, height, shift_control, line_offset, bwidth, bits;
1595 ram_addr_t page0, page1, page_min, page_max;
1596 int disp_width, multi_scan, multi_run;
1597 uint8_t *d;
1598 uint32_t v, addr1, addr;
1599 vga_draw_line_func *vga_draw_line;
1600
1601 full_update |= update_basic_params(s);
1602
1603 if (!full_update)
1604 vga_sync_dirty_bitmap(s);
1605
1606 s->get_resolution(s, &width, &height);
1607 disp_width = width;
1608
1609 shift_control = (s->gr[0x05] >> 5) & 3;
1610 double_scan = (s->cr[0x09] >> 7);
1611 if (shift_control != 1) {
1612 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1613 } else {
1614 /* in CGA modes, multi_scan is ignored */
1615 /* XXX: is it correct ? */
1616 multi_scan = double_scan;
1617 }
1618 multi_run = multi_scan;
1619 if (shift_control != s->shift_control ||
1620 double_scan != s->double_scan) {
1621 full_update = 1;
1622 s->shift_control = shift_control;
1623 s->double_scan = double_scan;
1624 }
1625
1626 if (shift_control == 0) {
1627 if (s->sr[0x01] & 8) {
1628 disp_width <<= 1;
1629 }
1630 } else if (shift_control == 1) {
1631 if (s->sr[0x01] & 8) {
1632 disp_width <<= 1;
1633 }
1634 }
1635
1636 depth = s->get_bpp(s);
1637 if (s->line_offset != s->last_line_offset ||
1638 disp_width != s->last_width ||
1639 height != s->last_height ||
1640 s->last_depth != depth) {
1641 #if defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1642 if (depth == 16 || depth == 32) {
1643 #else
1644 if (depth == 32) {
1645 #endif
1646 qemu_free_displaysurface(s->ds);
1647 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1648 s->line_offset,
1649 s->vram_ptr + (s->start_addr * 4));
1650 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1651 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1652 #endif
1653 dpy_resize(s->ds);
1654 } else {
1655 qemu_console_resize(s->ds, disp_width, height);
1656 }
1657 s->last_scr_width = disp_width;
1658 s->last_scr_height = height;
1659 s->last_width = disp_width;
1660 s->last_height = height;
1661 s->last_line_offset = s->line_offset;
1662 s->last_depth = depth;
1663 full_update = 1;
1664 } else if (is_buffer_shared(s->ds->surface) &&
1665 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1666 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1667 dpy_setdata(s->ds);
1668 }
1669
1670 s->rgb_to_pixel =
1671 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1672
1673 if (shift_control == 0) {
1674 full_update |= update_palette16(s);
1675 if (s->sr[0x01] & 8) {
1676 v = VGA_DRAW_LINE4D2;
1677 } else {
1678 v = VGA_DRAW_LINE4;
1679 }
1680 bits = 4;
1681 } else if (shift_control == 1) {
1682 full_update |= update_palette16(s);
1683 if (s->sr[0x01] & 8) {
1684 v = VGA_DRAW_LINE2D2;
1685 } else {
1686 v = VGA_DRAW_LINE2;
1687 }
1688 bits = 4;
1689 } else {
1690 switch(s->get_bpp(s)) {
1691 default:
1692 case 0:
1693 full_update |= update_palette256(s);
1694 v = VGA_DRAW_LINE8D2;
1695 bits = 4;
1696 break;
1697 case 8:
1698 full_update |= update_palette256(s);
1699 v = VGA_DRAW_LINE8;
1700 bits = 8;
1701 break;
1702 case 15:
1703 v = VGA_DRAW_LINE15;
1704 bits = 16;
1705 break;
1706 case 16:
1707 v = VGA_DRAW_LINE16;
1708 bits = 16;
1709 break;
1710 case 24:
1711 v = VGA_DRAW_LINE24;
1712 bits = 24;
1713 break;
1714 case 32:
1715 v = VGA_DRAW_LINE32;
1716 bits = 32;
1717 break;
1718 }
1719 }
1720 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1721
1722 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1723 s->cursor_invalidate(s);
1724
1725 line_offset = s->line_offset;
1726 #if 0
1727 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1728 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1729 #endif
1730 addr1 = (s->start_addr * 4);
1731 bwidth = (width * bits + 7) / 8;
1732 y_start = -1;
1733 page_min = -1;
1734 page_max = 0;
1735 d = ds_get_data(s->ds);
1736 linesize = ds_get_linesize(s->ds);
1737 y1 = 0;
1738 for(y = 0; y < height; y++) {
1739 addr = addr1;
1740 if (!(s->cr[0x17] & 1)) {
1741 int shift;
1742 /* CGA compatibility handling */
1743 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1744 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1745 }
1746 if (!(s->cr[0x17] & 2)) {
1747 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1748 }
1749 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1750 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1751 update = full_update |
1752 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1753 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1754 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1755 /* if wide line, can use another page */
1756 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1757 VGA_DIRTY_FLAG);
1758 }
1759 /* explicit invalidation for the hardware cursor */
1760 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1761 if (update) {
1762 if (y_start < 0)
1763 y_start = y;
1764 if (page0 < page_min)
1765 page_min = page0;
1766 if (page1 > page_max)
1767 page_max = page1;
1768 if (!(is_buffer_shared(s->ds->surface))) {
1769 vga_draw_line(s, d, s->vram_ptr + addr, width);
1770 if (s->cursor_draw_line)
1771 s->cursor_draw_line(s, d, y);
1772 }
1773 } else {
1774 if (y_start >= 0) {
1775 /* flush to display */
1776 dpy_update(s->ds, 0, y_start,
1777 disp_width, y - y_start);
1778 y_start = -1;
1779 }
1780 }
1781 if (!multi_run) {
1782 mask = (s->cr[0x17] & 3) ^ 3;
1783 if ((y1 & mask) == mask)
1784 addr1 += line_offset;
1785 y1++;
1786 multi_run = multi_scan;
1787 } else {
1788 multi_run--;
1789 }
1790 /* line compare acts on the displayed lines */
1791 if (y == s->line_compare)
1792 addr1 = 0;
1793 d += linesize;
1794 }
1795 if (y_start >= 0) {
1796 /* flush to display */
1797 dpy_update(s->ds, 0, y_start,
1798 disp_width, y - y_start);
1799 }
1800 /* reset modified pages */
1801 if (page_max >= page_min) {
1802 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1803 VGA_DIRTY_FLAG);
1804 }
1805 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1806 }
1807
1808 static void vga_draw_blank(VGAState *s, int full_update)
1809 {
1810 int i, w, val;
1811 uint8_t *d;
1812
1813 if (!full_update)
1814 return;
1815 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1816 return;
1817 vga_dirty_log_stop(s);
1818
1819 s->rgb_to_pixel =
1820 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1821 if (ds_get_bits_per_pixel(s->ds) == 8)
1822 val = s->rgb_to_pixel(0, 0, 0);
1823 else
1824 val = 0;
1825 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1826 d = ds_get_data(s->ds);
1827 for(i = 0; i < s->last_scr_height; i++) {
1828 memset(d, val, w);
1829 d += ds_get_linesize(s->ds);
1830 }
1831 dpy_update(s->ds, 0, 0,
1832 s->last_scr_width, s->last_scr_height);
1833 }
1834
1835 #define GMODE_TEXT 0
1836 #define GMODE_GRAPH 1
1837 #define GMODE_BLANK 2
1838
1839 static void vga_update_display(void *opaque)
1840 {
1841 VGAState *s = (VGAState *)opaque;
1842 int full_update, graphic_mode;
1843
1844 if (ds_get_bits_per_pixel(s->ds) == 0) {
1845 /* nothing to do */
1846 } else {
1847 full_update = s->full_update;
1848 s->full_update = 0;
1849 if (!(s->ar_index & 0x20)) {
1850 graphic_mode = GMODE_BLANK;
1851 } else {
1852 graphic_mode = s->gr[6] & 1;
1853 }
1854 if (graphic_mode != s->graphic_mode) {
1855 s->graphic_mode = graphic_mode;
1856 full_update = 1;
1857 }
1858 switch(graphic_mode) {
1859 case GMODE_TEXT:
1860 vga_draw_text(s, full_update);
1861 break;
1862 case GMODE_GRAPH:
1863 #ifdef TARGET_IA64
1864 full_update = 1;
1865 #endif
1866 vga_draw_graphic(s, full_update);
1867 break;
1868 case GMODE_BLANK:
1869 default:
1870 vga_draw_blank(s, full_update);
1871 break;
1872 }
1873 }
1874 }
1875
1876 /* force a full display refresh */
1877 static void vga_invalidate_display(void *opaque)
1878 {
1879 VGAState *s = (VGAState *)opaque;
1880
1881 s->full_update = 1;
1882 }
1883
1884 void vga_reset(void *opaque)
1885 {
1886 VGAState *s = (VGAState *) opaque;
1887
1888 s->lfb_addr = 0;
1889 s->lfb_end = 0;
1890 s->map_addr = 0;
1891 s->map_end = 0;
1892 s->lfb_vram_mapped = 0;
1893 s->bios_offset = 0;
1894 s->bios_size = 0;
1895 s->sr_index = 0;
1896 memset(s->sr, '\0', sizeof(s->sr));
1897 s->gr_index = 0;
1898 memset(s->gr, '\0', sizeof(s->gr));
1899 s->ar_index = 0;
1900 memset(s->ar, '\0', sizeof(s->ar));
1901 s->ar_flip_flop = 0;
1902 s->cr_index = 0;
1903 memset(s->cr, '\0', sizeof(s->cr));
1904 s->msr = 0;
1905 s->fcr = 0;
1906 s->st00 = 0;
1907 s->st01 = 0;
1908 s->dac_state = 0;
1909 s->dac_sub_index = 0;
1910 s->dac_read_index = 0;
1911 s->dac_write_index = 0;
1912 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1913 s->dac_8bit = 0;
1914 memset(s->palette, '\0', sizeof(s->palette));
1915 s->bank_offset = 0;
1916 #ifdef CONFIG_BOCHS_VBE
1917 s->vbe_index = 0;
1918 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1919 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1920 s->vbe_start_addr = 0;
1921 s->vbe_line_offset = 0;
1922 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1923 #endif
1924 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1925 s->graphic_mode = -1; /* force full update */
1926 s->shift_control = 0;
1927 s->double_scan = 0;
1928 s->line_offset = 0;
1929 s->line_compare = 0;
1930 s->start_addr = 0;
1931 s->plane_updated = 0;
1932 s->last_cw = 0;
1933 s->last_ch = 0;
1934 s->last_width = 0;
1935 s->last_height = 0;
1936 s->last_scr_width = 0;
1937 s->last_scr_height = 0;
1938 s->cursor_start = 0;
1939 s->cursor_end = 0;
1940 s->cursor_offset = 0;
1941 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1942 memset(s->last_palette, '\0', sizeof(s->last_palette));
1943 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1944 switch (vga_retrace_method) {
1945 case VGA_RETRACE_DUMB:
1946 break;
1947 case VGA_RETRACE_PRECISE:
1948 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1949 break;
1950 }
1951 }
1952
1953 #define TEXTMODE_X(x) ((x) % width)
1954 #define TEXTMODE_Y(x) ((x) / width)
1955 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1956 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1957 /* relay text rendering to the display driver
1958 * instead of doing a full vga_update_display() */
1959 static void vga_update_text(void *opaque, console_ch_t *chardata)
1960 {
1961 VGAState *s = (VGAState *) opaque;
1962 int graphic_mode, i, cursor_offset, cursor_visible;
1963 int cw, cheight, width, height, size, c_min, c_max;
1964 uint32_t *src;
1965 console_ch_t *dst, val;
1966 char msg_buffer[80];
1967 int full_update = 0;
1968
1969 if (!(s->ar_index & 0x20)) {
1970 graphic_mode = GMODE_BLANK;
1971 } else {
1972 graphic_mode = s->gr[6] & 1;
1973 }
1974 if (graphic_mode != s->graphic_mode) {
1975 s->graphic_mode = graphic_mode;
1976 full_update = 1;
1977 }
1978 if (s->last_width == -1) {
1979 s->last_width = 0;
1980 full_update = 1;
1981 }
1982
1983 switch (graphic_mode) {
1984 case GMODE_TEXT:
1985 /* TODO: update palette */
1986 full_update |= update_basic_params(s);
1987
1988 /* total width & height */
1989 cheight = (s->cr[9] & 0x1f) + 1;
1990 cw = 8;
1991 if (!(s->sr[1] & 0x01))
1992 cw = 9;
1993 if (s->sr[1] & 0x08)
1994 cw = 16; /* NOTE: no 18 pixel wide */
1995 width = (s->cr[0x01] + 1);
1996 if (s->cr[0x06] == 100) {
1997 /* ugly hack for CGA 160x100x16 - explain me the logic */
1998 height = 100;
1999 } else {
2000 height = s->cr[0x12] |
2001 ((s->cr[0x07] & 0x02) << 7) |
2002 ((s->cr[0x07] & 0x40) << 3);
2003 height = (height + 1) / cheight;
2004 }
2005
2006 size = (height * width);
2007 if (size > CH_ATTR_SIZE) {
2008 if (!full_update)
2009 return;
2010
2011 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2012 width, height);
2013 break;
2014 }
2015
2016 if (width != s->last_width || height != s->last_height ||
2017 cw != s->last_cw || cheight != s->last_ch) {
2018 s->last_scr_width = width * cw;
2019 s->last_scr_height = height * cheight;
2020 s->ds->surface->width = width;
2021 s->ds->surface->height = height;
2022 dpy_resize(s->ds);
2023 s->last_width = width;
2024 s->last_height = height;
2025 s->last_ch = cheight;
2026 s->last_cw = cw;
2027 full_update = 1;
2028 }
2029
2030 /* Update "hardware" cursor */
2031 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
2032 if (cursor_offset != s->cursor_offset ||
2033 s->cr[0xa] != s->cursor_start ||
2034 s->cr[0xb] != s->cursor_end || full_update) {
2035 cursor_visible = !(s->cr[0xa] & 0x20);
2036 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2037 dpy_cursor(s->ds,
2038 TEXTMODE_X(cursor_offset),
2039 TEXTMODE_Y(cursor_offset));
2040 else
2041 dpy_cursor(s->ds, -1, -1);
2042 s->cursor_offset = cursor_offset;
2043 s->cursor_start = s->cr[0xa];
2044 s->cursor_end = s->cr[0xb];
2045 }
2046
2047 src = (uint32_t *) s->vram_ptr + s->start_addr;
2048 dst = chardata;
2049
2050 if (full_update) {
2051 for (i = 0; i < size; src ++, dst ++, i ++)
2052 console_write_ch(dst, VMEM2CHTYPE(*src));
2053
2054 dpy_update(s->ds, 0, 0, width, height);
2055 } else {
2056 c_max = 0;
2057
2058 for (i = 0; i < size; src ++, dst ++, i ++) {
2059 console_write_ch(&val, VMEM2CHTYPE(*src));
2060 if (*dst != val) {
2061 *dst = val;
2062 c_max = i;
2063 break;
2064 }
2065 }
2066 c_min = i;
2067 for (; i < size; src ++, dst ++, i ++) {
2068 console_write_ch(&val, VMEM2CHTYPE(*src));
2069 if (*dst != val) {
2070 *dst = val;
2071 c_max = i;
2072 }
2073 }
2074
2075 if (c_min <= c_max) {
2076 i = TEXTMODE_Y(c_min);
2077 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2078 }
2079 }
2080
2081 return;
2082 case GMODE_GRAPH:
2083 if (!full_update)
2084 return;
2085
2086 s->get_resolution(s, &width, &height);
2087 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2088 width, height);
2089 break;
2090 case GMODE_BLANK:
2091 default:
2092 if (!full_update)
2093 return;
2094
2095 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2096 break;
2097 }
2098
2099 /* Display a message */
2100 s->last_width = 60;
2101 s->last_height = height = 3;
2102 dpy_cursor(s->ds, -1, -1);
2103 s->ds->surface->width = s->last_width;
2104 s->ds->surface->height = height;
2105 dpy_resize(s->ds);
2106
2107 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2108 console_write_ch(dst ++, ' ');
2109
2110 size = strlen(msg_buffer);
2111 width = (s->last_width - size) / 2;
2112 dst = chardata + s->last_width + width;
2113 for (i = 0; i < size; i ++)
2114 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2115
2116 dpy_update(s->ds, 0, 0, s->last_width, height);
2117 }
2118
2119 static CPUReadMemoryFunc *vga_mem_read[3] = {
2120 vga_mem_readb,
2121 vga_mem_readw,
2122 vga_mem_readl,
2123 };
2124
2125 static CPUWriteMemoryFunc *vga_mem_write[3] = {
2126 vga_mem_writeb,
2127 vga_mem_writew,
2128 vga_mem_writel,
2129 };
2130
2131 static void vga_save(QEMUFile *f, void *opaque)
2132 {
2133 VGAState *s = opaque;
2134 int i;
2135
2136 if (s->pci_dev)
2137 pci_device_save(s->pci_dev, f);
2138
2139 qemu_put_be32s(f, &s->latch);
2140 qemu_put_8s(f, &s->sr_index);
2141 qemu_put_buffer(f, s->sr, 8);
2142 qemu_put_8s(f, &s->gr_index);
2143 qemu_put_buffer(f, s->gr, 16);
2144 qemu_put_8s(f, &s->ar_index);
2145 qemu_put_buffer(f, s->ar, 21);
2146 qemu_put_be32(f, s->ar_flip_flop);
2147 qemu_put_8s(f, &s->cr_index);
2148 qemu_put_buffer(f, s->cr, 256);
2149 qemu_put_8s(f, &s->msr);
2150 qemu_put_8s(f, &s->fcr);
2151 qemu_put_byte(f, s->st00);
2152 qemu_put_8s(f, &s->st01);
2153
2154 qemu_put_8s(f, &s->dac_state);
2155 qemu_put_8s(f, &s->dac_sub_index);
2156 qemu_put_8s(f, &s->dac_read_index);
2157 qemu_put_8s(f, &s->dac_write_index);
2158 qemu_put_buffer(f, s->dac_cache, 3);
2159 qemu_put_buffer(f, s->palette, 768);
2160
2161 qemu_put_be32(f, s->bank_offset);
2162 #ifdef CONFIG_BOCHS_VBE
2163 qemu_put_byte(f, 1);
2164 qemu_put_be16s(f, &s->vbe_index);
2165 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2166 qemu_put_be16s(f, &s->vbe_regs[i]);
2167 qemu_put_be32s(f, &s->vbe_start_addr);
2168 qemu_put_be32s(f, &s->vbe_line_offset);
2169 qemu_put_be32s(f, &s->vbe_bank_mask);
2170 #else
2171 qemu_put_byte(f, 0);
2172 #endif
2173 }
2174
2175 static int vga_load(QEMUFile *f, void *opaque, int version_id)
2176 {
2177 VGAState *s = opaque;
2178 int is_vbe, i, ret;
2179
2180 if (version_id > 2)
2181 return -EINVAL;
2182
2183 if (s->pci_dev && version_id >= 2) {
2184 ret = pci_device_load(s->pci_dev, f);
2185 if (ret < 0)
2186 return ret;
2187 }
2188
2189 qemu_get_be32s(f, &s->latch);
2190 qemu_get_8s(f, &s->sr_index);
2191 qemu_get_buffer(f, s->sr, 8);
2192 qemu_get_8s(f, &s->gr_index);
2193 qemu_get_buffer(f, s->gr, 16);
2194 qemu_get_8s(f, &s->ar_index);
2195 qemu_get_buffer(f, s->ar, 21);
2196 s->ar_flip_flop=qemu_get_be32(f);
2197 qemu_get_8s(f, &s->cr_index);
2198 qemu_get_buffer(f, s->cr, 256);
2199 qemu_get_8s(f, &s->msr);
2200 qemu_get_8s(f, &s->fcr);
2201 qemu_get_8s(f, &s->st00);
2202 qemu_get_8s(f, &s->st01);
2203
2204 qemu_get_8s(f, &s->dac_state);
2205 qemu_get_8s(f, &s->dac_sub_index);
2206 qemu_get_8s(f, &s->dac_read_index);
2207 qemu_get_8s(f, &s->dac_write_index);
2208 qemu_get_buffer(f, s->dac_cache, 3);
2209 qemu_get_buffer(f, s->palette, 768);
2210
2211 s->bank_offset=qemu_get_be32(f);
2212 is_vbe = qemu_get_byte(f);
2213 #ifdef CONFIG_BOCHS_VBE
2214 if (!is_vbe)
2215 return -EINVAL;
2216 qemu_get_be16s(f, &s->vbe_index);
2217 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2218 qemu_get_be16s(f, &s->vbe_regs[i]);
2219 qemu_get_be32s(f, &s->vbe_start_addr);
2220 qemu_get_be32s(f, &s->vbe_line_offset);
2221 qemu_get_be32s(f, &s->vbe_bank_mask);
2222 #else
2223 if (is_vbe)
2224 return -EINVAL;
2225 #endif
2226
2227 /* force refresh */
2228 s->graphic_mode = -1;
2229 return 0;
2230 }
2231
2232 typedef struct PCIVGAState {
2233 PCIDevice dev;
2234 VGAState vga_state;
2235 } PCIVGAState;
2236
2237 static int s1, s2;
2238
2239 static void mark_dirty(target_phys_addr_t start, target_phys_addr_t len)
2240 {
2241 target_phys_addr_t end = start + len;
2242
2243 while (start < end) {
2244 cpu_physical_memory_set_dirty(cpu_get_physical_page_desc(start));
2245 start += TARGET_PAGE_SIZE;
2246 }
2247 }
2248
2249 void vga_dirty_log_start(VGAState *s)
2250 {
2251 if (kvm_enabled() && s->map_addr)
2252 if (!s1) {
2253 kvm_log_start(s->map_addr, s->map_end - s->map_addr);
2254 mark_dirty(s->map_addr, s->map_end - s->map_addr);
2255 s1 = 1;
2256 }
2257 if (kvm_enabled() && s->lfb_vram_mapped) {
2258 if (!s2) {
2259 kvm_log_start(isa_mem_base + 0xa0000, 0x8000);
2260 kvm_log_start(isa_mem_base + 0xa8000, 0x8000);
2261 mark_dirty(isa_mem_base + 0xa0000, 0x10000);
2262 }
2263 s2 = 1;
2264 }
2265 }
2266
2267 void vga_dirty_log_stop(VGAState *s)
2268 {
2269 if (kvm_enabled() && s->map_addr && s1)
2270 kvm_log_stop(s->map_addr, s->map_end - s->map_addr);
2271
2272 if (kvm_enabled() && s->lfb_vram_mapped && s2) {
2273 kvm_log_stop(isa_mem_base + 0xa0000, 0x8000);
2274 kvm_log_stop(isa_mem_base + 0xa8000, 0x8000);
2275 }
2276 s1 = s2 = 0;
2277 }
2278
2279 static void vga_map(PCIDevice *pci_dev, int region_num,
2280 uint32_t addr, uint32_t size, int type)
2281 {
2282 PCIVGAState *d = (PCIVGAState *)pci_dev;
2283 VGAState *s = &d->vga_state;
2284 if (region_num == PCI_ROM_SLOT) {
2285 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2286 } else {
2287 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2288 }
2289
2290 s->map_addr = addr;
2291 s->map_end = addr + VGA_RAM_SIZE;
2292
2293 vga_dirty_log_start(s);
2294 }
2295
2296 void vga_common_init(VGAState *s, int vga_ram_size)
2297 {
2298 int i, j, v, b;
2299
2300 for(i = 0;i < 256; i++) {
2301 v = 0;
2302 for(j = 0; j < 8; j++) {
2303 v |= ((i >> j) & 1) << (j * 4);
2304 }
2305 expand4[i] = v;
2306
2307 v = 0;
2308 for(j = 0; j < 4; j++) {
2309 v |= ((i >> (2 * j)) & 3) << (j * 4);
2310 }
2311 expand2[i] = v;
2312 }
2313 for(i = 0; i < 16; i++) {
2314 v = 0;
2315 for(j = 0; j < 4; j++) {
2316 b = ((i >> j) & 1);
2317 v |= b << (2 * j);
2318 v |= b << (2 * j + 1);
2319 }
2320 expand4to8[i] = v;
2321 }
2322
2323 s->vram_offset = qemu_ram_alloc(vga_ram_size);
2324 s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
2325 s->vram_size = vga_ram_size;
2326 s->get_bpp = vga_get_bpp;
2327 s->get_offsets = vga_get_offsets;
2328 s->get_resolution = vga_get_resolution;
2329 s->update = vga_update_display;
2330 s->invalidate = vga_invalidate_display;
2331 s->screen_dump = vga_screen_dump;
2332 s->text_update = vga_update_text;
2333 switch (vga_retrace_method) {
2334 case VGA_RETRACE_DUMB:
2335 s->retrace = vga_dumb_retrace;
2336 s->update_retrace_info = vga_dumb_update_retrace_info;
2337 break;
2338
2339 case VGA_RETRACE_PRECISE:
2340 s->retrace = vga_precise_retrace;
2341 s->update_retrace_info = vga_precise_update_retrace_info;
2342 break;
2343 }
2344 vga_reset(s);
2345 }
2346
2347 /* used by both ISA and PCI */
2348 void vga_init(VGAState *s)
2349 {
2350 int vga_io_memory;
2351
2352 qemu_register_reset(vga_reset, s);
2353 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2354
2355 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2356
2357 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2358 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2359 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2360 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2361
2362 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2363
2364 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2365 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2366 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2367 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2368 s->bank_offset = 0;
2369
2370 #ifdef CONFIG_BOCHS_VBE
2371 #if defined (TARGET_I386)
2372 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2373 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2374
2375 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2376 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2377
2378 /* old Bochs IO ports */
2379 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2380 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2381
2382 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2383 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2384 #else
2385 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2386 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2387
2388 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2389 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2390 #endif
2391 #endif /* CONFIG_BOCHS_VBE */
2392
2393 vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
2394 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2395 vga_io_memory);
2396 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2397 }
2398
2399 /* Memory mapped interface */
2400 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2401 {
2402 VGAState *s = opaque;
2403
2404 return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
2405 }
2406
2407 static void vga_mm_writeb (void *opaque,
2408 target_phys_addr_t addr, uint32_t value)
2409 {
2410 VGAState *s = opaque;
2411
2412 vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
2413 }
2414
2415 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2416 {
2417 VGAState *s = opaque;
2418
2419 return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
2420 }
2421
2422 static void vga_mm_writew (void *opaque,
2423 target_phys_addr_t addr, uint32_t value)
2424 {
2425 VGAState *s = opaque;
2426
2427 vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
2428 }
2429
2430 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2431 {
2432 VGAState *s = opaque;
2433
2434 return vga_ioport_read(s, addr >> s->it_shift);
2435 }
2436
2437 static void vga_mm_writel (void *opaque,
2438 target_phys_addr_t addr, uint32_t value)
2439 {
2440 VGAState *s = opaque;
2441
2442 vga_ioport_write(s, addr >> s->it_shift, value);
2443 }
2444
2445 static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2446 &vga_mm_readb,
2447 &vga_mm_readw,
2448 &vga_mm_readl,
2449 };
2450
2451 static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2452 &vga_mm_writeb,
2453 &vga_mm_writew,
2454 &vga_mm_writel,
2455 };
2456
2457 static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2458 target_phys_addr_t ctrl_base, int it_shift)
2459 {
2460 int s_ioport_ctrl, vga_io_memory;
2461
2462 s->it_shift = it_shift;
2463 s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2464 vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
2465
2466 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2467
2468 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2469 s->bank_offset = 0;
2470 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2471 qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
2472 }
2473
2474 int isa_vga_init(void)
2475 {
2476 VGAState *s;
2477
2478 s = qemu_mallocz(sizeof(VGAState));
2479
2480 vga_common_init(s, VGA_RAM_SIZE);
2481 vga_init(s);
2482
2483 s->ds = graphic_console_init(s->update, s->invalidate,
2484 s->screen_dump, s->text_update, s);
2485
2486 #ifdef CONFIG_BOCHS_VBE
2487 /* XXX: use optimized standard vga accesses */
2488 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2489 VGA_RAM_SIZE, s->vram_offset);
2490 #endif
2491 return 0;
2492 }
2493
2494 int isa_vga_mm_init(target_phys_addr_t vram_base,
2495 target_phys_addr_t ctrl_base, int it_shift)
2496 {
2497 VGAState *s;
2498
2499 s = qemu_mallocz(sizeof(VGAState));
2500
2501 vga_common_init(s, VGA_RAM_SIZE);
2502 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2503
2504 s->ds = graphic_console_init(s->update, s->invalidate,
2505 s->screen_dump, s->text_update, s);
2506
2507 #ifdef CONFIG_BOCHS_VBE
2508 /* XXX: use optimized standard vga accesses */
2509 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2510 VGA_RAM_SIZE, s->vram_offset);
2511 #endif
2512 return 0;
2513 }
2514
2515 static void pci_vga_write_config(PCIDevice *d,
2516 uint32_t address, uint32_t val, int len)
2517 {
2518 PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
2519 VGAState *s = &pvs->vga_state;
2520
2521 vga_dirty_log_stop(s);
2522 pci_default_write_config(d, address, val, len);
2523 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
2524 s->map_addr = 0;
2525 vga_dirty_log_start(s);
2526 }
2527
2528 int pci_vga_init(PCIBus *bus,
2529 unsigned long vga_bios_offset, int vga_bios_size)
2530 {
2531 PCIVGAState *d;
2532 VGAState *s;
2533 uint8_t *pci_conf;
2534
2535 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2536 sizeof(PCIVGAState),
2537 -1, NULL, pci_vga_write_config);
2538 if (!d)
2539 return -1;
2540 s = &d->vga_state;
2541
2542 vga_common_init(s, VGA_RAM_SIZE);
2543 vga_init(s);
2544
2545 s->ds = graphic_console_init(s->update, s->invalidate,
2546 s->screen_dump, s->text_update, s);
2547
2548 s->pci_dev = &d->dev;
2549
2550 pci_conf = d->dev.config;
2551 // dummy VGA (same as Bochs ID)
2552 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
2553 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
2554 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
2555 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
2556
2557 /* XXX: VGA_RAM_SIZE must be a power of two */
2558 pci_register_bar(&d->dev, 0, VGA_RAM_SIZE,
2559 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2560 if (vga_bios_size != 0) {
2561 unsigned int bios_total_size;
2562 s->bios_offset = vga_bios_offset;
2563 s->bios_size = vga_bios_size;
2564 /* must be a power of two */
2565 bios_total_size = 1;
2566 while (bios_total_size < vga_bios_size)
2567 bios_total_size <<= 1;
2568 pci_register_bar(&d->dev, PCI_ROM_SLOT, bios_total_size,
2569 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2570 }
2571 return 0;
2572 }
2573
2574 /********************************************************/
2575 /* vga screen dump */
2576
2577 static void vga_save_dpy_update(DisplayState *ds,
2578 int x, int y, int w, int h)
2579 {
2580 if (screen_dump_filename) {
2581 ppm_save(screen_dump_filename, ds->surface);
2582 screen_dump_filename = NULL;
2583 }
2584 }
2585
2586 static void vga_save_dpy_resize(DisplayState *s)
2587 {
2588 }
2589
2590 static void vga_save_dpy_refresh(DisplayState *s)
2591 {
2592 }
2593
2594 int ppm_save(const char *filename, struct DisplaySurface *ds)
2595 {
2596 FILE *f;
2597 uint8_t *d, *d1;
2598 uint32_t v;
2599 int y, x;
2600 uint8_t r, g, b;
2601
2602 f = fopen(filename, "wb");
2603 if (!f)
2604 return -1;
2605 fprintf(f, "P6\n%d %d\n%d\n",
2606 ds->width, ds->height, 255);
2607 d1 = ds->data;
2608 for(y = 0; y < ds->height; y++) {
2609 d = d1;
2610 for(x = 0; x < ds->width; x++) {
2611 if (ds->pf.bits_per_pixel == 32)
2612 v = *(uint32_t *)d;
2613 else
2614 v = (uint32_t) (*(uint16_t *)d);
2615 r = ((v >> ds->pf.rshift) & ds->pf.rmax) * 256 /
2616 (ds->pf.rmax + 1);
2617 g = ((v >> ds->pf.gshift) & ds->pf.gmax) * 256 /
2618 (ds->pf.gmax + 1);
2619 b = ((v >> ds->pf.bshift) & ds->pf.bmax) * 256 /
2620 (ds->pf.bmax + 1);
2621 fputc(r, f);
2622 fputc(g, f);
2623 fputc(b, f);
2624 d += ds->pf.bytes_per_pixel;
2625 }
2626 d1 += ds->linesize;
2627 }
2628 fclose(f);
2629 return 0;
2630 }
2631
2632 static DisplayChangeListener* vga_screen_dump_init(DisplayState *ds)
2633 {
2634 DisplayChangeListener *dcl;
2635
2636 dcl = qemu_mallocz(sizeof(DisplayChangeListener));
2637 dcl->dpy_update = vga_save_dpy_update;
2638 dcl->dpy_resize = vga_save_dpy_resize;
2639 dcl->dpy_refresh = vga_save_dpy_refresh;
2640 register_displaychangelistener(ds, dcl);
2641 return dcl;
2642 }
2643
2644 /* save the vga display in a PPM image even if no display is
2645 available */
2646 static void vga_screen_dump(void *opaque, const char *filename)
2647 {
2648 VGAState *s = (VGAState *)opaque;
2649
2650 if (!screen_dump_dcl)
2651 screen_dump_dcl = vga_screen_dump_init(s->ds);
2652
2653 screen_dump_filename = (char *)filename;
2654 vga_invalidate_display(s);
2655 vga_hw_update();
2656 }
2657
Patches shipped by Fedora