target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "exec-all.h"
  28
  29 enum {
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 /* no MMU emulation */
  38 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  39                         target_ulong address, int rw, int access_type)
  40 {
  41     *physical = address;
  42     *prot = PAGE_READ | PAGE_WRITE;
  43     return TLBRET_MATCH;
  44 }
  45
  46 /* fixed mapping MMU emulation */
  47 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  48                            target_ulong address, int rw, int access_type)
  49 {
  50     if (address <= (int32_t)0x7FFFFFFFUL) {
  51         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  52             *physical = address + 0x40000000UL;
  53         else
  54             *physical = address;
  55     } else if (address <= (int32_t)0xBFFFFFFFUL)
  56         *physical = address & 0x1FFFFFFF;
  57     else
  58         *physical = address;
  59
  60     *prot = PAGE_READ | PAGE_WRITE;
  61     return TLBRET_MATCH;
  62 }
  63
  64 /* MIPS32/MIPS64 R4000-style MMU emulation */
  65 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
  66                      target_ulong address, int rw, int access_type)
  67 {
  68     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  69     int i;
  70
  71     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  72         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  73         /* 1k pages are not supported. */
  74         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  75         target_ulong tag = address & ~mask;
  76         target_ulong VPN = tlb->VPN & ~mask;
  77 #if defined(TARGET_MIPS64)
  78         tag &= env->SEGMask;
  79 #endif
  80
  81         /* Check ASID, virtual page number & size */
  82         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  83             /* TLB match */
  84             int n = !!(address & mask & ~(mask >> 1));
  85             /* Check access rights */
  86             if (!(n ? tlb->V1 : tlb->V0))
  87                 return TLBRET_INVALID;
  88             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  89                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  90                 *prot = PAGE_READ;
  91                 if (n ? tlb->D1 : tlb->D0)
  92                     *prot |= PAGE_WRITE;
  93                 return TLBRET_MATCH;
  94             }
  95             return TLBRET_DIRTY;
  96         }
  97     }
  98     return TLBRET_NOMATCH;
  99 }
 100
 101 #if !defined(CONFIG_USER_ONLY)
 102 static int get_physical_address (CPUState *env, target_ulong *physical,
 103                                 int *prot, target_ulong address,
 104                                 int rw, int access_type)
 105 {
 106     /* User mode can only access useg/xuseg */
 107     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 108     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 109     int kernel_mode = !user_mode && !supervisor_mode;
 110 #if defined(TARGET_MIPS64)
 111     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 112     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 113     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 114 #endif
 115     int ret = TLBRET_MATCH;
 116
 117 #if 0
 118     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 119 #endif
 120
 121     if (address <= (int32_t)0x7FFFFFFFUL) {
 122         /* useg */
 123         if (env->CP0_Status & (1 << CP0St_ERL)) {
 124             *physical = address & 0xFFFFFFFF;
 125             *prot = PAGE_READ | PAGE_WRITE;
 126         } else {
 127             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 128         }
 129 #if defined(TARGET_MIPS64)
 130     } else if (address < 0x4000000000000000ULL) {
 131         /* xuseg */
 132         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 133             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 134         } else {
 135             ret = TLBRET_BADADDR;
 136         }
 137     } else if (address < 0x8000000000000000ULL) {
 138         /* xsseg */
 139         if ((supervisor_mode || kernel_mode) &&
 140             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 141             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 142         } else {
 143             ret = TLBRET_BADADDR;
 144         }
 145     } else if (address < 0xC000000000000000ULL) {
 146         /* xkphys */
 147         if (kernel_mode && KX &&
 148             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 149             *physical = address & env->PAMask;
 150             *prot = PAGE_READ | PAGE_WRITE;
 151         } else {
 152             ret = TLBRET_BADADDR;
 153         }
 154     } else if (address < 0xFFFFFFFF80000000ULL) {
 155         /* xkseg */
 156         if (kernel_mode && KX &&
 157             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 158             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 159         } else {
 160             ret = TLBRET_BADADDR;
 161         }
 162 #endif
 163     } else if (address < (int32_t)0xA0000000UL) {
 164         /* kseg0 */
 165         if (kernel_mode) {
 166             *physical = address - (int32_t)0x80000000UL;
 167             *prot = PAGE_READ | PAGE_WRITE;
 168         } else {
 169             ret = TLBRET_BADADDR;
 170         }
 171     } else if (address < (int32_t)0xC0000000UL) {
 172         /* kseg1 */
 173         if (kernel_mode) {
 174             *physical = address - (int32_t)0xA0000000UL;
 175             *prot = PAGE_READ | PAGE_WRITE;
 176         } else {
 177             ret = TLBRET_BADADDR;
 178         }
 179     } else if (address < (int32_t)0xE0000000UL) {
 180         /* sseg (kseg2) */
 181         if (supervisor_mode || kernel_mode) {
 182             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 183         } else {
 184             ret = TLBRET_BADADDR;
 185         }
 186     } else {
 187         /* kseg3 */
 188         /* XXX: debug segment is not emulated */
 189         if (kernel_mode) {
 190             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 191         } else {
 192             ret = TLBRET_BADADDR;
 193         }
 194     }
 195 #if 0
 196     qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
 197             address, rw, access_type, *physical, *prot, ret);
 198     }
 199 #endif
 200
 201     return ret;
 202 }
 203 #endif
 204
 205 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 206 {
 207 #if defined(CONFIG_USER_ONLY)
 208     return addr;
 209 #else
 210     target_ulong phys_addr;
 211     int prot;
 212
 213     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 214         return -1;
 215     return phys_addr;
 216 #endif
 217 }
 218
 219 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 220                                int mmu_idx, int is_softmmu)
 221 {
 222 #if !defined(CONFIG_USER_ONLY)
 223     target_ulong physical;
 224     int prot;
 225 #endif
 226     int exception = 0, error_code = 0;
 227     int access_type;
 228     int ret = 0;
 229
 230 #if 0
 231     log_cpu_state(env, 0);
 232 #endif
 233     qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
 234               __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
 235
 236     rw &= 1;
 237
 238     /* data access */
 239     /* XXX: put correct access by using cpu_restore_state()
 240        correctly */
 241     access_type = ACCESS_INT;
 242 #if defined(CONFIG_USER_ONLY)
 243     ret = TLBRET_NOMATCH;
 244 #else
 245     ret = get_physical_address(env, &physical, &prot,
 246                                address, rw, access_type);
 247     qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
 248               __func__, address, ret, physical, prot);
 249     if (ret == TLBRET_MATCH) {
 250        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
 251                           physical & TARGET_PAGE_MASK, prot,
 252                           mmu_idx, is_softmmu);
 253     } else if (ret < 0)
 254 #endif
 255     {
 256         switch (ret) {
 257         default:
 258         case TLBRET_BADADDR:
 259             /* Reference to kernel address from user mode or supervisor mode */
 260             /* Reference to supervisor address from user mode */
 261             if (rw)
 262                 exception = EXCP_AdES;
 263             else
 264                 exception = EXCP_AdEL;
 265             break;
 266         case TLBRET_NOMATCH:
 267             /* No TLB match for a mapped address */
 268             if (rw)
 269                 exception = EXCP_TLBS;
 270             else
 271                 exception = EXCP_TLBL;
 272             error_code = 1;
 273             break;
 274         case TLBRET_INVALID:
 275             /* TLB match with no valid bit */
 276             if (rw)
 277                 exception = EXCP_TLBS;
 278             else
 279                 exception = EXCP_TLBL;
 280             break;
 281         case TLBRET_DIRTY:
 282             /* TLB match but 'D' bit is cleared */
 283             exception = EXCP_LTLBL;
 284             break;
 285
 286         }
 287         /* Raise exception */
 288         env->CP0_BadVAddr = address;
 289         env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 290                            ((address >> 9) &   0x007ffff0);
 291         env->CP0_EntryHi =
 292             (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 293 #if defined(TARGET_MIPS64)
 294         env->CP0_EntryHi &= env->SEGMask;
 295         env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 296                             ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 297                             ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 298 #endif
 299         env->exception_index = exception;
 300         env->error_code = error_code;
 301         ret = 1;
 302     }
 303
 304     return ret;
 305 }
 306
 307 static const char * const excp_names[EXCP_LAST + 1] = {
 308     [EXCP_RESET] = "reset",
 309     [EXCP_SRESET] = "soft reset",
 310     [EXCP_DSS] = "debug single step",
 311     [EXCP_DINT] = "debug interrupt",
 312     [EXCP_NMI] = "non-maskable interrupt",
 313     [EXCP_MCHECK] = "machine check",
 314     [EXCP_EXT_INTERRUPT] = "interrupt",
 315     [EXCP_DFWATCH] = "deferred watchpoint",
 316     [EXCP_DIB] = "debug instruction breakpoint",
 317     [EXCP_IWATCH] = "instruction fetch watchpoint",
 318     [EXCP_AdEL] = "address error load",
 319     [EXCP_AdES] = "address error store",
 320     [EXCP_TLBF] = "TLB refill",
 321     [EXCP_IBE] = "instruction bus error",
 322     [EXCP_DBp] = "debug breakpoint",
 323     [EXCP_SYSCALL] = "syscall",
 324     [EXCP_BREAK] = "break",
 325     [EXCP_CpU] = "coprocessor unusable",
 326     [EXCP_RI] = "reserved instruction",
 327     [EXCP_OVERFLOW] = "arithmetic overflow",
 328     [EXCP_TRAP] = "trap",
 329     [EXCP_FPE] = "floating point",
 330     [EXCP_DDBS] = "debug data break store",
 331     [EXCP_DWATCH] = "data watchpoint",
 332     [EXCP_LTLBL] = "TLB modify",
 333     [EXCP_TLBL] = "TLB load",
 334     [EXCP_TLBS] = "TLB store",
 335     [EXCP_DBE] = "data bus error",
 336     [EXCP_DDBL] = "debug data break load",
 337     [EXCP_THREAD] = "thread",
 338     [EXCP_MDMX] = "MDMX",
 339     [EXCP_C2E] = "precise coprocessor 2",
 340     [EXCP_CACHE] = "cache error",
 341 };
 342
 343 void do_interrupt (CPUState *env)
 344 {
 345 #if !defined(CONFIG_USER_ONLY)
 346     target_ulong offset;
 347     int cause = -1;
 348     const char *name;
 349
 350     if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 351         if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
 352             name = "unknown";
 353         else
 354             name = excp_names[env->exception_index];
 355
 356         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 357                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 358     }
 359     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 360         (env->hflags & MIPS_HFLAG_DM))
 361         env->exception_index = EXCP_DINT;
 362     offset = 0x180;
 363     switch (env->exception_index) {
 364     case EXCP_DSS:
 365         env->CP0_Debug |= 1 << CP0DB_DSS;
 366         /* Debug single step cannot be raised inside a delay slot and
 367            resume will always occur on the next instruction
 368            (but we assume the pc has always been updated during
 369            code translation). */
 370         env->CP0_DEPC = env->active_tc.PC;
 371         goto enter_debug_mode;
 372     case EXCP_DINT:
 373         env->CP0_Debug |= 1 << CP0DB_DINT;
 374         goto set_DEPC;
 375     case EXCP_DIB:
 376         env->CP0_Debug |= 1 << CP0DB_DIB;
 377         goto set_DEPC;
 378     case EXCP_DBp:
 379         env->CP0_Debug |= 1 << CP0DB_DBp;
 380         goto set_DEPC;
 381     case EXCP_DDBS:
 382         env->CP0_Debug |= 1 << CP0DB_DDBS;
 383         goto set_DEPC;
 384     case EXCP_DDBL:
 385         env->CP0_Debug |= 1 << CP0DB_DDBL;
 386     set_DEPC:
 387         if (env->hflags & MIPS_HFLAG_BMASK) {
 388             /* If the exception was raised from a delay slot,
 389                come back to the jump.  */
 390             env->CP0_DEPC = env->active_tc.PC - 4;
 391             env->hflags &= ~MIPS_HFLAG_BMASK;
 392         } else {
 393             env->CP0_DEPC = env->active_tc.PC;
 394         }
 395  enter_debug_mode:
 396         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 397         env->hflags &= ~(MIPS_HFLAG_KSU);
 398         /* EJTAG probe trap enable is not implemented... */
 399         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 400             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 401         env->active_tc.PC = (int32_t)0xBFC00480;
 402         break;
 403     case EXCP_RESET:
 404         cpu_reset(env);
 405         break;
 406     case EXCP_SRESET:
 407         env->CP0_Status |= (1 << CP0St_SR);
 408         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 409         goto set_error_EPC;
 410     case EXCP_NMI:
 411         env->CP0_Status |= (1 << CP0St_NMI);
 412  set_error_EPC:
 413         if (env->hflags & MIPS_HFLAG_BMASK) {
 414             /* If the exception was raised from a delay slot,
 415                come back to the jump.  */
 416             env->CP0_ErrorEPC = env->active_tc.PC - 4;
 417             env->hflags &= ~MIPS_HFLAG_BMASK;
 418         } else {
 419             env->CP0_ErrorEPC = env->active_tc.PC;
 420         }
 421         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 422         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 423         env->hflags &= ~(MIPS_HFLAG_KSU);
 424         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 425             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 426         env->active_tc.PC = (int32_t)0xBFC00000;
 427         break;
 428     case EXCP_EXT_INTERRUPT:
 429         cause = 0;
 430         if (env->CP0_Cause & (1 << CP0Ca_IV))
 431             offset = 0x200;
 432         goto set_EPC;
 433     case EXCP_LTLBL:
 434         cause = 1;
 435         goto set_EPC;
 436     case EXCP_TLBL:
 437         cause = 2;
 438         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 439 #if defined(TARGET_MIPS64)
 440             int R = env->CP0_BadVAddr >> 62;
 441             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 442             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 443             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 444
 445             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 446                 offset = 0x080;
 447             else
 448 #endif
 449                 offset = 0x000;
 450         }
 451         goto set_EPC;
 452     case EXCP_TLBS:
 453         cause = 3;
 454         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 455 #if defined(TARGET_MIPS64)
 456             int R = env->CP0_BadVAddr >> 62;
 457             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 458             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 459             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 460
 461             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 462                 offset = 0x080;
 463             else
 464 #endif
 465                 offset = 0x000;
 466         }
 467         goto set_EPC;
 468     case EXCP_AdEL:
 469         cause = 4;
 470         goto set_EPC;
 471     case EXCP_AdES:
 472         cause = 5;
 473         goto set_EPC;
 474     case EXCP_IBE:
 475         cause = 6;
 476         goto set_EPC;
 477     case EXCP_DBE:
 478         cause = 7;
 479         goto set_EPC;
 480     case EXCP_SYSCALL:
 481         cause = 8;
 482         goto set_EPC;
 483     case EXCP_BREAK:
 484         cause = 9;
 485         goto set_EPC;
 486     case EXCP_RI:
 487         cause = 10;
 488         goto set_EPC;
 489     case EXCP_CpU:
 490         cause = 11;
 491         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 492                          (env->error_code << CP0Ca_CE);
 493         goto set_EPC;
 494     case EXCP_OVERFLOW:
 495         cause = 12;
 496         goto set_EPC;
 497     case EXCP_TRAP:
 498         cause = 13;
 499         goto set_EPC;
 500     case EXCP_FPE:
 501         cause = 15;
 502         goto set_EPC;
 503     case EXCP_C2E:
 504         cause = 18;
 505         goto set_EPC;
 506     case EXCP_MDMX:
 507         cause = 22;
 508         goto set_EPC;
 509     case EXCP_DWATCH:
 510         cause = 23;
 511         /* XXX: TODO: manage defered watch exceptions */
 512         goto set_EPC;
 513     case EXCP_MCHECK:
 514         cause = 24;
 515         goto set_EPC;
 516     case EXCP_THREAD:
 517         cause = 25;
 518         goto set_EPC;
 519     case EXCP_CACHE:
 520         cause = 30;
 521         if (env->CP0_Status & (1 << CP0St_BEV)) {
 522             offset = 0x100;
 523         } else {
 524             offset = 0x20000100;
 525         }
 526  set_EPC:
 527         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 528             if (env->hflags & MIPS_HFLAG_BMASK) {
 529                 /* If the exception was raised from a delay slot,
 530                    come back to the jump.  */
 531                 env->CP0_EPC = env->active_tc.PC - 4;
 532                 env->CP0_Cause |= (1 << CP0Ca_BD);
 533             } else {
 534                 env->CP0_EPC = env->active_tc.PC;
 535                 env->CP0_Cause &= ~(1 << CP0Ca_BD);
 536             }
 537             env->CP0_Status |= (1 << CP0St_EXL);
 538             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 539             env->hflags &= ~(MIPS_HFLAG_KSU);
 540         }
 541         env->hflags &= ~MIPS_HFLAG_BMASK;
 542         if (env->CP0_Status & (1 << CP0St_BEV)) {
 543             env->active_tc.PC = (int32_t)0xBFC00200;
 544         } else {
 545             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 546         }
 547         env->active_tc.PC += offset;
 548         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 549         break;
 550     default:
 551         qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 552         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 553         exit(1);
 554     }
 555     if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 556         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 557                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 558                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 559                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 560                 env->CP0_DEPC);
 561     }
 562 #endif
 563     env->exception_index = EXCP_NONE;
 564 }
 565
 566 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 567 {
 568     r4k_tlb_t *tlb;
 569     target_ulong addr;
 570     target_ulong end;
 571     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 572     target_ulong mask;
 573
 574     tlb = &env->tlb->mmu.r4k.tlb[idx];
 575     /* The qemu TLB is flushed when the ASID changes, so no need to
 576        flush these entries again.  */
 577     if (tlb->G == 0 && tlb->ASID != ASID) {
 578         return;
 579     }
 580
 581     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 582         /* For tlbwr, we can shadow the discarded entry into
 583            a new (fake) TLB entry, as long as the guest can not
 584            tell that it's there.  */
 585         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 586         env->tlb->tlb_in_use++;
 587         return;
 588     }
 589
 590     /* 1k pages are not supported. */
 591     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 592     if (tlb->V0) {
 593         addr = tlb->VPN & ~mask;
 594 #if defined(TARGET_MIPS64)
 595         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 596             addr |= 0x3FFFFF0000000000ULL;
 597         }
 598 #endif
 599         end = addr | (mask >> 1);
 600         while (addr < end) {
 601             tlb_flush_page (env, addr);
 602             addr += TARGET_PAGE_SIZE;
 603         }
 604     }
 605     if (tlb->V1) {
 606         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 607 #if defined(TARGET_MIPS64)
 608         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 609             addr |= 0x3FFFFF0000000000ULL;
 610         }
 611 #endif
 612         end = addr | mask;
 613         while (addr - 1 < end) {
 614             tlb_flush_page (env, addr);
 615             addr += TARGET_PAGE_SIZE;
 616         }
 617     }
 618 }