hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "qemu-timer.h"
  27 #include "sysbus.h"
  28
  29 //#define DEBUG_TIMER
  30
  31 #ifdef DEBUG_TIMER
  32 #define DPRINTF(fmt, ...)                                       \
  33     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...) do {} while (0)
  36 #endif
  37
  38 /*
  39  * Registers of hardware timer in sun4m.
  40  *
  41  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  42  * produced as NCR89C105. See
  43  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  44  *
  45  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  46  * are zero. Bit 31 is 1 when count has been reached.
  47  *
  48  * Per-CPU timers interrupt local CPU, system timer uses normal
  49  * interrupt routing.
  50  *
  51  */
  52
  53 #define MAX_CPUS 16
  54
  55 typedef struct CPUTimerState {
  56     qemu_irq irq;
  57     ptimer_state *timer;
  58     uint32_t count, counthigh, reached;
  59     uint64_t limit;
  60     // processor only
  61     uint32_t running;
  62 } CPUTimerState;
  63
  64 typedef struct SLAVIO_TIMERState {
  65     SysBusDevice busdev;
  66     uint32_t num_cpus;
  67     CPUTimerState cputimer[MAX_CPUS + 1];
  68     uint32_t cputimer_mode;
  69 } SLAVIO_TIMERState;
  70
  71 typedef struct TimerContext {
  72     SLAVIO_TIMERState *s;
  73     unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
  74 } TimerContext;
  75
  76 #define SYS_TIMER_SIZE 0x14
  77 #define CPU_TIMER_SIZE 0x10
  78
  79 #define TIMER_LIMIT         0
  80 #define TIMER_COUNTER       1
  81 #define TIMER_COUNTER_NORST 2
  82 #define TIMER_STATUS        3
  83 #define TIMER_MODE          4
  84
  85 #define TIMER_COUNT_MASK32 0xfffffe00
  86 #define TIMER_LIMIT_MASK32 0x7fffffff
  87 #define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
  88 #define TIMER_MAX_COUNT32  0x7ffffe00ULL
  89 #define TIMER_REACHED      0x80000000
  90 #define TIMER_PERIOD       500ULL // 500ns
  91 #define LIMIT_TO_PERIODS(l) ((l) >> 9)
  92 #define PERIODS_TO_LIMIT(l) ((l) << 9)
  93
  94 static int slavio_timer_is_user(TimerContext *tc)
  95 {
  96     SLAVIO_TIMERState *s = tc->s;
  97     unsigned int timer_index = tc->timer_index;
  98
  99     return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
 100 }
 101
 102 // Update count, set irq, update expire_time
 103 // Convert from ptimer countdown units
 104 static void slavio_timer_get_out(CPUTimerState *t)
 105 {
 106     uint64_t count, limit;
 107
 108     if (t->limit == 0) { /* free-run system or processor counter */
 109         limit = TIMER_MAX_COUNT32;
 110     } else {
 111         limit = t->limit;
 112     }
 113     count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
 114
 115     DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh,
 116             t->count);
 117     t->count = count & TIMER_COUNT_MASK32;
 118     t->counthigh = count >> 32;
 119 }
 120
 121 // timer callback
 122 static void slavio_timer_irq(void *opaque)
 123 {
 124     TimerContext *tc = opaque;
 125     SLAVIO_TIMERState *s = tc->s;
 126     CPUTimerState *t = &s->cputimer[tc->timer_index];
 127
 128     slavio_timer_get_out(t);
 129     DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
 130     t->reached = TIMER_REACHED;
 131     if (!slavio_timer_is_user(tc)) {
 132         qemu_irq_raise(t->irq);
 133     }
 134 }
 135
 136 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
 137 {
 138     TimerContext *tc = opaque;
 139     SLAVIO_TIMERState *s = tc->s;
 140     uint32_t saddr, ret;
 141     unsigned int timer_index = tc->timer_index;
 142     CPUTimerState *t = &s->cputimer[timer_index];
 143
 144     saddr = addr >> 2;
 145     switch (saddr) {
 146     case TIMER_LIMIT:
 147         // read limit (system counter mode) or read most signifying
 148         // part of counter (user mode)
 149         if (slavio_timer_is_user(tc)) {
 150             // read user timer MSW
 151             slavio_timer_get_out(t);
 152             ret = t->counthigh | t->reached;
 153         } else {
 154             // read limit
 155             // clear irq
 156             qemu_irq_lower(t->irq);
 157             t->reached = 0;
 158             ret = t->limit & TIMER_LIMIT_MASK32;
 159         }
 160         break;
 161     case TIMER_COUNTER:
 162         // read counter and reached bit (system mode) or read lsbits
 163         // of counter (user mode)
 164         slavio_timer_get_out(t);
 165         if (slavio_timer_is_user(tc)) { // read user timer LSW
 166             ret = t->count & TIMER_MAX_COUNT64;
 167         } else { // read limit
 168             ret = (t->count & TIMER_MAX_COUNT32) |
 169                 t->reached;
 170         }
 171         break;
 172     case TIMER_STATUS:
 173         // only available in processor counter/timer
 174         // read start/stop status
 175         if (timer_index > 0) {
 176             ret = t->running;
 177         } else {
 178             ret = 0;
 179         }
 180         break;
 181     case TIMER_MODE:
 182         // only available in system counter
 183         // read user/system mode
 184         ret = s->cputimer_mode;
 185         break;
 186     default:
 187         DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
 188         ret = 0;
 189         break;
 190     }
 191     DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
 192
 193     return ret;
 194 }
 195
 196 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
 197                                     uint32_t val)
 198 {
 199     TimerContext *tc = opaque;
 200     SLAVIO_TIMERState *s = tc->s;
 201     uint32_t saddr;
 202     unsigned int timer_index = tc->timer_index;
 203     CPUTimerState *t = &s->cputimer[timer_index];
 204
 205     DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
 206     saddr = addr >> 2;
 207     switch (saddr) {
 208     case TIMER_LIMIT:
 209         if (slavio_timer_is_user(tc)) {
 210             uint64_t count;
 211
 212             // set user counter MSW, reset counter
 213             t->limit = TIMER_MAX_COUNT64;
 214             t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
 215             t->reached = 0;
 216             count = ((uint64_t)t->counthigh << 32) | t->count;
 217             DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
 218                     timer_index, count);
 219             ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 220         } else {
 221             // set limit, reset counter
 222             qemu_irq_lower(t->irq);
 223             t->limit = val & TIMER_MAX_COUNT32;
 224             if (t->timer) {
 225                 if (t->limit == 0) { /* free-run */
 226                     ptimer_set_limit(t->timer,
 227                                      LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 228                 } else {
 229                     ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
 230                 }
 231             }
 232         }
 233         break;
 234     case TIMER_COUNTER:
 235         if (slavio_timer_is_user(tc)) {
 236             uint64_t count;
 237
 238             // set user counter LSW, reset counter
 239             t->limit = TIMER_MAX_COUNT64;
 240             t->count = val & TIMER_MAX_COUNT64;
 241             t->reached = 0;
 242             count = ((uint64_t)t->counthigh) << 32 | t->count;
 243             DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
 244                     timer_index, count);
 245             ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 246         } else
 247             DPRINTF("not user timer\n");
 248         break;
 249     case TIMER_COUNTER_NORST:
 250         // set limit without resetting counter
 251         t->limit = val & TIMER_MAX_COUNT32;
 252         if (t->limit == 0) { /* free-run */
 253             ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
 254         } else {
 255             ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
 256         }
 257         break;
 258     case TIMER_STATUS:
 259         if (slavio_timer_is_user(tc)) {
 260             // start/stop user counter
 261             if ((val & 1) && !t->running) {
 262                 DPRINTF("processor %d user timer started\n",
 263                         timer_index);
 264                 ptimer_run(t->timer, 0);
 265                 t->running = 1;
 266             } else if (!(val & 1) && t->running) {
 267                 DPRINTF("processor %d user timer stopped\n",
 268                         timer_index);
 269                 ptimer_stop(t->timer);
 270                 t->running = 0;
 271             }
 272         }
 273         break;
 274     case TIMER_MODE:
 275         if (timer_index == 0) {
 276             unsigned int i;
 277
 278             for (i = 0; i < s->num_cpus; i++) {
 279                 unsigned int processor = 1 << i;
 280                 CPUTimerState *curr_timer = &s->cputimer[i + 1];
 281
 282                 // check for a change in timer mode for this processor
 283                 if ((val & processor) != (s->cputimer_mode & processor)) {
 284                     if (val & processor) { // counter -> user timer
 285                         qemu_irq_lower(curr_timer->irq);
 286                         // counters are always running
 287                         ptimer_stop(curr_timer->timer);
 288                         curr_timer->running = 0;
 289                         // user timer limit is always the same
 290                         curr_timer->limit = TIMER_MAX_COUNT64;
 291                         ptimer_set_limit(curr_timer->timer,
 292                                          LIMIT_TO_PERIODS(curr_timer->limit),
 293                                          1);
 294                         // set this processors user timer bit in config
 295                         // register
 296                         s->cputimer_mode |= processor;
 297                         DPRINTF("processor %d changed from counter to user "
 298                                 "timer\n", timer_index);
 299                     } else { // user timer -> counter
 300                         // stop the user timer if it is running
 301                         if (curr_timer->running) {
 302                             ptimer_stop(curr_timer->timer);
 303                         }
 304                         // start the counter
 305                         ptimer_run(curr_timer->timer, 0);
 306                         curr_timer->running = 1;
 307                         // clear this processors user timer bit in config
 308                         // register
 309                         s->cputimer_mode &= ~processor;
 310                         DPRINTF("processor %d changed from user timer to "
 311                                 "counter\n", timer_index);
 312                     }
 313                 }
 314             }
 315         } else {
 316             DPRINTF("not system timer\n");
 317         }
 318         break;
 319     default:
 320         DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
 321         break;
 322     }
 323 }
 324
 325 static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
 326     NULL,
 327     NULL,
 328     slavio_timer_mem_readl,
 329 };
 330
 331 static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
 332     NULL,
 333     NULL,
 334     slavio_timer_mem_writel,
 335 };
 336
 337 static const VMStateDescription vmstate_timer = {
 338     .name ="timer",
 339     .version_id = 3,
 340     .minimum_version_id = 3,
 341     .minimum_version_id_old = 3,
 342     .fields      = (VMStateField []) {
 343         VMSTATE_UINT64(limit, CPUTimerState),
 344         VMSTATE_UINT32(count, CPUTimerState),
 345         VMSTATE_UINT32(counthigh, CPUTimerState),
 346         VMSTATE_UINT32(reached, CPUTimerState),
 347         VMSTATE_UINT32(running, CPUTimerState),
 348         VMSTATE_PTIMER(timer, CPUTimerState),
 349         VMSTATE_END_OF_LIST()
 350     }
 351 };
 352
 353 static const VMStateDescription vmstate_slavio_timer = {
 354     .name ="slavio_timer",
 355     .version_id = 3,
 356     .minimum_version_id = 3,
 357     .minimum_version_id_old = 3,
 358     .fields      = (VMStateField []) {
 359         VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
 360                              vmstate_timer, CPUTimerState),
 361         VMSTATE_END_OF_LIST()
 362     }
 363 };
 364
 365 static void slavio_timer_reset(DeviceState *d)
 366 {
 367     SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
 368     unsigned int i;
 369     CPUTimerState *curr_timer;
 370
 371     for (i = 0; i <= MAX_CPUS; i++) {
 372         curr_timer = &s->cputimer[i];
 373         curr_timer->limit = 0;
 374         curr_timer->count = 0;
 375         curr_timer->reached = 0;
 376         if (i < s->num_cpus) {
 377             ptimer_set_limit(curr_timer->timer,
 378                              LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 379             ptimer_run(curr_timer->timer, 0);
 380         }
 381         curr_timer->running = 1;
 382     }
 383     s->cputimer_mode = 0;
 384 }
 385
 386 static int slavio_timer_init1(SysBusDevice *dev)
 387 {
 388     int io;
 389     SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
 390     QEMUBH *bh;
 391     unsigned int i;
 392     TimerContext *tc;
 393
 394     for (i = 0; i <= MAX_CPUS; i++) {
 395         tc = qemu_mallocz(sizeof(TimerContext));
 396         tc->s = s;
 397         tc->timer_index = i;
 398
 399         bh = qemu_bh_new(slavio_timer_irq, tc);
 400         s->cputimer[i].timer = ptimer_init(bh);
 401         ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
 402
 403         io = cpu_register_io_memory(slavio_timer_mem_read,
 404                                     slavio_timer_mem_write, tc);
 405         if (i == 0) {
 406             sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
 407         } else {
 408             sysbus_init_mmio(dev, CPU_TIMER_SIZE, io);
 409         }
 410
 411         sysbus_init_irq(dev, &s->cputimer[i].irq);
 412     }
 413
 414     slavio_timer_reset(&s->busdev.qdev);
 415
 416     return 0;
 417 }
 418
 419 static SysBusDeviceInfo slavio_timer_info = {
 420     .init = slavio_timer_init1,
 421     .qdev.name  = "slavio_timer",
 422     .qdev.size  = sizeof(SLAVIO_TIMERState),
 423     .qdev.vmsd  = &vmstate_slavio_timer,
 424     .qdev.reset = slavio_timer_reset,
 425     .qdev.props = (Property[]) {
 426         DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
 427         DEFINE_PROP_END_OF_LIST(),
 428     }
 429 };
 430
 431 static void slavio_timer_register_devices(void)
 432 {
 433     sysbus_register_withprop(&slavio_timer_info);
 434 }
 435
 436 device_init(slavio_timer_register_devices)