target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_I386_H
  20 #define CPU_I386_H
  21
  22 #include "config.h"
  23
  24 #ifdef TARGET_X86_64
  25 #define TARGET_LONG_BITS 64
  26 #else
  27 #define TARGET_LONG_BITS 32
  28 #endif
  29
  30 /* target supports implicit self modifying code */
  31 #define TARGET_HAS_SMC
  32 /* support for self modifying code even if the modified instruction is
  33    close to the modifying instruction */
  34 #define TARGET_HAS_PRECISE_SMC
  35
  36 #define TARGET_HAS_ICE 1
  37
  38 #ifdef TARGET_X86_64
  39 #define ELF_MACHINE     EM_X86_64
  40 #else
  41 #define ELF_MACHINE     EM_386
  42 #endif
  43
  44 #define CPUState struct CPUX86State
  45
  46 #include "cpu-defs.h"
  47
  48 #include "softfloat.h"
  49
  50 #define R_EAX 0
  51 #define R_ECX 1
  52 #define R_EDX 2
  53 #define R_EBX 3
  54 #define R_ESP 4
  55 #define R_EBP 5
  56 #define R_ESI 6
  57 #define R_EDI 7
  58
  59 #define R_AL 0
  60 #define R_CL 1
  61 #define R_DL 2
  62 #define R_BL 3
  63 #define R_AH 4
  64 #define R_CH 5
  65 #define R_DH 6
  66 #define R_BH 7
  67
  68 #define R_ES 0
  69 #define R_CS 1
  70 #define R_SS 2
  71 #define R_DS 3
  72 #define R_FS 4
  73 #define R_GS 5
  74
  75 /* segment descriptor fields */
  76 #define DESC_G_MASK     (1 << 23)
  77 #define DESC_B_SHIFT    22
  78 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  79 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  80 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  81 #define DESC_AVL_MASK   (1 << 20)
  82 #define DESC_P_MASK     (1 << 15)
  83 #define DESC_DPL_SHIFT  13
  84 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
  85 #define DESC_S_MASK     (1 << 12)
  86 #define DESC_TYPE_SHIFT 8
  87 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
  88 #define DESC_A_MASK     (1 << 8)
  89
  90 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  91 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  92 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  93
  94 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  95 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  96
  97 #define DESC_TSS_BUSY_MASK (1 << 9)
  98
  99 /* eflags masks */
 100 #define CC_C    0x0001
 101 #define CC_P    0x0004
 102 #define CC_A    0x0010
 103 #define CC_Z    0x0040
 104 #define CC_S    0x0080
 105 #define CC_O    0x0800
 106
 107 #define TF_SHIFT   8
 108 #define IOPL_SHIFT 12
 109 #define VM_SHIFT   17
 110
 111 #define TF_MASK                 0x00000100
 112 #define IF_MASK                 0x00000200
 113 #define DF_MASK                 0x00000400
 114 #define IOPL_MASK               0x00003000
 115 #define NT_MASK                 0x00004000
 116 #define RF_MASK                 0x00010000
 117 #define VM_MASK                 0x00020000
 118 #define AC_MASK                 0x00040000
 119 #define VIF_MASK                0x00080000
 120 #define VIP_MASK                0x00100000
 121 #define ID_MASK                 0x00200000
 122
 123 /* hidden flags - used internally by qemu to represent additional cpu
 124    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 125    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
 126    position to ease oring with eflags. */
 127 /* current cpl */
 128 #define HF_CPL_SHIFT         0
 129 /* true if soft mmu is being used */
 130 #define HF_SOFTMMU_SHIFT     2
 131 /* true if hardware interrupts must be disabled for next instruction */
 132 #define HF_INHIBIT_IRQ_SHIFT 3
 133 /* 16 or 32 segments */
 134 #define HF_CS32_SHIFT        4
 135 #define HF_SS32_SHIFT        5
 136 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 137 #define HF_ADDSEG_SHIFT      6
 138 /* copy of CR0.PE (protected mode) */
 139 #define HF_PE_SHIFT          7
 140 #define HF_TF_SHIFT          8 /* must be same as eflags */
 141 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 142 #define HF_EM_SHIFT         10
 143 #define HF_TS_SHIFT         11
 144 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 145 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 146 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 147 #define HF_RF_SHIFT         16 /* must be same as eflags */
 148 #define HF_VM_SHIFT         17 /* must be same as eflags */
 149 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 150 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 151 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 152 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 153
 154 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 155 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 156 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 157 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 158 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 159 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 160 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 161 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 162 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 163 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 164 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 165 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 166 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 167 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 168 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
 169 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 170 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 171 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 172 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 173 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 174
 175 /* hflags2 */
 176
 177 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 178 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 179 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 180 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 181
 182 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 183 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 184 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 185 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 186
 187 #define CR0_PE_SHIFT 0
 188 #define CR0_MP_SHIFT 1
 189
 190 #define CR0_PE_MASK  (1 << 0)
 191 #define CR0_MP_MASK  (1 << 1)
 192 #define CR0_EM_MASK  (1 << 2)
 193 #define CR0_TS_MASK  (1 << 3)
 194 #define CR0_ET_MASK  (1 << 4)
 195 #define CR0_NE_MASK  (1 << 5)
 196 #define CR0_WP_MASK  (1 << 16)
 197 #define CR0_AM_MASK  (1 << 18)
 198 #define CR0_PG_MASK  (1 << 31)
 199
 200 #define CR4_VME_MASK  (1 << 0)
 201 #define CR4_PVI_MASK  (1 << 1)
 202 #define CR4_TSD_MASK  (1 << 2)
 203 #define CR4_DE_MASK   (1 << 3)
 204 #define CR4_PSE_MASK  (1 << 4)
 205 #define CR4_PAE_MASK  (1 << 5)
 206 #define CR4_MCE_MASK  (1 << 6)
 207 #define CR4_PGE_MASK  (1 << 7)
 208 #define CR4_PCE_MASK  (1 << 8)
 209 #define CR4_OSFXSR_SHIFT 9
 210 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 211 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 212
 213 #define DR6_BD          (1 << 13)
 214 #define DR6_BS          (1 << 14)
 215 #define DR6_BT          (1 << 15)
 216 #define DR6_FIXED_1     0xffff0ff0
 217
 218 #define DR7_GD          (1 << 13)
 219 #define DR7_TYPE_SHIFT  16
 220 #define DR7_LEN_SHIFT   18
 221 #define DR7_FIXED_1     0x00000400
 222
 223 #define PG_PRESENT_BIT  0
 224 #define PG_RW_BIT       1
 225 #define PG_USER_BIT     2
 226 #define PG_PWT_BIT      3
 227 #define PG_PCD_BIT      4
 228 #define PG_ACCESSED_BIT 5
 229 #define PG_DIRTY_BIT    6
 230 #define PG_PSE_BIT      7
 231 #define PG_GLOBAL_BIT   8
 232 #define PG_NX_BIT       63
 233
 234 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 235 #define PG_RW_MASK       (1 << PG_RW_BIT)
 236 #define PG_USER_MASK     (1 << PG_USER_BIT)
 237 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 238 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 239 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 240 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 241 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 242 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 243 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 244
 245 #define PG_ERROR_W_BIT     1
 246
 247 #define PG_ERROR_P_MASK    0x01
 248 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 249 #define PG_ERROR_U_MASK    0x04
 250 #define PG_ERROR_RSVD_MASK 0x08
 251 #define PG_ERROR_I_D_MASK  0x10
 252
 253 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
 254 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
 255
 256 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
 257 #define MCE_BANKS_DEF   10
 258
 259 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
 260 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
 261 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
 262
 263 #define MCI_STATUS_VAL  (1ULL<<63)  /* valid error */
 264 #define MCI_STATUS_OVER (1ULL<<62)  /* previous errors lost */
 265 #define MCI_STATUS_UC   (1ULL<<61)  /* uncorrected error */
 266 #define MCI_STATUS_EN   (1ULL<<60)  /* error enabled */
 267 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
 268 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
 269 #define MCI_STATUS_PCC  (1ULL<<57)  /* processor context corrupt */
 270 #define MCI_STATUS_S    (1ULL<<56)  /* Signaled machine check */
 271 #define MCI_STATUS_AR   (1ULL<<55)  /* Action required */
 272
 273 /* MISC register defines */
 274 #define MCM_ADDR_SEGOFF 0       /* segment offset */
 275 #define MCM_ADDR_LINEAR 1       /* linear address */
 276 #define MCM_ADDR_PHYS   2       /* physical address */
 277 #define MCM_ADDR_MEM    3       /* memory address */
 278 #define MCM_ADDR_GENERIC 7      /* generic */
 279
 280 #define MSR_IA32_TSC                    0x10
 281 #define MSR_IA32_APICBASE               0x1b
 282 #define MSR_IA32_APICBASE_BSP           (1<<8)
 283 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 284 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 285
 286 #define MSR_MTRRcap                     0xfe
 287 #define MSR_MTRRcap_VCNT                8
 288 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 289 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 290
 291 #define MSR_IA32_SYSENTER_CS            0x174
 292 #define MSR_IA32_SYSENTER_ESP           0x175
 293 #define MSR_IA32_SYSENTER_EIP           0x176
 294
 295 #define MSR_MCG_CAP                     0x179
 296 #define MSR_MCG_STATUS                  0x17a
 297 #define MSR_MCG_CTL                     0x17b
 298
 299 #define MSR_IA32_PERF_STATUS            0x198
 300
 301 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 302 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 303
 304 #define MSR_MTRRfix64K_00000            0x250
 305 #define MSR_MTRRfix16K_80000            0x258
 306 #define MSR_MTRRfix16K_A0000            0x259
 307 #define MSR_MTRRfix4K_C0000             0x268
 308 #define MSR_MTRRfix4K_C8000             0x269
 309 #define MSR_MTRRfix4K_D0000             0x26a
 310 #define MSR_MTRRfix4K_D8000             0x26b
 311 #define MSR_MTRRfix4K_E0000             0x26c
 312 #define MSR_MTRRfix4K_E8000             0x26d
 313 #define MSR_MTRRfix4K_F0000             0x26e
 314 #define MSR_MTRRfix4K_F8000             0x26f
 315
 316 #define MSR_PAT                         0x277
 317
 318 #define MSR_MTRRdefType                 0x2ff
 319
 320 #define MSR_MC0_CTL                     0x400
 321 #define MSR_MC0_STATUS                  0x401
 322 #define MSR_MC0_ADDR                    0x402
 323 #define MSR_MC0_MISC                    0x403
 324
 325 #define MSR_EFER                        0xc0000080
 326
 327 #define MSR_EFER_SCE   (1 << 0)
 328 #define MSR_EFER_LME   (1 << 8)
 329 #define MSR_EFER_LMA   (1 << 10)
 330 #define MSR_EFER_NXE   (1 << 11)
 331 #define MSR_EFER_SVME  (1 << 12)
 332 #define MSR_EFER_FFXSR (1 << 14)
 333
 334 #define MSR_STAR                        0xc0000081
 335 #define MSR_LSTAR                       0xc0000082
 336 #define MSR_CSTAR                       0xc0000083
 337 #define MSR_FMASK                       0xc0000084
 338 #define MSR_FSBASE                      0xc0000100
 339 #define MSR_GSBASE                      0xc0000101
 340 #define MSR_KERNELGSBASE                0xc0000102
 341 #define MSR_TSC_AUX                     0xc0000103
 342
 343 #define MSR_VM_HSAVE_PA                 0xc0010117
 344
 345 /* cpuid_features bits */
 346 #define CPUID_FP87 (1 << 0)
 347 #define CPUID_VME  (1 << 1)
 348 #define CPUID_DE   (1 << 2)
 349 #define CPUID_PSE  (1 << 3)
 350 #define CPUID_TSC  (1 << 4)
 351 #define CPUID_MSR  (1 << 5)
 352 #define CPUID_PAE  (1 << 6)
 353 #define CPUID_MCE  (1 << 7)
 354 #define CPUID_CX8  (1 << 8)
 355 #define CPUID_APIC (1 << 9)
 356 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 357 #define CPUID_MTRR (1 << 12)
 358 #define CPUID_PGE  (1 << 13)
 359 #define CPUID_MCA  (1 << 14)
 360 #define CPUID_CMOV (1 << 15)
 361 #define CPUID_PAT  (1 << 16)
 362 #define CPUID_PSE36   (1 << 17)
 363 #define CPUID_PN   (1 << 18)
 364 #define CPUID_CLFLUSH (1 << 19)
 365 #define CPUID_DTS (1 << 21)
 366 #define CPUID_ACPI (1 << 22)
 367 #define CPUID_MMX  (1 << 23)
 368 #define CPUID_FXSR (1 << 24)
 369 #define CPUID_SSE  (1 << 25)
 370 #define CPUID_SSE2 (1 << 26)
 371 #define CPUID_SS (1 << 27)
 372 #define CPUID_HT (1 << 28)
 373 #define CPUID_TM (1 << 29)
 374 #define CPUID_IA64 (1 << 30)
 375 #define CPUID_PBE (1 << 31)
 376
 377 #define CPUID_EXT_SSE3     (1 << 0)
 378 #define CPUID_EXT_DTES64   (1 << 2)
 379 #define CPUID_EXT_MONITOR  (1 << 3)
 380 #define CPUID_EXT_DSCPL    (1 << 4)
 381 #define CPUID_EXT_VMX      (1 << 5)
 382 #define CPUID_EXT_SMX      (1 << 6)
 383 #define CPUID_EXT_EST      (1 << 7)
 384 #define CPUID_EXT_TM2      (1 << 8)
 385 #define CPUID_EXT_SSSE3    (1 << 9)
 386 #define CPUID_EXT_CID      (1 << 10)
 387 #define CPUID_EXT_CX16     (1 << 13)
 388 #define CPUID_EXT_XTPR     (1 << 14)
 389 #define CPUID_EXT_PDCM     (1 << 15)
 390 #define CPUID_EXT_DCA      (1 << 18)
 391 #define CPUID_EXT_SSE41    (1 << 19)
 392 #define CPUID_EXT_SSE42    (1 << 20)
 393 #define CPUID_EXT_X2APIC   (1 << 21)
 394 #define CPUID_EXT_MOVBE    (1 << 22)
 395 #define CPUID_EXT_POPCNT   (1 << 23)
 396 #define CPUID_EXT_XSAVE    (1 << 26)
 397 #define CPUID_EXT_OSXSAVE  (1 << 27)
 398 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 399
 400 #define CPUID_EXT2_SYSCALL (1 << 11)
 401 #define CPUID_EXT2_MP      (1 << 19)
 402 #define CPUID_EXT2_NX      (1 << 20)
 403 #define CPUID_EXT2_MMXEXT  (1 << 22)
 404 #define CPUID_EXT2_FFXSR   (1 << 25)
 405 #define CPUID_EXT2_PDPE1GB (1 << 26)
 406 #define CPUID_EXT2_RDTSCP  (1 << 27)
 407 #define CPUID_EXT2_LM      (1 << 29)
 408 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 409 #define CPUID_EXT2_3DNOW   (1 << 31)
 410
 411 #define CPUID_EXT3_LAHF_LM (1 << 0)
 412 #define CPUID_EXT3_CMP_LEG (1 << 1)
 413 #define CPUID_EXT3_SVM     (1 << 2)
 414 #define CPUID_EXT3_EXTAPIC (1 << 3)
 415 #define CPUID_EXT3_CR8LEG  (1 << 4)
 416 #define CPUID_EXT3_ABM     (1 << 5)
 417 #define CPUID_EXT3_SSE4A   (1 << 6)
 418 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 419 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 420 #define CPUID_EXT3_OSVW    (1 << 9)
 421 #define CPUID_EXT3_IBS     (1 << 10)
 422 #define CPUID_EXT3_SKINIT  (1 << 12)
 423
 424 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 425 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 426 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 427
 428 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 429 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 430 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 431
 432 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 433 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 434
 435 #define EXCP00_DIVZ     0
 436 #define EXCP01_DB       1
 437 #define EXCP02_NMI      2
 438 #define EXCP03_INT3     3
 439 #define EXCP04_INTO     4
 440 #define EXCP05_BOUND    5
 441 #define EXCP06_ILLOP    6
 442 #define EXCP07_PREX     7
 443 #define EXCP08_DBLE     8
 444 #define EXCP09_XERR     9
 445 #define EXCP0A_TSS      10
 446 #define EXCP0B_NOSEG    11
 447 #define EXCP0C_STACK    12
 448 #define EXCP0D_GPF      13
 449 #define EXCP0E_PAGE     14
 450 #define EXCP10_COPR     16
 451 #define EXCP11_ALGN     17
 452 #define EXCP12_MCHK     18
 453
 454 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 455                                  for syscall instruction */
 456
 457 enum {
 458     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 459     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 460
 461     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 462     CC_OP_MULW,
 463     CC_OP_MULL,
 464     CC_OP_MULQ,
 465
 466     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 467     CC_OP_ADDW,
 468     CC_OP_ADDL,
 469     CC_OP_ADDQ,
 470
 471     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 472     CC_OP_ADCW,
 473     CC_OP_ADCL,
 474     CC_OP_ADCQ,
 475
 476     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 477     CC_OP_SUBW,
 478     CC_OP_SUBL,
 479     CC_OP_SUBQ,
 480
 481     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 482     CC_OP_SBBW,
 483     CC_OP_SBBL,
 484     CC_OP_SBBQ,
 485
 486     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 487     CC_OP_LOGICW,
 488     CC_OP_LOGICL,
 489     CC_OP_LOGICQ,
 490
 491     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 492     CC_OP_INCW,
 493     CC_OP_INCL,
 494     CC_OP_INCQ,
 495
 496     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 497     CC_OP_DECW,
 498     CC_OP_DECL,
 499     CC_OP_DECQ,
 500
 501     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 502     CC_OP_SHLW,
 503     CC_OP_SHLL,
 504     CC_OP_SHLQ,
 505
 506     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 507     CC_OP_SARW,
 508     CC_OP_SARL,
 509     CC_OP_SARQ,
 510
 511     CC_OP_NB,
 512 };
 513
 514 #ifdef FLOATX80
 515 #define USE_X86LDOUBLE
 516 #endif
 517
 518 #ifdef USE_X86LDOUBLE
 519 typedef floatx80 CPU86_LDouble;
 520 #else
 521 typedef float64 CPU86_LDouble;
 522 #endif
 523
 524 typedef struct SegmentCache {
 525     uint32_t selector;
 526     target_ulong base;
 527     uint32_t limit;
 528     uint32_t flags;
 529 } SegmentCache;
 530
 531 typedef union {
 532     uint8_t _b[16];
 533     uint16_t _w[8];
 534     uint32_t _l[4];
 535     uint64_t _q[2];
 536     float32 _s[4];
 537     float64 _d[2];
 538 } XMMReg;
 539
 540 typedef union {
 541     uint8_t _b[8];
 542     uint16_t _w[4];
 543     uint32_t _l[2];
 544     float32 _s[2];
 545     uint64_t q;
 546 } MMXReg;
 547
 548 #ifdef HOST_WORDS_BIGENDIAN
 549 #define XMM_B(n) _b[15 - (n)]
 550 #define XMM_W(n) _w[7 - (n)]
 551 #define XMM_L(n) _l[3 - (n)]
 552 #define XMM_S(n) _s[3 - (n)]
 553 #define XMM_Q(n) _q[1 - (n)]
 554 #define XMM_D(n) _d[1 - (n)]
 555
 556 #define MMX_B(n) _b[7 - (n)]
 557 #define MMX_W(n) _w[3 - (n)]
 558 #define MMX_L(n) _l[1 - (n)]
 559 #define MMX_S(n) _s[1 - (n)]
 560 #else
 561 #define XMM_B(n) _b[n]
 562 #define XMM_W(n) _w[n]
 563 #define XMM_L(n) _l[n]
 564 #define XMM_S(n) _s[n]
 565 #define XMM_Q(n) _q[n]
 566 #define XMM_D(n) _d[n]
 567
 568 #define MMX_B(n) _b[n]
 569 #define MMX_W(n) _w[n]
 570 #define MMX_L(n) _l[n]
 571 #define MMX_S(n) _s[n]
 572 #endif
 573 #define MMX_Q(n) q
 574
 575 typedef union {
 576 #ifdef USE_X86LDOUBLE
 577     CPU86_LDouble d __attribute__((aligned(16)));
 578 #else
 579     CPU86_LDouble d;
 580 #endif
 581     MMXReg mmx;
 582 } FPReg;
 583
 584 typedef struct {
 585     uint64_t base;
 586     uint64_t mask;
 587 } MTRRVar;
 588
 589 #define CPU_NB_REGS64 16
 590 #define CPU_NB_REGS32 8
 591
 592 #ifdef TARGET_X86_64
 593 #define CPU_NB_REGS CPU_NB_REGS64
 594 #else
 595 #define CPU_NB_REGS CPU_NB_REGS32
 596 #endif
 597
 598 #define NB_MMU_MODES 2
 599
 600 typedef struct CPUX86State {
 601     /* standard registers */
 602     target_ulong regs[CPU_NB_REGS];
 603     target_ulong eip;
 604     target_ulong eflags; /* eflags register. During CPU emulation, CC
 605                         flags and DF are set to zero because they are
 606                         stored elsewhere */
 607
 608     /* emulator internal eflags handling */
 609     target_ulong cc_src;
 610     target_ulong cc_dst;
 611     uint32_t cc_op;
 612     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 613     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 614                         are known at translation time. */
 615     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 616
 617     /* segments */
 618     SegmentCache segs[6]; /* selector values */
 619     SegmentCache ldt;
 620     SegmentCache tr;
 621     SegmentCache gdt; /* only base and limit are used */
 622     SegmentCache idt; /* only base and limit are used */
 623
 624     target_ulong cr[5]; /* NOTE: cr1 is unused */
 625     int32_t a20_mask;
 626
 627     /* FPU state */
 628     unsigned int fpstt; /* top of stack index */
 629     uint16_t fpus;
 630     uint16_t fpuc;
 631     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 632     FPReg fpregs[8];
 633
 634     /* emulator internal variables */
 635     float_status fp_status;
 636     CPU86_LDouble ft0;
 637
 638     float_status mmx_status; /* for 3DNow! float ops */
 639     float_status sse_status;
 640     uint32_t mxcsr;
 641     XMMReg xmm_regs[CPU_NB_REGS];
 642     XMMReg xmm_t0;
 643     MMXReg mmx_t0;
 644     target_ulong cc_tmp; /* temporary for rcr/rcl */
 645
 646     /* sysenter registers */
 647     uint32_t sysenter_cs;
 648     target_ulong sysenter_esp;
 649     target_ulong sysenter_eip;
 650     uint64_t efer;
 651     uint64_t star;
 652
 653     uint64_t vm_hsave;
 654     uint64_t vm_vmcb;
 655     uint64_t tsc_offset;
 656     uint64_t intercept;
 657     uint16_t intercept_cr_read;
 658     uint16_t intercept_cr_write;
 659     uint16_t intercept_dr_read;
 660     uint16_t intercept_dr_write;
 661     uint32_t intercept_exceptions;
 662     uint8_t v_tpr;
 663
 664 #ifdef TARGET_X86_64
 665     target_ulong lstar;
 666     target_ulong cstar;
 667     target_ulong fmask;
 668     target_ulong kernelgsbase;
 669 #endif
 670     uint64_t system_time_msr;
 671     uint64_t wall_clock_msr;
 672
 673     uint64_t tsc;
 674
 675     uint64_t pat;
 676
 677     /* exception/interrupt handling */
 678     int error_code;
 679     int exception_is_int;
 680     target_ulong exception_next_eip;
 681     target_ulong dr[8]; /* debug registers */
 682     union {
 683         CPUBreakpoint *cpu_breakpoint[4];
 684         CPUWatchpoint *cpu_watchpoint[4];
 685     }; /* break/watchpoints for dr[0..3] */
 686     uint32_t smbase;
 687     int old_exception;  /* exception in flight */
 688
 689     CPU_COMMON
 690
 691     /* processor features (e.g. for CPUID insn) */
 692     uint32_t cpuid_level;
 693     uint32_t cpuid_vendor1;
 694     uint32_t cpuid_vendor2;
 695     uint32_t cpuid_vendor3;
 696     uint32_t cpuid_version;
 697     uint32_t cpuid_features;
 698     uint32_t cpuid_ext_features;
 699     uint32_t cpuid_xlevel;
 700     uint32_t cpuid_model[12];
 701     uint32_t cpuid_ext2_features;
 702     uint32_t cpuid_ext3_features;
 703     uint32_t cpuid_apic_id;
 704     int cpuid_vendor_override;
 705
 706     /* MTRRs */
 707     uint64_t mtrr_fixed[11];
 708     uint64_t mtrr_deftype;
 709     MTRRVar mtrr_var[8];
 710
 711     /* For KVM */
 712     uint64_t interrupt_bitmap[256 / 64];
 713     uint32_t mp_state;
 714
 715     /* in order to simplify APIC support, we leave this pointer to the
 716        user */
 717     struct APICState *apic_state;
 718
 719     uint64 mcg_cap;
 720     uint64 mcg_status;
 721     uint64 mcg_ctl;
 722     uint64 mce_banks[MCE_BANKS_DEF*4];
 723
 724     uint64_t tsc_aux;
 725
 726     /* vmstate */
 727     uint16_t fpus_vmstate;
 728     uint16_t fptag_vmstate;
 729     uint16_t fpregs_format_vmstate;
 730     int32_t pending_irq_vmstate;
 731 } CPUX86State;
 732
 733 CPUX86State *cpu_x86_init(const char *cpu_model);
 734 int cpu_x86_exec(CPUX86State *s);
 735 void cpu_x86_close(CPUX86State *s);
 736 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 737                                                  ...));
 738 int cpu_get_pic_interrupt(CPUX86State *s);
 739 /* MSDOS compatibility mode FPU exception support */
 740 void cpu_set_ferr(CPUX86State *s);
 741
 742 /* this function must always be used to load data in the segment
 743    cache: it synchronizes the hflags with the segment cache values */
 744 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 745                                           int seg_reg, unsigned int selector,
 746                                           target_ulong base,
 747                                           unsigned int limit,
 748                                           unsigned int flags)
 749 {
 750     SegmentCache *sc;
 751     unsigned int new_hflags;
 752
 753     sc = &env->segs[seg_reg];
 754     sc->selector = selector;
 755     sc->base = base;
 756     sc->limit = limit;
 757     sc->flags = flags;
 758
 759     /* update the hidden flags */
 760     {
 761         if (seg_reg == R_CS) {
 762 #ifdef TARGET_X86_64
 763             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 764                 /* long mode */
 765                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 766                 env->hflags &= ~(HF_ADDSEG_MASK);
 767             } else
 768 #endif
 769             {
 770                 /* legacy / compatibility case */
 771                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 772                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 773                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 774                     new_hflags;
 775             }
 776         }
 777         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 778             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 779         if (env->hflags & HF_CS64_MASK) {
 780             /* zero base assumed for DS, ES and SS in long mode */
 781         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 782                    (env->eflags & VM_MASK) ||
 783                    !(env->hflags & HF_CS32_MASK)) {
 784             /* XXX: try to avoid this test. The problem comes from the
 785                fact that is real mode or vm86 mode we only modify the
 786                'base' and 'selector' fields of the segment cache to go
 787                faster. A solution may be to force addseg to one in
 788                translate-i386.c. */
 789             new_hflags |= HF_ADDSEG_MASK;
 790         } else {
 791             new_hflags |= ((env->segs[R_DS].base |
 792                             env->segs[R_ES].base |
 793                             env->segs[R_SS].base) != 0) <<
 794                 HF_ADDSEG_SHIFT;
 795         }
 796         env->hflags = (env->hflags &
 797                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 798     }
 799 }
 800
 801 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
 802                             target_ulong *base, unsigned int *limit,
 803                             unsigned int *flags);
 804
 805 /* wrapper, just in case memory mappings must be changed */
 806 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 807 {
 808 #if HF_CPL_MASK == 3
 809     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 810 #else
 811 #error HF_CPL_MASK is hardcoded
 812 #endif
 813 }
 814
 815 /* op_helper.c */
 816 /* used for debug or cpu save/restore */
 817 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 818 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 819
 820 /* cpu-exec.c */
 821 /* the following helpers are only usable in user mode simulation as
 822    they can trigger unexpected exceptions */
 823 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 824 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 825 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 826
 827 /* you can call this signal handler from your SIGBUS and SIGSEGV
 828    signal handlers to inform the virtual CPU of exceptions. non zero
 829    is returned if the signal was handled by the virtual CPU.  */
 830 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 831                            void *puc);
 832
 833 /* helper.c */
 834 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
 835                              int is_write, int mmu_idx, int is_softmmu);
 836 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
 837 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 838 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
 839                    uint32_t *eax, uint32_t *ebx,
 840                    uint32_t *ecx, uint32_t *edx);
 841
 842 static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
 843 {
 844     return (dr7 >> (index * 2)) & 3;
 845 }
 846
 847 static inline int hw_breakpoint_type(unsigned long dr7, int index)
 848 {
 849     return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3;
 850 }
 851
 852 static inline int hw_breakpoint_len(unsigned long dr7, int index)
 853 {
 854     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3);
 855     return (len == 2) ? 8 : len + 1;
 856 }
 857
 858 void hw_breakpoint_insert(CPUX86State *env, int index);
 859 void hw_breakpoint_remove(CPUX86State *env, int index);
 860 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
 861
 862 /* will be suppressed */
 863 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 864 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
 865 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
 866
 867 /* hw/apic.c */
 868 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 869 uint64_t cpu_get_apic_base(CPUX86State *env);
 870 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 871 #ifndef NO_CPU_IO_DEFS
 872 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 873 #endif
 874
 875 /* hw/pc.c */
 876 void cpu_smm_update(CPUX86State *env);
 877 uint64_t cpu_get_tsc(CPUX86State *env);
 878
 879 /* used to debug */
 880 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 881 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 882
 883 #define TARGET_PAGE_BITS 12
 884
 885 #define cpu_init cpu_x86_init
 886 #define cpu_exec cpu_x86_exec
 887 #define cpu_gen_code cpu_x86_gen_code
 888 #define cpu_signal_handler cpu_x86_signal_handler
 889 #define cpu_list x86_cpu_list
 890
 891 #define CPU_SAVE_VERSION 12
 892
 893 /* MMU modes definitions */
 894 #define MMU_MODE0_SUFFIX _kernel
 895 #define MMU_MODE1_SUFFIX _user
 896 #define MMU_USER_IDX 1
 897 static inline int cpu_mmu_index (CPUState *env)
 898 {
 899     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 900 }
 901
 902 /* translate.c */
 903 void optimize_flags_init(void);
 904
 905 typedef struct CCTable {
 906     int (*compute_all)(void); /* return all the flags */
 907     int (*compute_c)(void);  /* return the C flag */
 908 } CCTable;
 909
 910 #if defined(CONFIG_USER_ONLY)
 911 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 912 {
 913     if (newsp)
 914         env->regs[R_ESP] = newsp;
 915     env->regs[R_EAX] = 0;
 916 }
 917 #endif
 918
 919 #include "cpu-all.h"
 920 #include "exec-all.h"
 921
 922 #include "svm.h"
 923
 924 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 925 {
 926     env->eip = tb->pc - tb->cs_base;
 927 }
 928
 929 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 930                                         target_ulong *cs_base, int *flags)
 931 {
 932     *cs_base = env->segs[R_CS].base;
 933     *pc = *cs_base + env->eip;
 934     *flags = env->hflags |
 935         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
 936 }
 937
 938 void apic_init_reset(CPUState *env);
 939 void apic_sipi(CPUState *env);
 940 void do_cpu_init(CPUState *env);
 941 void do_cpu_sipi(CPUState *env);
 942 #endif /* CPU_I386_H */