osf.h

   1 /*
   2 *****************************************************************************
   3 **                                                                          *
   4 **  Copyright © 1993, 1994                                                  *
   5 **  by Digital Equipment Corporation, Maynard, Massachusetts.               *
   6 **                                                                          *
   7 **  All Rights Reserved                                                     *
   8 **                                                                          *
   9 **  Permission  is  hereby  granted  to  use, copy, modify and distribute   *
  10 **  this  software  and  its  documentation,  in  both  source  code  and   *
  11 **  object  code  form,  and without fee, for the purpose of distribution   *
  12 **  of this software  or  modifications  of this software within products   *
  13 **  incorporating  an  integrated   circuit  implementing  Digital's  AXP   *
  14 **  architecture,  regardless  of the  source of such integrated circuit,   *
  15 **  provided that the  above copyright  notice and this permission notice   *
  16 **  appear  in  all copies,  and  that  the  name  of  Digital  Equipment   *
  17 **  Corporation  not  be  used  in advertising or publicity pertaining to   *
  18 **  distribution of the  document  or  software without specific, written   *
  19 **  prior permission.                                                       *
  20 **                                                                          *
  21 **  Digital  Equipment  Corporation   disclaims  all   warranties  and/or   *
  22 **  guarantees  with  regard  to  this  software,  including  all implied   *
  23 **  warranties of fitness for  a  particular purpose and merchantability,   *
  24 **  and makes  no  representations  regarding  the use of, or the results   *
  25 **  of the use of, the software and documentation in terms of correctness,  *
  26 **  accuracy,  reliability,  currentness  or  otherwise;  and you rely on   *
  27 **  the software, documentation and results solely at your own risk.        *
  28 **                                                                          *
  29 **  AXP is a trademark of Digital Equipment Corporation.                    *
  30 **                                                                          *
  31 *****************************************************************************
  32 */
  33
  34 /*
  35 **  Seg0 and Seg1 Virtual Address (VA) Format
  36 **
  37 **        Loc   Size    Name    Function
  38 **       -----  ----    ----    ---------------------------------
  39 **      <42:33>  10     SEG1    First level page table offset
  40 **      <32:23>  10     SEG2    Second level page table offset
  41 **      <22:13>  10     SEG3    Third level page table offset
  42 **      <12:00>  13     OFFSET  Byte within page offset
  43 */
  44
  45 #define VA_V_SEG1       33
  46 #define VA_M_SEG1       (0x3FF<<VA_V_SEG1)
  47 #define VA_V_SEG2       23
  48 #define VA_M_SEG2       (0x3FF<<VA_V_SEG2)
  49 #define VA_V_SEG3       13
  50 #define VA_M_SEG3       (0x3FF<<VA_V_SEG3)
  51 #define VA_V_OFFSET     0
  52 #define VA_M_OFFSET     0x1FFF
  53
  54 /*
  55 **  Virtual Address Options: 8K byte page size
  56 */
  57
  58 #define VA_S_SIZE       43
  59 #define VA_S_OFF        13
  60 #define VA_S_SEG        10
  61 #define VA_S_PAGE_SIZE  8192
  62
  63 /*
  64 **  Page Table Entry (PTE) Format
  65 **
  66 **       Extent Size    Name    Function
  67 **       ------ ----    ----    ---------------------------------
  68 **      <63:32>   32    PFN     Page Frame Number
  69 **      <31:16>   16    SW      Reserved for software
  70 **      <15:14>    2    RSV0    Reserved for hardware SBZ
  71 **         <13>    1    UWE     User Write Enable
  72 **         <12>    1    KWE     Kernel Write Enable
  73 **      <11:10>    2    RSV1    Reserved for hardware SBZ
  74 **          <9>    1    URE     User Read Enable
  75 **          <8>    1    KRE     Kernel Read Enable
  76 **          <7>    1    RSV2    Reserved for hardware SBZ
  77 **        <6:5>    2    GH      Granularity Hint
  78 **          <4>    1    ASM     Address Space Match
  79 **          <3>    1    FOE     Fault On Execute
  80 **          <2>    1    FOW     Fault On Write
  81 **          <1>    1    FOR     Fault On Read
  82 **          <0>    1    V       Valid
  83 */
  84
  85 #define PTE_V_PFN       32
  86 #define PTE_M_PFN       0xFFFFFFFF00000000
  87 #define PTE_V_SW        16
  88 #define PTE_M_SW        0x00000000FFFF0000
  89 #define PTE_V_UWE       13
  90 #define PTE_M_UWE       (1<<PTE_V_UWE)
  91 #define PTE_V_KWE       12
  92 #define PTE_M_KWE       (1<<PTE_V_KWE)
  93 #define PTE_V_URE       9
  94 #define PTE_M_URE       (1<<PTE_V_URE)
  95 #define PTE_V_KRE       8
  96 #define PTE_M_KRE       (1<<PTE_V_KRE)
  97 #define PTE_V_GH        5
  98 #define PTE_M_GH        (3<<PTE_V_GH)
  99 #define PTE_V_ASM       4
 100 #define PTE_M_ASM       (1<<PTE_V_ASM)
 101 #define PTE_V_FOE       3
 102 #define PTE_M_FOE       (1<<PTE_V_FOE)
 103 #define PTE_V_FOW       2
 104 #define PTE_M_FOW       (1<<PTE_V_FOW)
 105 #define PTE_V_FOR       1
 106 #define PTE_M_FOR       (1<<PTE_V_FOR)
 107 #define PTE_V_VALID     0
 108 #define PTE_M_VALID     (1<<PTE_V_VALID)
 109
 110 #define PTE_M_KSEG      0x1111
 111 #define PTE_M_PROT      0x3300
 112
 113 /*
 114 **  System Entry Instruction Fault (entIF) Constants:
 115 */
 116
 117 #define IF_K_BPT        0x0
 118 #define IF_K_BUGCHK     0x1
 119 #define IF_K_GENTRAP    0x2
 120 #define IF_K_FEN        0x3
 121 #define IF_K_OPCDEC     0x4
 122
 123 /*
 124 **  System Entry Hardware Interrupt (entInt) Constants:
 125 */
 126
 127 #define INT_K_IP        0x0
 128 #define INT_K_CLK       0x1
 129 #define INT_K_MCHK      0x2
 130 #define INT_K_DEV       0x3
 131 #define INT_K_PERF      0x4
 132
 133 /*
 134 **  System Entry MM Fault (entMM) Constants:
 135 */
 136
 137 #define MM_K_TNV        0x0
 138 #define MM_K_ACV        0x1
 139 #define MM_K_FOR        0x2
 140 #define MM_K_FOE        0x3
 141 #define MM_K_FOW        0x4
 142
 143 /*
 144 **  Process Control Block (PCB) Offsets:
 145 */
 146
 147 #define PCB_Q_KSP       0x0000
 148 #define PCB_Q_USP       0x0008
 149 #define PCB_Q_PTBR      0x0010
 150 #define PCB_L_PCC       0x0018
 151 #define PCB_L_ASN       0x001C
 152 #define PCB_Q_UNIQUE    0x0020
 153 #define PCB_Q_FEN       0x0028
 154 #define PCB_Q_RSV0      0x0030
 155 #define PCB_Q_RSV1      0x0038
 156
 157 /*
 158 **  Processor Status Register (PS) Bit Summary
 159 **
 160 **      Extent  Size    Name    Function
 161 **      ------  ----    ----    ---------------------------------
 162 **        <3>    1      CM      Current Mode
 163 **      <2:0>    3      IPL     Interrupt Priority Level
 164 **/
 165
 166 #define PS_V_CM         3
 167 #define PS_M_CM         (1<<PS_V_CM)
 168 #define PS_V_IPL        0
 169 #define PS_M_IPL        (7<<PS_V_IPL)
 170
 171 #define PS_K_KERN       (0<<PS_V_CM)
 172 #define PS_K_USER       (1<<PS_V_CM)
 173
 174 #define IPL_K_ZERO      0x0
 175 #define IPL_K_SW0       0x1
 176 #define IPL_K_SW1       0x2
 177 #define IPL_K_DEV0      0x3
 178 #define IPL_K_DEV1      0x4
 179 #define IPL_K_CLK       0x5
 180 #define IPL_K_IP        0x6
 181 #define IPL_K_RT        0x6
 182 #define IPL_K_PERF      0x6
 183 #define IPL_K_PFAIL     0x6
 184 #define IPL_K_MCHK      0x7
 185
 186 #define IPL_K_LOW       0x0
 187 #define IPL_K_HIGH      0x7
 188
 189 /*
 190 **  SCB Offset Definitions:
 191 */
 192
 193 #define SCB_Q_FEN               0x0010
 194 #define SCB_Q_ACV               0x0080
 195 #define SCB_Q_TNV               0x0090
 196 #define SCB_Q_FOR               0x00A0
 197 #define SCB_Q_FOW               0x00B0
 198 #define SCB_Q_FOE               0x00C0
 199 #define SCB_Q_ARITH             0x0200
 200 #define SCB_Q_KAST              0x0240
 201 #define SCB_Q_EAST              0x0250
 202 #define SCB_Q_SAST              0x0260
 203 #define SCB_Q_UAST              0x0270
 204 #define SCB_Q_UNALIGN           0x0280
 205 #define SCB_Q_BPT               0x0400
 206 #define SCB_Q_BUGCHK            0x0410
 207 #define SCB_Q_OPCDEC            0x0420
 208 #define SCB_Q_ILLPAL            0x0430
 209 #define SCB_Q_TRAP              0x0440
 210 #define SCB_Q_CHMK              0x0480
 211 #define SCB_Q_CHME              0x0490
 212 #define SCB_Q_CHMS              0x04A0
 213 #define SCB_Q_CHMU              0x04B0
 214 #define SCB_Q_SW0               0x0500
 215 #define SCB_Q_SW1               0x0510
 216 #define SCB_Q_SW2               0x0520
 217 #define SCB_Q_SW3               0x0530
 218 #define SCB_Q_SW4               0x0540
 219 #define SCB_Q_SW5               0x0550
 220 #define SCB_Q_SW6               0x0560
 221 #define SCB_Q_SW7               0x0570
 222 #define SCB_Q_SW8               0x0580
 223 #define SCB_Q_SW9               0x0590
 224 #define SCB_Q_SW10              0x05A0
 225 #define SCB_Q_SW11              0x05B0
 226 #define SCB_Q_SW12              0x05C0
 227 #define SCB_Q_SW13              0x05D0
 228 #define SCB_Q_SW14              0x05E0
 229 #define SCB_Q_SW15              0x05F0
 230 #define SCB_Q_CLOCK             0x0600
 231 #define SCB_Q_INTER             0x0610
 232 #define SCB_Q_SYSERR            0x0620
 233 #define SCB_Q_PROCERR           0x0630
 234 #define SCB_Q_PWRFAIL           0x0640
 235 #define SCB_Q_PERFMON           0x0650
 236 #define SCB_Q_SYSMCHK           0x0660
 237 #define SCB_Q_PROCMCHK          0x0670
 238 #define SCB_Q_PASSREL           0x0680
 239
 240 /*
 241 **  Stack Frame (FRM) Offsets:
 242 **
 243 **  There are two types of system entries for OSF/1 - those for the
 244 **  callsys CALL_PAL function and those for exceptions and interrupts.
 245 **  Both entry types use the same stack frame layout.  The stack frame
 246 **  contains space for the PC, the PS, the saved GP, and the saved
 247 **  argument registers a0, a1, and a2.  On entry, SP points to the
 248 **  saved PS.
 249 */
 250
 251 #define FRM_Q_PS        0x0000
 252 #define FRM_Q_PC        0x0008
 253 #define FRM_Q_GP        0x0010
 254 #define FRM_Q_A0        0x0018
 255 #define FRM_Q_A1        0x0020
 256 #define FRM_Q_A2        0x0028
 257
 258 #define FRM_K_SIZE      48
 259
 260 /*
 261 **  Halt Codes:
 262 */
 263
 264 #define HLT_K_RESET         0x0000
 265 #define HLT_K_HW_HALT       0x0001
 266 #define HLT_K_KSP_INVAL     0x0002
 267 #define HLT_K_SCBB_INVAL    0x0003
 268 #define HLT_K_PTBR_INVAL    0x0004
 269 #define HLT_K_SW_HALT       0x0005
 270 #define HLT_K_DBL_MCHK      0x0006
 271 #define HLT_K_MCHK_FROM_PAL 0x0007
 272
 273 /*
 274 **  Machine Check Codes:
 275 */
 276
 277 #define MCHK_K_TPERR        0x0080
 278 #define MCHK_K_TCPERR       0x0082
 279 #define MCHK_K_HERR         0x0084
 280 #define MCHK_K_ECC_C        0x0086
 281 #define MCHK_K_ECC_NC       0x0088
 282 #define MCHK_K_UNKNOWN      0x008A
 283 #define MCHK_K_CACKSOFT     0x008C
 284 #define MCHK_K_BUGCHECK     0x008E
 285 #define MCHK_K_OS_BUGCHECK  0x0090
 286 #define MCHK_K_DCPERR       0x0092
 287 #define MCHK_K_ICPERR       0x0094
 288 #define MCHK_K_RETRY_IRD    0x0096
 289 #define MCHK_K_PROC_HERR    0x0098
 290
 291 /*
 292 ** System Machine Check Codes:
 293 */
 294
 295 #define MCHK_K_READ_NXM     0x0200
 296 #define MCHK_K_SYS_HERR     0x0202
 297
 298 /*
 299 **  Machine Check Error Status Summary (MCES) Register Format
 300 **
 301 **       Extent Size    Name    Function
 302 **       ------ ----    ----    ---------------------------------
 303 **        <0>     1     MIP     Machine check in progress
 304 **        <1>     1     SCE     System correctable error in progress
 305 **        <2>     1     PCE     Processor correctable error in progress
 306 **        <3>     1     DPC     Disable PCE error reporting
 307 **        <4>     1     DSC     Disable SCE error reporting
 308 */
 309
 310 #define MCES_V_MIP      0
 311 #define MCES_M_MIP      (1<<MCES_V_MIP)
 312 #define MCES_V_SCE      1
 313 #define MCES_M_SCE      (1<<MCES_V_SCE)
 314 #define MCES_V_PCE      2
 315 #define MCES_M_PCE      (1<<MCES_V_PCE)
 316 #define MCES_V_DPC      3
 317 #define MCES_M_DPC      (1<<MCES_V_DPC)
 318 #define MCES_V_DSC      4
 319 #define MCES_M_DSC      (1<<MCES_V_DSC)
 320
 321 #define MCES_M_ALL      (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
 322                          | MCES_M_DSC)
 323
 324 /*
 325 **  Who-Am-I (WHAMI) Register Format
 326 **
 327 **       Extent Size    Name    Function
 328 **       ------ ----    ----    ---------------------------------
 329 **        <7:0>   8     ID      Who-Am-I identifier
 330 **        <15:8>   1    SWAP    Swap PALcode flag - character 'S'
 331 */
 332
 333 #define WHAMI_V_SWAP    8
 334 #define WHAMI_M_SWAP    (1<<WHAMI_V_SWAP)
 335 #define WHAMI_V_ID      0
 336 #define WHAMI_M_ID      0xFF
 337
 338 #define WHAMI_K_SWAP    0x53    /* Character 'S' */
 339
 340 /*
 341  * OSF/1 PAL-code-imposed page table bits
 342  */
 343 #define _PAGE_VALID     0x0001
 344 #define _PAGE_FOR       0x0002  /* used for page protection (fault on read) */
 345 #define _PAGE_FOW       0x0004  /* used for page protection (fault on write) */
 346 #define _PAGE_FOE       0x0008  /* used for page protection (fault on exec) */
 347 #define _PAGE_ASM       0x0010
 348 #define _PAGE_KRE       0x0100  /* xxx - see below on the "accessed" bit */
 349 #define _PAGE_URE       0x0200  /* xxx */
 350 #define _PAGE_KWE       0x1000  /* used to do the dirty bit in software */
 351 #define _PAGE_UWE       0x2000  /* used to do the dirty bit in software */