1 # OpenSBI boot test for RISC-V machines
3 # Copyright (c) 2022, Ventana Micro
5 # This work is licensed under the terms of the GNU GPL, version 2 or
6 # later. See the COPYING file in the top-level directory.
8 from avocado_qemu
import QemuSystemTest
9 from avocado
import skip
10 from avocado_qemu
import wait_for_console_pattern
12 class RiscvOpenSBI(QemuSystemTest
):
14 :avocado: tags=accel:tcg
18 def boot_opensbi(self
):
21 wait_for_console_pattern(self
, 'Platform Name')
22 wait_for_console_pattern(self
, 'Boot HART MEDELEG')
24 @skip("requires OpenSBI fix to work")
25 def test_riscv32_spike(self
):
27 :avocado: tags=arch:riscv32
28 :avocado: tags=machine:spike
32 def test_riscv64_spike(self
):
34 :avocado: tags=arch:riscv64
35 :avocado: tags=machine:spike
39 def test_riscv32_sifive_u(self
):
41 :avocado: tags=arch:riscv32
42 :avocado: tags=machine:sifive_u
46 def test_riscv64_sifive_u(self
):
48 :avocado: tags=arch:riscv64
49 :avocado: tags=machine:sifive_u
53 def test_riscv32_virt(self
):
55 :avocado: tags=arch:riscv32
56 :avocado: tags=machine:virt
60 def test_riscv64_virt(self
):
62 :avocado: tags=arch:riscv64
63 :avocado: tags=machine:virt