tests/tcg/aarch64/sysregs.c

   1 /*
   2  * Check emulated system register access for linux-user mode.
   3  *
   4  * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt
   5  *
   6  * Copyright (c) 2019 Linaro
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  *
  11  * SPDX-License-Identifier: GPL-2.0-or-later
  12  */
  13
  14 #include <asm/hwcap.h>
  15 #include <stdio.h>
  16 #include <sys/auxv.h>
  17 #include <signal.h>
  18 #include <string.h>
  19 #include <stdbool.h>
  20
  21 #ifndef HWCAP_CPUID
  22 #define HWCAP_CPUID (1 << 11)
  23 #endif
  24
  25 /*
  26  * Older assemblers don't recognize newer system register names,
  27  * but we can still access them by the Sn_n_Cn_Cn_n syntax.
  28  */
  29 #define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
  30 #define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
  31
  32 int failed_bit_count;
  33
  34 /* Read and print system register `id' value */
  35 #define get_cpu_reg(id) ({                                      \
  36             unsigned long __val = 0xdeadbeef;                   \
  37             asm("mrs %0, "#id : "=r" (__val));                  \
  38             printf("%-20s: 0x%016lx\n", #id, __val);            \
  39             __val;                                               \
  40         })
  41
  42 /* As above but also check no bits outside of `mask' are set*/
  43 #define get_cpu_reg_check_mask(id, mask) ({                     \
  44             unsigned long __cval = get_cpu_reg(id);             \
  45             unsigned long __extra = __cval & ~mask;             \
  46             if (__extra) {                                      \
  47                 printf("%-20s: 0x%016lx\n", "  !!extra bits!!", __extra);   \
  48                 failed_bit_count++;                            \
  49             }                                                   \
  50 })
  51
  52 /* As above but check RAZ */
  53 #define get_cpu_reg_check_zero(id) ({                           \
  54             unsigned long __val = 0xdeadbeef;                   \
  55             asm("mrs %0, "#id : "=r" (__val));                  \
  56             if (__val) {                                        \
  57                 printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val);        \
  58                 failed_bit_count++;                            \
  59             }                                                   \
  60 })
  61
  62 /* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */
  63 #define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL)
  64
  65 bool should_fail;
  66 int should_fail_count;
  67 int should_not_fail_count;
  68 uintptr_t failed_pc[10];
  69
  70 void sigill_handler(int signo, siginfo_t *si, void *data)
  71 {
  72     ucontext_t *uc = (ucontext_t *)data;
  73
  74     if (should_fail) {
  75         should_fail_count++;
  76     } else {
  77         uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc;
  78         failed_pc[should_not_fail_count++] =  pc;
  79     }
  80     uc->uc_mcontext.pc += 4;
  81 }
  82
  83 int main(void)
  84 {
  85     struct sigaction sa;
  86
  87     /* Hook in a SIGILL handler */
  88     memset(&sa, 0, sizeof(struct sigaction));
  89     sa.sa_flags = SA_SIGINFO;
  90     sa.sa_sigaction = &sigill_handler;
  91     sigemptyset(&sa.sa_mask);
  92
  93     if (sigaction(SIGILL, &sa, 0) != 0) {
  94         perror("sigaction");
  95         return 1;
  96     }
  97
  98     /* Counter values have been exposed since Linux 4.12 */
  99     printf("Checking Counter registers\n");
 100
 101     get_cpu_reg(ctr_el0);
 102     get_cpu_reg(cntvct_el0);
 103     get_cpu_reg(cntfrq_el0);
 104
 105     /* HWCAP_CPUID indicates we can read feature registers, since Linux 4.11 */
 106     if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
 107         printf("CPUID registers unavailable\n");
 108         return 1;
 109     } else {
 110         printf("Checking CPUID registers\n");
 111     }
 112
 113     /*
 114      * Some registers only expose some bits to user-space. Anything
 115      * that is IMPDEF is exported as 0 to user-space. The _mask checks
 116      * assert no extra bits are set.
 117      *
 118      * This check is *not* comprehensive as some fields are set to
 119      * minimum valid fields - for the purposes of this check allowed
 120      * to have non-zero values.
 121      */
 122     get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
 123     get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
 124     get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
 125     /* TGran4 & TGran64 as pegged to -1 */
 126     get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
 127     get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
 128     get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000));
 129     /* EL1/EL0 reported as AA64 only */
 130     get_cpu_reg_check_mask(id_aa64pfr0_el1,  _m(000f,000f,00ff,0011));
 131     get_cpu_reg_check_mask(id_aa64pfr1_el1,  _m(0000,0000,0f00,0fff));
 132     /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
 133     get_cpu_reg_check_mask(id_aa64dfr0_el1,  _m(0000,0000,0000,0006));
 134     get_cpu_reg_check_zero(id_aa64dfr1_el1);
 135     get_cpu_reg_check_mask(id_aa64zfr0_el1,  _m(0ff0,ff0f,00ff,00ff));
 136 #ifdef HAS_ARMV9_SME
 137     get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
 138 #endif
 139
 140     get_cpu_reg_check_zero(id_aa64afr0_el1);
 141     get_cpu_reg_check_zero(id_aa64afr1_el1);
 142
 143     get_cpu_reg_check_mask(midr_el1,         _m(0000,0000,ffff,ffff));
 144     /* mpidr sets bit 31, everything else hidden */
 145     get_cpu_reg_check_mask(mpidr_el1,        _m(0000,0000,8000,0000));
 146     /* REVIDR is all IMPDEF so should be all zeros to user-space */
 147     get_cpu_reg_check_zero(revidr_el1);
 148
 149     /*
 150      * There are a block of more registers that are RAZ in the rest of
 151      * the Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 space. However for
 152      * brevity we don't check stuff that is currently un-allocated
 153      * here. Feel free to add them ;-)
 154      */
 155
 156     printf("Remaining registers should fail\n");
 157     should_fail = true;
 158
 159     /* Unexposed register access causes SIGILL */
 160     get_cpu_reg(id_mmfr0_el1);
 161     get_cpu_reg(id_mmfr1_el1);
 162     get_cpu_reg(id_mmfr2_el1);
 163     get_cpu_reg(id_mmfr3_el1);
 164
 165     get_cpu_reg(mvfr0_el1);
 166     get_cpu_reg(mvfr1_el1);
 167
 168     if (should_not_fail_count > 0) {
 169         int i;
 170         for (i = 0; i < should_not_fail_count; i++) {
 171             uintptr_t pc = failed_pc[i];
 172             uint32_t insn = *(uint32_t *) pc;
 173             printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc);
 174         }
 175         return 1;
 176     }
 177
 178     if (failed_bit_count > 0) {
 179         printf("Extra information leaked to user-space!\n");
 180         return 1;
 181     }
 182
 183     return should_fail_count == 6 ? 0 : 1;
 184 }