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pci: pci.h cleanup: move out stuff not in pci.c
[qemu/agraf.git] / hw / vmware_vga.c
blobbb3410105fb0f01122a3df0929684bc47db6523e
1 /*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "console.h"
26 #include "pci.h"
27 #include "vmware_vga.h"
28
29 #define VERBOSE
30 #undef DIRECT_VRAM
31 #define HW_RECT_ACCEL
32 #define HW_FILL_ACCEL
33 #define HW_MOUSE_ACCEL
34
35 # include "vga_int.h"
36
37 struct vmsvga_state_s {
38 VGACommonState vga;
39
40 int width;
41 int height;
42 int invalidated;
43 int depth;
44 int bypp;
45 int enable;
46 int config;
47 struct {
48 int id;
49 int x;
50 int y;
51 int on;
52 } cursor;
53
54 target_phys_addr_t vram_base;
55
56 int index;
57 int scratch_size;
58 uint32_t *scratch;
59 int new_width;
60 int new_height;
61 uint32_t guest;
62 uint32_t svgaid;
63 uint32_t wred;
64 uint32_t wgreen;
65 uint32_t wblue;
66 int syncing;
67 int fb_size;
68
69 union {
70 uint32_t *fifo;
71 struct __attribute__((__packed__)) {
72 uint32_t min;
73 uint32_t max;
74 uint32_t next_cmd;
75 uint32_t stop;
76 /* Add registers here when adding capabilities. */
77 uint32_t fifo[0];
78 } *cmd;
79 };
80
81 #define REDRAW_FIFO_LEN 512
82 struct vmsvga_rect_s {
83 int x, y, w, h;
84 } redraw_fifo[REDRAW_FIFO_LEN];
85 int redraw_fifo_first, redraw_fifo_last;
86 };
87
88 struct pci_vmsvga_state_s {
89 PCIDevice card;
90 struct vmsvga_state_s chip;
91 };
92
93 #define SVGA_MAGIC 0x900000UL
94 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
95 #define SVGA_ID_0 SVGA_MAKE_ID(0)
96 #define SVGA_ID_1 SVGA_MAKE_ID(1)
97 #define SVGA_ID_2 SVGA_MAKE_ID(2)
98
99 #define SVGA_LEGACY_BASE_PORT 0x4560
100 #define SVGA_INDEX_PORT 0x0
101 #define SVGA_VALUE_PORT 0x1
102 #define SVGA_BIOS_PORT 0x2
103
104 #define SVGA_VERSION_2
105
106 #ifdef SVGA_VERSION_2
107 # define SVGA_ID SVGA_ID_2
108 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
109 # define SVGA_IO_MUL 1
110 # define SVGA_FIFO_SIZE 0x10000
111 # define SVGA_MEM_BASE 0xe0000000
112 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
113 #else
114 # define SVGA_ID SVGA_ID_1
115 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
116 # define SVGA_IO_MUL 4
117 # define SVGA_FIFO_SIZE 0x10000
118 # define SVGA_MEM_BASE 0xe0000000
119 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
120 #endif
121
122 enum {
123 /* ID 0, 1 and 2 registers */
124 SVGA_REG_ID = 0,
125 SVGA_REG_ENABLE = 1,
126 SVGA_REG_WIDTH = 2,
127 SVGA_REG_HEIGHT = 3,
128 SVGA_REG_MAX_WIDTH = 4,
129 SVGA_REG_MAX_HEIGHT = 5,
130 SVGA_REG_DEPTH = 6,
131 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
132 SVGA_REG_PSEUDOCOLOR = 8,
133 SVGA_REG_RED_MASK = 9,
134 SVGA_REG_GREEN_MASK = 10,
135 SVGA_REG_BLUE_MASK = 11,
136 SVGA_REG_BYTES_PER_LINE = 12,
137 SVGA_REG_FB_START = 13,
138 SVGA_REG_FB_OFFSET = 14,
139 SVGA_REG_VRAM_SIZE = 15,
140 SVGA_REG_FB_SIZE = 16,
141
142 /* ID 1 and 2 registers */
143 SVGA_REG_CAPABILITIES = 17,
144 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
145 SVGA_REG_MEM_SIZE = 19,
146 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
147 SVGA_REG_SYNC = 21, /* Write to force synchronization */
148 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
149 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
150 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
151 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
152 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
153 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
154 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
155 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
156 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
157 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
158 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
159
160 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
161 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
162 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
163 };
164
165 #define SVGA_CAP_NONE 0
166 #define SVGA_CAP_RECT_FILL (1 << 0)
167 #define SVGA_CAP_RECT_COPY (1 << 1)
168 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
169 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
170 #define SVGA_CAP_RASTER_OP (1 << 4)
171 #define SVGA_CAP_CURSOR (1 << 5)
172 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
173 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
174 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
175 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
176 #define SVGA_CAP_GLYPH (1 << 10)
177 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
178 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
179 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
180 #define SVGA_CAP_3D (1 << 14)
181 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
182 #define SVGA_CAP_MULTIMON (1 << 16)
183 #define SVGA_CAP_PITCHLOCK (1 << 17)
184
185 /*
186 * FIFO offsets (seen as an array of 32-bit words)
187 */
188 enum {
189 /*
190 * The original defined FIFO offsets
191 */
192 SVGA_FIFO_MIN = 0,
193 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
194 SVGA_FIFO_NEXT_CMD,
195 SVGA_FIFO_STOP,
196
197 /*
198 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
199 */
200 SVGA_FIFO_CAPABILITIES = 4,
201 SVGA_FIFO_FLAGS,
202 SVGA_FIFO_FENCE,
203 SVGA_FIFO_3D_HWVERSION,
204 SVGA_FIFO_PITCHLOCK,
205 };
206
207 #define SVGA_FIFO_CAP_NONE 0
208 #define SVGA_FIFO_CAP_FENCE (1 << 0)
209 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
210 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
211
212 #define SVGA_FIFO_FLAG_NONE 0
213 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
214
215 /* These values can probably be changed arbitrarily. */
216 #define SVGA_SCRATCH_SIZE 0x8000
217 #define SVGA_MAX_WIDTH 2360
218 #define SVGA_MAX_HEIGHT 1770
219
220 #ifdef VERBOSE
221 # define GUEST_OS_BASE 0x5001
222 static const char *vmsvga_guest_id[] = {
223 [0x00] = "Dos",
224 [0x01] = "Windows 3.1",
225 [0x02] = "Windows 95",
226 [0x03] = "Windows 98",
227 [0x04] = "Windows ME",
228 [0x05] = "Windows NT",
229 [0x06] = "Windows 2000",
230 [0x07] = "Linux",
231 [0x08] = "OS/2",
232 [0x09] = "an unknown OS",
233 [0x0a] = "BSD",
234 [0x0b] = "Whistler",
235 [0x0c] = "an unknown OS",
236 [0x0d] = "an unknown OS",
237 [0x0e] = "an unknown OS",
238 [0x0f] = "an unknown OS",
239 [0x10] = "an unknown OS",
240 [0x11] = "an unknown OS",
241 [0x12] = "an unknown OS",
242 [0x13] = "an unknown OS",
243 [0x14] = "an unknown OS",
244 [0x15] = "Windows 2003",
245 };
246 #endif
247
248 enum {
249 SVGA_CMD_INVALID_CMD = 0,
250 SVGA_CMD_UPDATE = 1,
251 SVGA_CMD_RECT_FILL = 2,
252 SVGA_CMD_RECT_COPY = 3,
253 SVGA_CMD_DEFINE_BITMAP = 4,
254 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
255 SVGA_CMD_DEFINE_PIXMAP = 6,
256 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
257 SVGA_CMD_RECT_BITMAP_FILL = 8,
258 SVGA_CMD_RECT_PIXMAP_FILL = 9,
259 SVGA_CMD_RECT_BITMAP_COPY = 10,
260 SVGA_CMD_RECT_PIXMAP_COPY = 11,
261 SVGA_CMD_FREE_OBJECT = 12,
262 SVGA_CMD_RECT_ROP_FILL = 13,
263 SVGA_CMD_RECT_ROP_COPY = 14,
264 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
265 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
266 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
267 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
268 SVGA_CMD_DEFINE_CURSOR = 19,
269 SVGA_CMD_DISPLAY_CURSOR = 20,
270 SVGA_CMD_MOVE_CURSOR = 21,
271 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
272 SVGA_CMD_DRAW_GLYPH = 23,
273 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
274 SVGA_CMD_UPDATE_VERBOSE = 25,
275 SVGA_CMD_SURFACE_FILL = 26,
276 SVGA_CMD_SURFACE_COPY = 27,
277 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
278 SVGA_CMD_FRONT_ROP_FILL = 29,
279 SVGA_CMD_FENCE = 30,
280 };
281
282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
283 enum {
284 SVGA_CURSOR_ON_HIDE = 0,
285 SVGA_CURSOR_ON_SHOW = 1,
286 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
287 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
288 };
289
290 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
291 int x, int y, int w, int h)
292 {
293 #ifndef DIRECT_VRAM
294 int line;
295 int bypl;
296 int width;
297 int start;
298 uint8_t *src;
299 uint8_t *dst;
300
301 if (x + w > s->width) {
302 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
303 __FUNCTION__, x, w);
304 x = MIN(x, s->width);
305 w = s->width - x;
306 }
307
308 if (y + h > s->height) {
309 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
310 __FUNCTION__, y, h);
311 y = MIN(y, s->height);
312 h = s->height - y;
313 }
314
315 line = h;
316 bypl = s->bypp * s->width;
317 width = s->bypp * w;
318 start = s->bypp * x + bypl * y;
319 src = s->vga.vram_ptr + start;
320 dst = ds_get_data(s->vga.ds) + start;
321
322 for (; line > 0; line --, src += bypl, dst += bypl)
323 memcpy(dst, src, width);
324 #endif
325
326 dpy_update(s->vga.ds, x, y, w, h);
327 }
328
329 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
330 {
331 #ifndef DIRECT_VRAM
332 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
333 #endif
334
335 dpy_update(s->vga.ds, 0, 0, s->width, s->height);
336 }
337
338 #ifdef DIRECT_VRAM
339 # define vmsvga_update_rect_delayed vmsvga_update_rect
340 #else
341 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
342 int x, int y, int w, int h)
343 {
344 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
345 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
346 rect->x = x;
347 rect->y = y;
348 rect->w = w;
349 rect->h = h;
350 }
351 #endif
352
353 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
354 {
355 struct vmsvga_rect_s *rect;
356 if (s->invalidated) {
357 s->redraw_fifo_first = s->redraw_fifo_last;
358 return;
359 }
360 /* Overlapping region updates can be optimised out here - if someone
361 * knows a smart algorithm to do that, please share. */
362 while (s->redraw_fifo_first != s->redraw_fifo_last) {
363 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
364 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
365 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
366 }
367 }
368
369 #ifdef HW_RECT_ACCEL
370 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
371 int x0, int y0, int x1, int y1, int w, int h)
372 {
373 # ifdef DIRECT_VRAM
374 uint8_t *vram = ds_get_data(s->ds);
375 # else
376 uint8_t *vram = s->vga.vram_ptr;
377 # endif
378 int bypl = s->bypp * s->width;
379 int width = s->bypp * w;
380 int line = h;
381 uint8_t *ptr[2];
382
383 # ifdef DIRECT_VRAM
384 if (s->ds->dpy_copy)
385 qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
386 else
387 # endif
388 {
389 if (y1 > y0) {
390 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
391 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
392 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
393 memmove(ptr[1], ptr[0], width);
394 } else {
395 ptr[0] = vram + s->bypp * x0 + bypl * y0;
396 ptr[1] = vram + s->bypp * x1 + bypl * y1;
397 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
398 memmove(ptr[1], ptr[0], width);
399 }
400 }
401
402 vmsvga_update_rect_delayed(s, x1, y1, w, h);
403 }
404 #endif
405
406 #ifdef HW_FILL_ACCEL
407 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
408 uint32_t c, int x, int y, int w, int h)
409 {
410 # ifdef DIRECT_VRAM
411 uint8_t *vram = ds_get_data(s->ds);
412 # else
413 uint8_t *vram = s->vga.vram_ptr;
414 # endif
415 int bypp = s->bypp;
416 int bypl = bypp * s->width;
417 int width = bypp * w;
418 int line = h;
419 int column;
420 uint8_t *fst = vram + bypp * x + bypl * y;
421 uint8_t *dst;
422 uint8_t *src;
423 uint8_t col[4];
424
425 # ifdef DIRECT_VRAM
426 if (s->ds->dpy_fill)
427 s->ds->dpy_fill(s->ds, x, y, w, h, c);
428 else
429 # endif
430 {
431 col[0] = c;
432 col[1] = c >> 8;
433 col[2] = c >> 16;
434 col[3] = c >> 24;
435
436 if (line --) {
437 dst = fst;
438 src = col;
439 for (column = width; column > 0; column --) {
440 *(dst ++) = *(src ++);
441 if (src - col == bypp)
442 src = col;
443 }
444 dst = fst;
445 for (; line > 0; line --) {
446 dst += bypl;
447 memcpy(dst, fst, width);
448 }
449 }
450 }
451
452 vmsvga_update_rect_delayed(s, x, y, w, h);
453 }
454 #endif
455
456 struct vmsvga_cursor_definition_s {
457 int width;
458 int height;
459 int id;
460 int bpp;
461 int hot_x;
462 int hot_y;
463 uint32_t mask[1024];
464 uint32_t image[1024];
465 };
466
467 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
468 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
469
470 #ifdef HW_MOUSE_ACCEL
471 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
472 struct vmsvga_cursor_definition_s *c)
473 {
474 int i;
475 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
476 c->mask[i] = ~c->mask[i];
477
478 if (s->vga.ds->cursor_define)
479 s->vga.ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
480 (uint8_t *) c->image, (uint8_t *) c->mask);
481 }
482 #endif
483
484 #define CMD(f) le32_to_cpu(s->cmd->f)
485
486 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
487 {
488 if (!s->config || !s->enable)
489 return 1;
490 return (s->cmd->next_cmd == s->cmd->stop);
491 }
492
493 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
494 {
495 uint32_t cmd = s->fifo[CMD(stop) >> 2];
496 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
497 if (CMD(stop) >= CMD(max))
498 s->cmd->stop = s->cmd->min;
499 return cmd;
500 }
501
502 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
503 {
504 return le32_to_cpu(vmsvga_fifo_read_raw(s));
505 }
506
507 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
508 {
509 uint32_t cmd, colour;
510 int args = 0;
511 int x, y, dx, dy, width, height;
512 struct vmsvga_cursor_definition_s cursor;
513 while (!vmsvga_fifo_empty(s))
514 switch (cmd = vmsvga_fifo_read(s)) {
515 case SVGA_CMD_UPDATE:
516 case SVGA_CMD_UPDATE_VERBOSE:
517 x = vmsvga_fifo_read(s);
518 y = vmsvga_fifo_read(s);
519 width = vmsvga_fifo_read(s);
520 height = vmsvga_fifo_read(s);
521 vmsvga_update_rect_delayed(s, x, y, width, height);
522 break;
523
524 case SVGA_CMD_RECT_FILL:
525 colour = vmsvga_fifo_read(s);
526 x = vmsvga_fifo_read(s);
527 y = vmsvga_fifo_read(s);
528 width = vmsvga_fifo_read(s);
529 height = vmsvga_fifo_read(s);
530 #ifdef HW_FILL_ACCEL
531 vmsvga_fill_rect(s, colour, x, y, width, height);
532 break;
533 #else
534 goto badcmd;
535 #endif
536
537 case SVGA_CMD_RECT_COPY:
538 x = vmsvga_fifo_read(s);
539 y = vmsvga_fifo_read(s);
540 dx = vmsvga_fifo_read(s);
541 dy = vmsvga_fifo_read(s);
542 width = vmsvga_fifo_read(s);
543 height = vmsvga_fifo_read(s);
544 #ifdef HW_RECT_ACCEL
545 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
546 break;
547 #else
548 goto badcmd;
549 #endif
550
551 case SVGA_CMD_DEFINE_CURSOR:
552 cursor.id = vmsvga_fifo_read(s);
553 cursor.hot_x = vmsvga_fifo_read(s);
554 cursor.hot_y = vmsvga_fifo_read(s);
555 cursor.width = x = vmsvga_fifo_read(s);
556 cursor.height = y = vmsvga_fifo_read(s);
557 vmsvga_fifo_read(s);
558 cursor.bpp = vmsvga_fifo_read(s);
559 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
560 cursor.mask[args] = vmsvga_fifo_read_raw(s);
561 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
562 cursor.image[args] = vmsvga_fifo_read_raw(s);
563 #ifdef HW_MOUSE_ACCEL
564 vmsvga_cursor_define(s, &cursor);
565 break;
566 #else
567 args = 0;
568 goto badcmd;
569 #endif
570
571 /*
572 * Other commands that we at least know the number of arguments
573 * for so we can avoid FIFO desync if driver uses them illegally.
574 */
575 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
576 vmsvga_fifo_read(s);
577 vmsvga_fifo_read(s);
578 vmsvga_fifo_read(s);
579 x = vmsvga_fifo_read(s);
580 y = vmsvga_fifo_read(s);
581 args = x * y;
582 goto badcmd;
583 case SVGA_CMD_RECT_ROP_FILL:
584 args = 6;
585 goto badcmd;
586 case SVGA_CMD_RECT_ROP_COPY:
587 args = 7;
588 goto badcmd;
589 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
590 vmsvga_fifo_read(s);
591 vmsvga_fifo_read(s);
592 args = 7 + (vmsvga_fifo_read(s) >> 2);
593 goto badcmd;
594 case SVGA_CMD_SURFACE_ALPHA_BLEND:
595 args = 12;
596 goto badcmd;
597
598 /*
599 * Other commands that are not listed as depending on any
600 * CAPABILITIES bits, but are not described in the README either.
601 */
602 case SVGA_CMD_SURFACE_FILL:
603 case SVGA_CMD_SURFACE_COPY:
604 case SVGA_CMD_FRONT_ROP_FILL:
605 case SVGA_CMD_FENCE:
606 case SVGA_CMD_INVALID_CMD:
607 break; /* Nop */
608
609 default:
610 badcmd:
611 while (args --)
612 vmsvga_fifo_read(s);
613 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
614 __FUNCTION__, cmd);
615 break;
616 }
617
618 s->syncing = 0;
619 }
620
621 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
622 {
623 struct vmsvga_state_s *s = opaque;
624 return s->index;
625 }
626
627 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
628 {
629 struct vmsvga_state_s *s = opaque;
630 s->index = index;
631 }
632
633 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
634 {
635 uint32_t caps;
636 struct vmsvga_state_s *s = opaque;
637 switch (s->index) {
638 case SVGA_REG_ID:
639 return s->svgaid;
640
641 case SVGA_REG_ENABLE:
642 return s->enable;
643
644 case SVGA_REG_WIDTH:
645 return s->width;
646
647 case SVGA_REG_HEIGHT:
648 return s->height;
649
650 case SVGA_REG_MAX_WIDTH:
651 return SVGA_MAX_WIDTH;
652
653 case SVGA_REG_MAX_HEIGHT:
654 return SVGA_MAX_HEIGHT;
655
656 case SVGA_REG_DEPTH:
657 return s->depth;
658
659 case SVGA_REG_BITS_PER_PIXEL:
660 return (s->depth + 7) & ~7;
661
662 case SVGA_REG_PSEUDOCOLOR:
663 return 0x0;
664
665 case SVGA_REG_RED_MASK:
666 return s->wred;
667 case SVGA_REG_GREEN_MASK:
668 return s->wgreen;
669 case SVGA_REG_BLUE_MASK:
670 return s->wblue;
671
672 case SVGA_REG_BYTES_PER_LINE:
673 return ((s->depth + 7) >> 3) * s->new_width;
674
675 case SVGA_REG_FB_START:
676 return s->vram_base;
677
678 case SVGA_REG_FB_OFFSET:
679 return 0x0;
680
681 case SVGA_REG_VRAM_SIZE:
682 return s->vga.vram_size - SVGA_FIFO_SIZE;
683
684 case SVGA_REG_FB_SIZE:
685 return s->fb_size;
686
687 case SVGA_REG_CAPABILITIES:
688 caps = SVGA_CAP_NONE;
689 #ifdef HW_RECT_ACCEL
690 caps |= SVGA_CAP_RECT_COPY;
691 #endif
692 #ifdef HW_FILL_ACCEL
693 caps |= SVGA_CAP_RECT_FILL;
694 #endif
695 #ifdef HW_MOUSE_ACCEL
696 if (s->vga.ds->mouse_set)
697 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
698 SVGA_CAP_CURSOR_BYPASS;
699 #endif
700 return caps;
701
702 case SVGA_REG_MEM_START:
703 return s->vram_base + s->vga.vram_size - SVGA_FIFO_SIZE;
704
705 case SVGA_REG_MEM_SIZE:
706 return SVGA_FIFO_SIZE;
707
708 case SVGA_REG_CONFIG_DONE:
709 return s->config;
710
711 case SVGA_REG_SYNC:
712 case SVGA_REG_BUSY:
713 return s->syncing;
714
715 case SVGA_REG_GUEST_ID:
716 return s->guest;
717
718 case SVGA_REG_CURSOR_ID:
719 return s->cursor.id;
720
721 case SVGA_REG_CURSOR_X:
722 return s->cursor.x;
723
724 case SVGA_REG_CURSOR_Y:
725 return s->cursor.x;
726
727 case SVGA_REG_CURSOR_ON:
728 return s->cursor.on;
729
730 case SVGA_REG_HOST_BITS_PER_PIXEL:
731 return (s->depth + 7) & ~7;
732
733 case SVGA_REG_SCRATCH_SIZE:
734 return s->scratch_size;
735
736 case SVGA_REG_MEM_REGS:
737 case SVGA_REG_NUM_DISPLAYS:
738 case SVGA_REG_PITCHLOCK:
739 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
740 return 0;
741
742 default:
743 if (s->index >= SVGA_SCRATCH_BASE &&
744 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
745 return s->scratch[s->index - SVGA_SCRATCH_BASE];
746 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
747 }
748
749 return 0;
750 }
751
752 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
753 {
754 struct vmsvga_state_s *s = opaque;
755 switch (s->index) {
756 case SVGA_REG_ID:
757 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
758 s->svgaid = value;
759 break;
760
761 case SVGA_REG_ENABLE:
762 s->enable = value;
763 s->config &= !!value;
764 s->width = -1;
765 s->height = -1;
766 s->invalidated = 1;
767 s->vga.invalidate(&s->vga);
768 if (s->enable)
769 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
770 break;
771
772 case SVGA_REG_WIDTH:
773 s->new_width = value;
774 s->invalidated = 1;
775 break;
776
777 case SVGA_REG_HEIGHT:
778 s->new_height = value;
779 s->invalidated = 1;
780 break;
781
782 case SVGA_REG_DEPTH:
783 case SVGA_REG_BITS_PER_PIXEL:
784 if (value != s->depth) {
785 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
786 s->config = 0;
787 }
788 break;
789
790 case SVGA_REG_CONFIG_DONE:
791 if (value) {
792 s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
793 /* Check range and alignment. */
794 if ((CMD(min) | CMD(max) |
795 CMD(next_cmd) | CMD(stop)) & 3)
796 break;
797 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
798 break;
799 if (CMD(max) > SVGA_FIFO_SIZE)
800 break;
801 if (CMD(max) < CMD(min) + 10 * 1024)
802 break;
803 }
804 s->config = !!value;
805 break;
806
807 case SVGA_REG_SYNC:
808 s->syncing = 1;
809 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
810 break;
811
812 case SVGA_REG_GUEST_ID:
813 s->guest = value;
814 #ifdef VERBOSE
815 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
816 ARRAY_SIZE(vmsvga_guest_id))
817 printf("%s: guest runs %s.\n", __FUNCTION__,
818 vmsvga_guest_id[value - GUEST_OS_BASE]);
819 #endif
820 break;
821
822 case SVGA_REG_CURSOR_ID:
823 s->cursor.id = value;
824 break;
825
826 case SVGA_REG_CURSOR_X:
827 s->cursor.x = value;
828 break;
829
830 case SVGA_REG_CURSOR_Y:
831 s->cursor.y = value;
832 break;
833
834 case SVGA_REG_CURSOR_ON:
835 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
836 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
837 #ifdef HW_MOUSE_ACCEL
838 if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
839 s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
840 #endif
841 break;
842
843 case SVGA_REG_MEM_REGS:
844 case SVGA_REG_NUM_DISPLAYS:
845 case SVGA_REG_PITCHLOCK:
846 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
847 break;
848
849 default:
850 if (s->index >= SVGA_SCRATCH_BASE &&
851 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
852 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
853 break;
854 }
855 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
856 }
857 }
858
859 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
860 {
861 printf("%s: what are we supposed to return?\n", __FUNCTION__);
862 return 0xcafe;
863 }
864
865 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
866 {
867 printf("%s: what are we supposed to do with (%08x)?\n",
868 __FUNCTION__, data);
869 }
870
871 static inline void vmsvga_size(struct vmsvga_state_s *s)
872 {
873 if (s->new_width != s->width || s->new_height != s->height) {
874 s->width = s->new_width;
875 s->height = s->new_height;
876 qemu_console_resize(s->vga.ds, s->width, s->height);
877 s->invalidated = 1;
878 }
879 }
880
881 static void vmsvga_update_display(void *opaque)
882 {
883 struct vmsvga_state_s *s = opaque;
884 if (!s->enable) {
885 s->vga.update(&s->vga);
886 return;
887 }
888
889 vmsvga_size(s);
890
891 vmsvga_fifo_run(s);
892 vmsvga_update_rect_flush(s);
893
894 /*
895 * Is it more efficient to look at vram VGA-dirty bits or wait
896 * for the driver to issue SVGA_CMD_UPDATE?
897 */
898 if (s->invalidated) {
899 s->invalidated = 0;
900 vmsvga_update_screen(s);
901 }
902 }
903
904 static void vmsvga_reset(struct vmsvga_state_s *s)
905 {
906 s->index = 0;
907 s->enable = 0;
908 s->config = 0;
909 s->width = -1;
910 s->height = -1;
911 s->svgaid = SVGA_ID;
912 s->depth = 24;
913 s->bypp = (s->depth + 7) >> 3;
914 s->cursor.on = 0;
915 s->redraw_fifo_first = 0;
916 s->redraw_fifo_last = 0;
917 switch (s->depth) {
918 case 8:
919 s->wred = 0x00000007;
920 s->wgreen = 0x00000038;
921 s->wblue = 0x000000c0;
922 break;
923 case 15:
924 s->wred = 0x0000001f;
925 s->wgreen = 0x000003e0;
926 s->wblue = 0x00007c00;
927 break;
928 case 16:
929 s->wred = 0x0000001f;
930 s->wgreen = 0x000007e0;
931 s->wblue = 0x0000f800;
932 break;
933 case 24:
934 s->wred = 0x00ff0000;
935 s->wgreen = 0x0000ff00;
936 s->wblue = 0x000000ff;
937 break;
938 case 32:
939 s->wred = 0x00ff0000;
940 s->wgreen = 0x0000ff00;
941 s->wblue = 0x000000ff;
942 break;
943 }
944 s->syncing = 0;
945 }
946
947 static void vmsvga_invalidate_display(void *opaque)
948 {
949 struct vmsvga_state_s *s = opaque;
950 if (!s->enable) {
951 s->vga.invalidate(&s->vga);
952 return;
953 }
954
955 s->invalidated = 1;
956 }
957
958 /* save the vga display in a PPM image even if no display is
959 available */
960 static void vmsvga_screen_dump(void *opaque, const char *filename)
961 {
962 struct vmsvga_state_s *s = opaque;
963 if (!s->enable) {
964 s->vga.screen_dump(&s->vga, filename);
965 return;
966 }
967
968 if (s->depth == 32) {
969 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
970 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
971 ppm_save(filename, ds);
972 qemu_free(ds);
973 }
974 }
975
976 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
977 {
978 struct vmsvga_state_s *s = opaque;
979
980 if (s->vga.text_update)
981 s->vga.text_update(&s->vga, chardata);
982 }
983
984 #ifdef DIRECT_VRAM
985 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
986 {
987 struct vmsvga_state_s *s = opaque;
988 if (addr < s->fb_size)
989 return *(uint8_t *) (ds_get_data(s->ds) + addr);
990 else
991 return *(uint8_t *) (s->vram_ptr + addr);
992 }
993
994 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
995 {
996 struct vmsvga_state_s *s = opaque;
997 if (addr < s->fb_size)
998 return *(uint16_t *) (ds_get_data(s->ds) + addr);
999 else
1000 return *(uint16_t *) (s->vram_ptr + addr);
1001 }
1002
1003 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1004 {
1005 struct vmsvga_state_s *s = opaque;
1006 if (addr < s->fb_size)
1007 return *(uint32_t *) (ds_get_data(s->ds) + addr);
1008 else
1009 return *(uint32_t *) (s->vram_ptr + addr);
1010 }
1011
1012 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1013 uint32_t value)
1014 {
1015 struct vmsvga_state_s *s = opaque;
1016 if (addr < s->fb_size)
1017 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
1018 else
1019 *(uint8_t *) (s->vram_ptr + addr) = value;
1020 }
1021
1022 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1023 uint32_t value)
1024 {
1025 struct vmsvga_state_s *s = opaque;
1026 if (addr < s->fb_size)
1027 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
1028 else
1029 *(uint16_t *) (s->vram_ptr + addr) = value;
1030 }
1031
1032 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1033 uint32_t value)
1034 {
1035 struct vmsvga_state_s *s = opaque;
1036 if (addr < s->fb_size)
1037 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
1038 else
1039 *(uint32_t *) (s->vram_ptr + addr) = value;
1040 }
1041
1042 static CPUReadMemoryFunc * const vmsvga_vram_read[] = {
1043 vmsvga_vram_readb,
1044 vmsvga_vram_readw,
1045 vmsvga_vram_readl,
1046 };
1047
1048 static CPUWriteMemoryFunc * const vmsvga_vram_write[] = {
1049 vmsvga_vram_writeb,
1050 vmsvga_vram_writew,
1051 vmsvga_vram_writel,
1052 };
1053 #endif
1054
1055 static int vmsvga_post_load(void *opaque, int version_id)
1056 {
1057 struct vmsvga_state_s *s = opaque;
1058
1059 s->invalidated = 1;
1060 if (s->config)
1061 s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
1062
1063 return 0;
1064 }
1065
1066 const VMStateDescription vmstate_vmware_vga_internal = {
1067 .name = "vmware_vga_internal",
1068 .version_id = 0,
1069 .minimum_version_id = 0,
1070 .minimum_version_id_old = 0,
1071 .post_load = vmsvga_post_load,
1072 .fields = (VMStateField []) {
1073 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1074 VMSTATE_INT32(enable, struct vmsvga_state_s),
1075 VMSTATE_INT32(config, struct vmsvga_state_s),
1076 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1077 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1078 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1079 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1080 VMSTATE_INT32(index, struct vmsvga_state_s),
1081 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1082 scratch_size, 0, vmstate_info_uint32, uint32_t),
1083 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1084 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1085 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1086 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1087 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1088 VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1089 VMSTATE_END_OF_LIST()
1090 }
1091 };
1092
1093 const VMStateDescription vmstate_vmware_vga = {
1094 .name = "vmware_vga",
1095 .version_id = 0,
1096 .minimum_version_id = 0,
1097 .minimum_version_id_old = 0,
1098 .fields = (VMStateField []) {
1099 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1100 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1101 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1102 VMSTATE_END_OF_LIST()
1103 }
1104 };
1105
1106 static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
1107 {
1108 s->scratch_size = SVGA_SCRATCH_SIZE;
1109 s->scratch = qemu_malloc(s->scratch_size * 4);
1110
1111 vmsvga_reset(s);
1112
1113 vga_common_init(&s->vga, vga_ram_size);
1114 vga_init(&s->vga);
1115 vmstate_register(0, &vmstate_vga_common, &s->vga);
1116
1117 s->vga.ds = graphic_console_init(vmsvga_update_display,
1118 vmsvga_invalidate_display,
1119 vmsvga_screen_dump,
1120 vmsvga_text_update, s);
1121
1122 #ifdef CONFIG_BOCHS_VBE
1123 /* XXX: use optimized standard vga accesses */
1124 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1125 vga_ram_size, s->vga.vram_offset);
1126 #endif
1127 }
1128
1129 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1130 pcibus_t addr, pcibus_t size, int type)
1131 {
1132 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1133 struct vmsvga_state_s *s = &d->chip;
1134
1135 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1136 1, 4, vmsvga_index_read, s);
1137 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1138 1, 4, vmsvga_index_write, s);
1139 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1140 1, 4, vmsvga_value_read, s);
1141 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1142 1, 4, vmsvga_value_write, s);
1143 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1144 1, 4, vmsvga_bios_read, s);
1145 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1146 1, 4, vmsvga_bios_write, s);
1147 }
1148
1149 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1150 pcibus_t addr, pcibus_t size, int type)
1151 {
1152 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1153 struct vmsvga_state_s *s = &d->chip;
1154 ram_addr_t iomemtype;
1155
1156 s->vram_base = addr;
1157 #ifdef DIRECT_VRAM
1158 iomemtype = cpu_register_io_memory(vmsvga_vram_read,
1159 vmsvga_vram_write, s);
1160 #else
1161 iomemtype = s->vga.vram_offset | IO_MEM_RAM;
1162 #endif
1163 cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
1164 iomemtype);
1165 }
1166
1167 static int pci_vmsvga_initfn(PCIDevice *dev)
1168 {
1169 struct pci_vmsvga_state_s *s =
1170 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1171
1172 pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1173 pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
1174 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1175 pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
1176 s->card.config[0x0c] = 0x08; /* Cache line size */
1177 s->card.config[0x0d] = 0x40; /* Latency timer */
1178 s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
1179 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1180 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1181 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1182 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1183 s->card.config[0x3c] = 0xff; /* End */
1184
1185 pci_register_bar(&s->card, 0, 0x10,
1186 PCI_BASE_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1187 pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
1188 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_mem);
1189
1190 vmsvga_init(&s->chip, VGA_RAM_SIZE);
1191
1192 vmstate_register(0, &vmstate_vmware_vga, s);
1193 return 0;
1194 }
1195
1196 void pci_vmsvga_init(PCIBus *bus)
1197 {
1198 pci_create_simple(bus, -1, "QEMUware SVGA");
1199 }
1200
1201 static PCIDeviceInfo vmsvga_info = {
1202 .qdev.name = "QEMUware SVGA",
1203 .qdev.size = sizeof(struct pci_vmsvga_state_s),
1204 .init = pci_vmsvga_initfn,
1205 };
1206
1207 static void vmsvga_register(void)
1208 {
1209 pci_qdev_register(&vmsvga_info);
1210 }
1211 device_init(vmsvga_register);
Qemu with PowerPC KVM improvements