hw/block/m25p80.c

   1 /*
   2  * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
   3  * set. Known devices table current as of Jun/2012 and taken from linux.
   4  * See drivers/mtd/devices/m25p80.c.
   5  *
   6  * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   7  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
   8  * Copyright (C) 2012 PetaLogix
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 or
  13  * (at your option) a later version of the License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include "hw/hw.h"
  25 #include "sysemu/blockdev.h"
  26 #include "hw/ssi.h"
  27
  28 #ifndef M25P80_ERR_DEBUG
  29 #define M25P80_ERR_DEBUG 0
  30 #endif
  31
  32 #define DB_PRINT_L(level, ...) do { \
  33     if (M25P80_ERR_DEBUG > (level)) { \
  34         fprintf(stderr,  ": %s: ", __func__); \
  35         fprintf(stderr, ## __VA_ARGS__); \
  36     } \
  37 } while (0);
  38
  39 /* Fields for FlashPartInfo->flags */
  40
  41 /* erase capabilities */
  42 #define ER_4K 1
  43 #define ER_32K 2
  44 /* set to allow the page program command to write 0s back to 1. Useful for
  45  * modelling EEPROM with SPI flash command set
  46  */
  47 #define WR_1 0x100
  48
  49 typedef struct FlashPartInfo {
  50     const char *part_name;
  51     /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
  52     uint32_t jedec;
  53     /* extended jedec code */
  54     uint16_t ext_jedec;
  55     /* there is confusion between manufacturers as to what a sector is. In this
  56      * device model, a "sector" is the size that is erased by the ERASE_SECTOR
  57      * command (opcode 0xd8).
  58      */
  59     uint32_t sector_size;
  60     uint32_t n_sectors;
  61     uint32_t page_size;
  62     uint8_t flags;
  63 } FlashPartInfo;
  64
  65 /* adapted from linux */
  66
  67 #define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
  68     .part_name = (_part_name),\
  69     .jedec = (_jedec),\
  70     .ext_jedec = (_ext_jedec),\
  71     .sector_size = (_sector_size),\
  72     .n_sectors = (_n_sectors),\
  73     .page_size = 256,\
  74     .flags = (_flags),\
  75
  76 #define JEDEC_NUMONYX 0x20
  77 #define JEDEC_WINBOND 0xEF
  78 #define JEDEC_SPANSION 0x01
  79
  80 static const FlashPartInfo known_devices[] = {
  81     /* Atmel -- some are (confusingly) marketed as "DataFlash" */
  82     { INFO("at25fs010",   0x1f6601,      0,  32 << 10,   4, ER_4K) },
  83     { INFO("at25fs040",   0x1f6604,      0,  64 << 10,   8, ER_4K) },
  84
  85     { INFO("at25df041a",  0x1f4401,      0,  64 << 10,   8, ER_4K) },
  86     { INFO("at25df321a",  0x1f4701,      0,  64 << 10,  64, ER_4K) },
  87     { INFO("at25df641",   0x1f4800,      0,  64 << 10, 128, ER_4K) },
  88
  89     { INFO("at26f004",    0x1f0400,      0,  64 << 10,   8, ER_4K) },
  90     { INFO("at26df081a",  0x1f4501,      0,  64 << 10,  16, ER_4K) },
  91     { INFO("at26df161a",  0x1f4601,      0,  64 << 10,  32, ER_4K) },
  92     { INFO("at26df321",   0x1f4700,      0,  64 << 10,  64, ER_4K) },
  93
  94     /* EON -- en25xxx */
  95     { INFO("en25f32",     0x1c3116,      0,  64 << 10,  64, ER_4K) },
  96     { INFO("en25p32",     0x1c2016,      0,  64 << 10,  64, 0) },
  97     { INFO("en25q32b",    0x1c3016,      0,  64 << 10,  64, 0) },
  98     { INFO("en25p64",     0x1c2017,      0,  64 << 10, 128, 0) },
  99
 100     /* Intel/Numonyx -- xxxs33b */
 101     { INFO("160s33b",     0x898911,      0,  64 << 10,  32, 0) },
 102     { INFO("320s33b",     0x898912,      0,  64 << 10,  64, 0) },
 103     { INFO("640s33b",     0x898913,      0,  64 << 10, 128, 0) },
 104
 105     /* Macronix */
 106     { INFO("mx25l4005a",  0xc22013,      0,  64 << 10,   8, ER_4K) },
 107     { INFO("mx25l8005",   0xc22014,      0,  64 << 10,  16, 0) },
 108     { INFO("mx25l1606e",  0xc22015,      0,  64 << 10,  32, ER_4K) },
 109     { INFO("mx25l3205d",  0xc22016,      0,  64 << 10,  64, 0) },
 110     { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
 111     { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
 112     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
 113     { INFO("mx25l25635e", 0xc22019,      0,  64 << 10, 512, 0) },
 114     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
 115
 116     /* Spansion -- single (large) sector size only, at least
 117      * for the chips listed here (without boot sectors).
 118      */
 119     { INFO("s25sl004a",   0x010212,      0,  64 << 10,   8, 0) },
 120     { INFO("s25sl008a",   0x010213,      0,  64 << 10,  16, 0) },
 121     { INFO("s25sl016a",   0x010214,      0,  64 << 10,  32, 0) },
 122     { INFO("s25sl032a",   0x010215,      0,  64 << 10,  64, 0) },
 123     { INFO("s25sl032p",   0x010215, 0x4d00,  64 << 10,  64, ER_4K) },
 124     { INFO("s25sl064a",   0x010216,      0,  64 << 10, 128, 0) },
 125     { INFO("s25fl256s0",  0x010219, 0x4d00, 256 << 10, 128, 0) },
 126     { INFO("s25fl256s1",  0x010219, 0x4d01,  64 << 10, 512, 0) },
 127     { INFO("s25fl512s",   0x010220, 0x4d00, 256 << 10, 256, 0) },
 128     { INFO("s70fl01gs",   0x010221, 0x4d00, 256 << 10, 256, 0) },
 129     { INFO("s25sl12800",  0x012018, 0x0300, 256 << 10,  64, 0) },
 130     { INFO("s25sl12801",  0x012018, 0x0301,  64 << 10, 256, 0) },
 131     { INFO("s25fl129p0",  0x012018, 0x4d00, 256 << 10,  64, 0) },
 132     { INFO("s25fl129p1",  0x012018, 0x4d01,  64 << 10, 256, 0) },
 133     { INFO("s25fl016k",   0xef4015,      0,  64 << 10,  32, ER_4K | ER_32K) },
 134     { INFO("s25fl064k",   0xef4017,      0,  64 << 10, 128, ER_4K | ER_32K) },
 135
 136     /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
 137     { INFO("sst25vf040b", 0xbf258d,      0,  64 << 10,   8, ER_4K) },
 138     { INFO("sst25vf080b", 0xbf258e,      0,  64 << 10,  16, ER_4K) },
 139     { INFO("sst25vf016b", 0xbf2541,      0,  64 << 10,  32, ER_4K) },
 140     { INFO("sst25vf032b", 0xbf254a,      0,  64 << 10,  64, ER_4K) },
 141     { INFO("sst25wf512",  0xbf2501,      0,  64 << 10,   1, ER_4K) },
 142     { INFO("sst25wf010",  0xbf2502,      0,  64 << 10,   2, ER_4K) },
 143     { INFO("sst25wf020",  0xbf2503,      0,  64 << 10,   4, ER_4K) },
 144     { INFO("sst25wf040",  0xbf2504,      0,  64 << 10,   8, ER_4K) },
 145
 146     /* ST Microelectronics -- newer production may have feature updates */
 147     { INFO("m25p05",      0x202010,      0,  32 << 10,   2, 0) },
 148     { INFO("m25p10",      0x202011,      0,  32 << 10,   4, 0) },
 149     { INFO("m25p20",      0x202012,      0,  64 << 10,   4, 0) },
 150     { INFO("m25p40",      0x202013,      0,  64 << 10,   8, 0) },
 151     { INFO("m25p80",      0x202014,      0,  64 << 10,  16, 0) },
 152     { INFO("m25p16",      0x202015,      0,  64 << 10,  32, 0) },
 153     { INFO("m25p32",      0x202016,      0,  64 << 10,  64, 0) },
 154     { INFO("m25p64",      0x202017,      0,  64 << 10, 128, 0) },
 155     { INFO("m25p128",     0x202018,      0, 256 << 10,  64, 0) },
 156
 157     { INFO("m45pe10",     0x204011,      0,  64 << 10,   2, 0) },
 158     { INFO("m45pe80",     0x204014,      0,  64 << 10,  16, 0) },
 159     { INFO("m45pe16",     0x204015,      0,  64 << 10,  32, 0) },
 160
 161     { INFO("m25pe80",     0x208014,      0,  64 << 10,  16, 0) },
 162     { INFO("m25pe16",     0x208015,      0,  64 << 10,  32, ER_4K) },
 163
 164     { INFO("m25px32",     0x207116,      0,  64 << 10,  64, ER_4K) },
 165     { INFO("m25px32-s0",  0x207316,      0,  64 << 10,  64, ER_4K) },
 166     { INFO("m25px32-s1",  0x206316,      0,  64 << 10,  64, ER_4K) },
 167     { INFO("m25px64",     0x207117,      0,  64 << 10, 128, 0) },
 168
 169     /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
 170     { INFO("w25x10",      0xef3011,      0,  64 << 10,   2, ER_4K) },
 171     { INFO("w25x20",      0xef3012,      0,  64 << 10,   4, ER_4K) },
 172     { INFO("w25x40",      0xef3013,      0,  64 << 10,   8, ER_4K) },
 173     { INFO("w25x80",      0xef3014,      0,  64 << 10,  16, ER_4K) },
 174     { INFO("w25x16",      0xef3015,      0,  64 << 10,  32, ER_4K) },
 175     { INFO("w25x32",      0xef3016,      0,  64 << 10,  64, ER_4K) },
 176     { INFO("w25q32",      0xef4016,      0,  64 << 10,  64, ER_4K) },
 177     { INFO("w25x64",      0xef3017,      0,  64 << 10, 128, ER_4K) },
 178     { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },
 179
 180     /* Numonyx -- n25q128 */
 181     { INFO("n25q128",      0x20ba18,      0,  64 << 10, 256, 0) },
 182 };
 183
 184 typedef enum {
 185     NOP = 0,
 186     WRSR = 0x1,
 187     WRDI = 0x4,
 188     RDSR = 0x5,
 189     WREN = 0x6,
 190     JEDEC_READ = 0x9f,
 191     BULK_ERASE = 0xc7,
 192
 193     READ = 0x3,
 194     FAST_READ = 0xb,
 195     DOR = 0x3b,
 196     QOR = 0x6b,
 197     DIOR = 0xbb,
 198     QIOR = 0xeb,
 199
 200     PP = 0x2,
 201     DPP = 0xa2,
 202     QPP = 0x32,
 203
 204     ERASE_4K = 0x20,
 205     ERASE_32K = 0x52,
 206     ERASE_SECTOR = 0xd8,
 207 } FlashCMD;
 208
 209 typedef enum {
 210     STATE_IDLE,
 211     STATE_PAGE_PROGRAM,
 212     STATE_READ,
 213     STATE_COLLECTING_DATA,
 214     STATE_READING_DATA,
 215 } CMDState;
 216
 217 typedef struct Flash {
 218     SSISlave ssidev;
 219     uint32_t r;
 220
 221     BlockDriverState *bdrv;
 222
 223     uint8_t *storage;
 224     uint32_t size;
 225     int page_size;
 226
 227     uint8_t state;
 228     uint8_t data[16];
 229     uint32_t len;
 230     uint32_t pos;
 231     uint8_t needed_bytes;
 232     uint8_t cmd_in_progress;
 233     uint64_t cur_addr;
 234     bool write_enable;
 235
 236     int64_t dirty_page;
 237
 238     const FlashPartInfo *pi;
 239
 240 } Flash;
 241
 242 typedef struct M25P80Class {
 243     SSISlaveClass parent_class;
 244     FlashPartInfo *pi;
 245 } M25P80Class;
 246
 247 #define TYPE_M25P80 "m25p80-generic"
 248 #define M25P80(obj) \
 249      OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
 250 #define M25P80_CLASS(klass) \
 251      OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
 252 #define M25P80_GET_CLASS(obj) \
 253      OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
 254
 255 static void bdrv_sync_complete(void *opaque, int ret)
 256 {
 257     /* do nothing. Masters do not directly interact with the backing store,
 258      * only the working copy so no mutexing required.
 259      */
 260 }
 261
 262 static void flash_sync_page(Flash *s, int page)
 263 {
 264     if (s->bdrv) {
 265         int bdrv_sector, nb_sectors;
 266         QEMUIOVector iov;
 267
 268         bdrv_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
 269         nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
 270         qemu_iovec_init(&iov, 1);
 271         qemu_iovec_add(&iov, s->storage + bdrv_sector * BDRV_SECTOR_SIZE,
 272                                                 nb_sectors * BDRV_SECTOR_SIZE);
 273         bdrv_aio_writev(s->bdrv, bdrv_sector, &iov, nb_sectors,
 274                                                 bdrv_sync_complete, NULL);
 275     }
 276 }
 277
 278 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
 279 {
 280     int64_t start, end, nb_sectors;
 281     QEMUIOVector iov;
 282
 283     if (!s->bdrv) {
 284         return;
 285     }
 286
 287     assert(!(len % BDRV_SECTOR_SIZE));
 288     start = off / BDRV_SECTOR_SIZE;
 289     end = (off + len) / BDRV_SECTOR_SIZE;
 290     nb_sectors = end - start;
 291     qemu_iovec_init(&iov, 1);
 292     qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
 293                                         nb_sectors * BDRV_SECTOR_SIZE);
 294     bdrv_aio_writev(s->bdrv, start, &iov, nb_sectors, bdrv_sync_complete, NULL);
 295 }
 296
 297 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
 298 {
 299     uint32_t len;
 300     uint8_t capa_to_assert = 0;
 301
 302     switch (cmd) {
 303     case ERASE_4K:
 304         len = 4 << 10;
 305         capa_to_assert = ER_4K;
 306         break;
 307     case ERASE_32K:
 308         len = 32 << 10;
 309         capa_to_assert = ER_32K;
 310         break;
 311     case ERASE_SECTOR:
 312         len = s->pi->sector_size;
 313         break;
 314     case BULK_ERASE:
 315         len = s->size;
 316         break;
 317     default:
 318         abort();
 319     }
 320
 321     DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
 322     if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
 323         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
 324                       " device\n", len);
 325     }
 326
 327     if (!s->write_enable) {
 328         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
 329         return;
 330     }
 331     memset(s->storage + offset, 0xff, len);
 332     flash_sync_area(s, offset, len);
 333 }
 334
 335 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
 336 {
 337     if (s->dirty_page >= 0 && s->dirty_page != newpage) {
 338         flash_sync_page(s, s->dirty_page);
 339         s->dirty_page = newpage;
 340     }
 341 }
 342
 343 static inline
 344 void flash_write8(Flash *s, uint64_t addr, uint8_t data)
 345 {
 346     int64_t page = addr / s->pi->page_size;
 347     uint8_t prev = s->storage[s->cur_addr];
 348
 349     if (!s->write_enable) {
 350         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
 351     }
 352
 353     if ((prev ^ data) & data) {
 354         DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 "  %" PRIx8
 355                    " -> %" PRIx8 "\n", addr, prev, data);
 356     }
 357
 358     if (s->pi->flags & WR_1) {
 359         s->storage[s->cur_addr] = data;
 360     } else {
 361         s->storage[s->cur_addr] &= data;
 362     }
 363
 364     flash_sync_dirty(s, page);
 365     s->dirty_page = page;
 366 }
 367
 368 static void complete_collecting_data(Flash *s)
 369 {
 370     s->cur_addr = s->data[0] << 16;
 371     s->cur_addr |= s->data[1] << 8;
 372     s->cur_addr |= s->data[2];
 373
 374     s->state = STATE_IDLE;
 375
 376     switch (s->cmd_in_progress) {
 377     case DPP:
 378     case QPP:
 379     case PP:
 380         s->state = STATE_PAGE_PROGRAM;
 381         break;
 382     case READ:
 383     case FAST_READ:
 384     case DOR:
 385     case QOR:
 386     case DIOR:
 387     case QIOR:
 388         s->state = STATE_READ;
 389         break;
 390     case ERASE_4K:
 391     case ERASE_32K:
 392     case ERASE_SECTOR:
 393         flash_erase(s, s->cur_addr, s->cmd_in_progress);
 394         break;
 395     case WRSR:
 396         if (s->write_enable) {
 397             s->write_enable = false;
 398         }
 399         break;
 400     default:
 401         break;
 402     }
 403 }
 404
 405 static void decode_new_cmd(Flash *s, uint32_t value)
 406 {
 407     s->cmd_in_progress = value;
 408     DB_PRINT_L(0, "decoded new command:%x\n", value);
 409
 410     switch (value) {
 411
 412     case ERASE_4K:
 413     case ERASE_32K:
 414     case ERASE_SECTOR:
 415     case READ:
 416     case DPP:
 417     case QPP:
 418     case PP:
 419         s->needed_bytes = 3;
 420         s->pos = 0;
 421         s->len = 0;
 422         s->state = STATE_COLLECTING_DATA;
 423         break;
 424
 425     case FAST_READ:
 426     case DOR:
 427     case QOR:
 428         s->needed_bytes = 4;
 429         s->pos = 0;
 430         s->len = 0;
 431         s->state = STATE_COLLECTING_DATA;
 432         break;
 433
 434     case DIOR:
 435         switch ((s->pi->jedec >> 16) & 0xFF) {
 436         case JEDEC_WINBOND:
 437         case JEDEC_SPANSION:
 438             s->needed_bytes = 4;
 439             break;
 440         case JEDEC_NUMONYX:
 441         default:
 442             s->needed_bytes = 5;
 443         }
 444         s->pos = 0;
 445         s->len = 0;
 446         s->state = STATE_COLLECTING_DATA;
 447         break;
 448
 449     case QIOR:
 450         switch ((s->pi->jedec >> 16) & 0xFF) {
 451         case JEDEC_WINBOND:
 452         case JEDEC_SPANSION:
 453             s->needed_bytes = 6;
 454             break;
 455         case JEDEC_NUMONYX:
 456         default:
 457             s->needed_bytes = 8;
 458         }
 459         s->pos = 0;
 460         s->len = 0;
 461         s->state = STATE_COLLECTING_DATA;
 462         break;
 463
 464     case WRSR:
 465         if (s->write_enable) {
 466             s->needed_bytes = 1;
 467             s->pos = 0;
 468             s->len = 0;
 469             s->state = STATE_COLLECTING_DATA;
 470         }
 471         break;
 472
 473     case WRDI:
 474         s->write_enable = false;
 475         break;
 476     case WREN:
 477         s->write_enable = true;
 478         break;
 479
 480     case RDSR:
 481         s->data[0] = (!!s->write_enable) << 1;
 482         s->pos = 0;
 483         s->len = 1;
 484         s->state = STATE_READING_DATA;
 485         break;
 486
 487     case JEDEC_READ:
 488         DB_PRINT_L(0, "populated jedec code\n");
 489         s->data[0] = (s->pi->jedec >> 16) & 0xff;
 490         s->data[1] = (s->pi->jedec >> 8) & 0xff;
 491         s->data[2] = s->pi->jedec & 0xff;
 492         if (s->pi->ext_jedec) {
 493             s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
 494             s->data[4] = s->pi->ext_jedec & 0xff;
 495             s->len = 5;
 496         } else {
 497             s->len = 3;
 498         }
 499         s->pos = 0;
 500         s->state = STATE_READING_DATA;
 501         break;
 502
 503     case BULK_ERASE:
 504         if (s->write_enable) {
 505             DB_PRINT_L(0, "chip erase\n");
 506             flash_erase(s, 0, BULK_ERASE);
 507         } else {
 508             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
 509                           "protect!\n");
 510         }
 511         break;
 512     case NOP:
 513         break;
 514     default:
 515         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
 516         break;
 517     }
 518 }
 519
 520 static int m25p80_cs(SSISlave *ss, bool select)
 521 {
 522     Flash *s = FROM_SSI_SLAVE(Flash, ss);
 523
 524     if (select) {
 525         s->len = 0;
 526         s->pos = 0;
 527         s->state = STATE_IDLE;
 528         flash_sync_dirty(s, -1);
 529     }
 530
 531     DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
 532
 533     return 0;
 534 }
 535
 536 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
 537 {
 538     Flash *s = FROM_SSI_SLAVE(Flash, ss);
 539     uint32_t r = 0;
 540
 541     switch (s->state) {
 542
 543     case STATE_PAGE_PROGRAM:
 544         DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
 545                    s->cur_addr, (uint8_t)tx);
 546         flash_write8(s, s->cur_addr, (uint8_t)tx);
 547         s->cur_addr++;
 548         break;
 549
 550     case STATE_READ:
 551         r = s->storage[s->cur_addr];
 552         DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
 553                    (uint8_t)r);
 554         s->cur_addr = (s->cur_addr + 1) % s->size;
 555         break;
 556
 557     case STATE_COLLECTING_DATA:
 558         s->data[s->len] = (uint8_t)tx;
 559         s->len++;
 560
 561         if (s->len == s->needed_bytes) {
 562             complete_collecting_data(s);
 563         }
 564         break;
 565
 566     case STATE_READING_DATA:
 567         r = s->data[s->pos];
 568         s->pos++;
 569         if (s->pos == s->len) {
 570             s->pos = 0;
 571             s->state = STATE_IDLE;
 572         }
 573         break;
 574
 575     default:
 576     case STATE_IDLE:
 577         decode_new_cmd(s, (uint8_t)tx);
 578         break;
 579     }
 580
 581     return r;
 582 }
 583
 584 static int m25p80_init(SSISlave *ss)
 585 {
 586     DriveInfo *dinfo;
 587     Flash *s = FROM_SSI_SLAVE(Flash, ss);
 588     M25P80Class *mc = M25P80_GET_CLASS(s);
 589
 590     s->pi = mc->pi;
 591
 592     s->size = s->pi->sector_size * s->pi->n_sectors;
 593     s->dirty_page = -1;
 594     s->storage = qemu_blockalign(s->bdrv, s->size);
 595
 596     dinfo = drive_get_next(IF_MTD);
 597
 598     if (dinfo && dinfo->bdrv) {
 599         DB_PRINT_L(0, "Binding to IF_MTD drive\n");
 600         s->bdrv = dinfo->bdrv;
 601         /* FIXME: Move to late init */
 602         if (bdrv_read(s->bdrv, 0, s->storage, DIV_ROUND_UP(s->size,
 603                                                     BDRV_SECTOR_SIZE))) {
 604             fprintf(stderr, "Failed to initialize SPI flash!\n");
 605             return 1;
 606         }
 607     } else {
 608         DB_PRINT_L(0, "No BDRV - binding to RAM\n");
 609         memset(s->storage, 0xFF, s->size);
 610     }
 611
 612     return 0;
 613 }
 614
 615 static void m25p80_pre_save(void *opaque)
 616 {
 617     flash_sync_dirty((Flash *)opaque, -1);
 618 }
 619
 620 static const VMStateDescription vmstate_m25p80 = {
 621     .name = "xilinx_spi",
 622     .version_id = 1,
 623     .minimum_version_id = 1,
 624     .minimum_version_id_old = 1,
 625     .pre_save = m25p80_pre_save,
 626     .fields = (VMStateField[]) {
 627         VMSTATE_UINT8(state, Flash),
 628         VMSTATE_UINT8_ARRAY(data, Flash, 16),
 629         VMSTATE_UINT32(len, Flash),
 630         VMSTATE_UINT32(pos, Flash),
 631         VMSTATE_UINT8(needed_bytes, Flash),
 632         VMSTATE_UINT8(cmd_in_progress, Flash),
 633         VMSTATE_UINT64(cur_addr, Flash),
 634         VMSTATE_BOOL(write_enable, Flash),
 635         VMSTATE_END_OF_LIST()
 636     }
 637 };
 638
 639 static void m25p80_class_init(ObjectClass *klass, void *data)
 640 {
 641     DeviceClass *dc = DEVICE_CLASS(klass);
 642     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
 643     M25P80Class *mc = M25P80_CLASS(klass);
 644
 645     k->init = m25p80_init;
 646     k->transfer = m25p80_transfer8;
 647     k->set_cs = m25p80_cs;
 648     k->cs_polarity = SSI_CS_LOW;
 649     dc->vmsd = &vmstate_m25p80;
 650     mc->pi = data;
 651 }
 652
 653 static const TypeInfo m25p80_info = {
 654     .name           = TYPE_M25P80,
 655     .parent         = TYPE_SSI_SLAVE,
 656     .instance_size  = sizeof(Flash),
 657     .class_size     = sizeof(M25P80Class),
 658     .abstract       = true,
 659 };
 660
 661 static void m25p80_register_types(void)
 662 {
 663     int i;
 664
 665     type_register_static(&m25p80_info);
 666     for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
 667         TypeInfo ti = {
 668             .name       = known_devices[i].part_name,
 669             .parent     = TYPE_M25P80,
 670             .class_init = m25p80_class_init,
 671             .class_data = (void *)&known_devices[i],
 672         };
 673         type_register(&ti);
 674     }
 675 }
 676
 677 type_init(m25p80_register_types)