Fix zero-length write(2).
[qemu/agraf.git] / hw / ppc.h
blobde13092ae4202a7da595187f5f8123f16b011e37
1 /* PowerPC hardware exceptions management helpers */
2 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
3 typedef struct clk_setup_t clk_setup_t;
4 struct clk_setup_t {
5 clk_setup_cb cb;
6 void *opaque;
7 };
8 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
10 if (clk->cb != NULL)
11 (*clk->cb)(clk->opaque, freq);
14 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
15 /* Embedded PowerPC DCR management */
16 typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
17 typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
18 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
19 int (*dcr_write_error)(int dcrn));
20 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
21 dcr_read_cb drc_read, dcr_write_cb dcr_write);
22 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
23 /* Embedded PowerPC reset */
24 void ppc40x_core_reset (CPUState *env);
25 void ppc40x_chip_reset (CPUState *env);
26 void ppc40x_system_reset (CPUState *env);
27 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
29 extern CPUWriteMemoryFunc * const PPC_io_write[];
30 extern CPUReadMemoryFunc * const PPC_io_read[];
31 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
33 void ppc40x_irq_init (CPUState *env);
34 void ppce500_irq_init (CPUState *env);
35 void ppc6xx_irq_init (CPUState *env);
36 void ppc970_irq_init (CPUState *env);
38 /* PPC machines for OpenBIOS */
39 enum {
40 ARCH_PREP = 0,
41 ARCH_MAC99,
42 ARCH_HEATHROW,
43 ARCH_MAC99_U3,
46 #define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
47 #define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
48 #define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
49 #define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
51 #define PPC_SERIAL_MM_BAUDBASE 399193