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configure: add -Werror to QEMU_CFLAGS early
[qemu/agraf.git] / target-ppc / translate.c
blob91eb7a062c5dd578792ca12ab0911162c3a4796b
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas.h"
23 #include "tcg-op.h"
24 #include "host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer;
70 static TCGv cpu_reserve;
71 static TCGv_i32 cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161
162 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, reserve_addr),
164 "reserve_addr");
165
166 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
167 offsetof(CPUPPCState, fpscr), "fpscr");
168
169 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
170 offsetof(CPUPPCState, access_type), "access_type");
171
172 /* register helpers */
173 #define GEN_HELPER 2
174 #include "helper.h"
175
176 done_init = 1;
177 }
178
179 /* internal defines */
180 typedef struct DisasContext {
181 struct TranslationBlock *tb;
182 target_ulong nip;
183 uint32_t opcode;
184 uint32_t exception;
185 /* Routine used to access memory */
186 int mem_idx;
187 int access_type;
188 /* Translation flags */
189 int le_mode;
190 #if defined(TARGET_PPC64)
191 int sf_mode;
192 int has_cfar;
193 #endif
194 int fpu_enabled;
195 int altivec_enabled;
196 int spe_enabled;
197 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
198 int singlestep_enabled;
199 } DisasContext;
200
201 struct opc_handler_t {
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
203 uint32_t inval1;
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
205 uint32_t inval2;
206 /* instruction type */
207 uint64_t type;
208 /* extended instruction type */
209 uint64_t type2;
210 /* handler */
211 void (*handler)(DisasContext *ctx);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 const char *oname;
214 #endif
215 #if defined(DO_PPC_STATISTICS)
216 uint64_t count;
217 #endif
218 };
219
220 static inline void gen_reset_fpstatus(void)
221 {
222 gen_helper_reset_fpstatus(cpu_env);
223 }
224
225 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
226 {
227 TCGv_i32 t0 = tcg_temp_new_i32();
228
229 if (set_fprf != 0) {
230 /* This case might be optimized later */
231 tcg_gen_movi_i32(t0, 1);
232 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
233 if (unlikely(set_rc)) {
234 tcg_gen_mov_i32(cpu_crf[1], t0);
235 }
236 gen_helper_float_check_status(cpu_env);
237 } else if (unlikely(set_rc)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0, 0);
240 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
241 tcg_gen_mov_i32(cpu_crf[1], t0);
242 }
243
244 tcg_temp_free_i32(t0);
245 }
246
247 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
248 {
249 if (ctx->access_type != access_type) {
250 tcg_gen_movi_i32(cpu_access_type, access_type);
251 ctx->access_type = access_type;
252 }
253 }
254
255 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
256 {
257 #if defined(TARGET_PPC64)
258 if (ctx->sf_mode)
259 tcg_gen_movi_tl(cpu_nip, nip);
260 else
261 #endif
262 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
263 }
264
265 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
266 {
267 TCGv_i32 t0, t1;
268 if (ctx->exception == POWERPC_EXCP_NONE) {
269 gen_update_nip(ctx, ctx->nip);
270 }
271 t0 = tcg_const_i32(excp);
272 t1 = tcg_const_i32(error);
273 gen_helper_raise_exception_err(cpu_env, t0, t1);
274 tcg_temp_free_i32(t0);
275 tcg_temp_free_i32(t1);
276 ctx->exception = (excp);
277 }
278
279 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
280 {
281 TCGv_i32 t0;
282 if (ctx->exception == POWERPC_EXCP_NONE) {
283 gen_update_nip(ctx, ctx->nip);
284 }
285 t0 = tcg_const_i32(excp);
286 gen_helper_raise_exception(cpu_env, t0);
287 tcg_temp_free_i32(t0);
288 ctx->exception = (excp);
289 }
290
291 static inline void gen_debug_exception(DisasContext *ctx)
292 {
293 TCGv_i32 t0;
294
295 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
296 (ctx->exception != POWERPC_EXCP_SYNC)) {
297 gen_update_nip(ctx, ctx->nip);
298 }
299 t0 = tcg_const_i32(EXCP_DEBUG);
300 gen_helper_raise_exception(cpu_env, t0);
301 tcg_temp_free_i32(t0);
302 }
303
304 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
305 {
306 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
307 }
308
309 /* Stop translation */
310 static inline void gen_stop_exception(DisasContext *ctx)
311 {
312 gen_update_nip(ctx, ctx->nip);
313 ctx->exception = POWERPC_EXCP_STOP;
314 }
315
316 /* No need to update nip here, as execution flow will change */
317 static inline void gen_sync_exception(DisasContext *ctx)
318 {
319 ctx->exception = POWERPC_EXCP_SYNC;
320 }
321
322 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
324
325 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
326 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
327
328 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
333
334 typedef struct opcode_t {
335 unsigned char opc1, opc2, opc3;
336 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
337 unsigned char pad[5];
338 #else
339 unsigned char pad[1];
340 #endif
341 opc_handler_t handler;
342 const char *oname;
343 } opcode_t;
344
345 /*****************************************************************************/
346 /*** Instruction decoding ***/
347 #define EXTRACT_HELPER(name, shift, nb) \
348 static inline uint32_t name(uint32_t opcode) \
349 { \
350 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
351 }
352
353 #define EXTRACT_SHELPER(name, shift, nb) \
354 static inline int32_t name(uint32_t opcode) \
355 { \
356 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
357 }
358
359 /* Opcode part 1 */
360 EXTRACT_HELPER(opc1, 26, 6);
361 /* Opcode part 2 */
362 EXTRACT_HELPER(opc2, 1, 5);
363 /* Opcode part 3 */
364 EXTRACT_HELPER(opc3, 6, 5);
365 /* Update Cr0 flags */
366 EXTRACT_HELPER(Rc, 0, 1);
367 /* Destination */
368 EXTRACT_HELPER(rD, 21, 5);
369 /* Source */
370 EXTRACT_HELPER(rS, 21, 5);
371 /* First operand */
372 EXTRACT_HELPER(rA, 16, 5);
373 /* Second operand */
374 EXTRACT_HELPER(rB, 11, 5);
375 /* Third operand */
376 EXTRACT_HELPER(rC, 6, 5);
377 /*** Get CRn ***/
378 EXTRACT_HELPER(crfD, 23, 3);
379 EXTRACT_HELPER(crfS, 18, 3);
380 EXTRACT_HELPER(crbD, 21, 5);
381 EXTRACT_HELPER(crbA, 16, 5);
382 EXTRACT_HELPER(crbB, 11, 5);
383 /* SPR / TBL */
384 EXTRACT_HELPER(_SPR, 11, 10);
385 static inline uint32_t SPR(uint32_t opcode)
386 {
387 uint32_t sprn = _SPR(opcode);
388
389 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
390 }
391 /*** Get constants ***/
392 EXTRACT_HELPER(IMM, 12, 8);
393 /* 16 bits signed immediate value */
394 EXTRACT_SHELPER(SIMM, 0, 16);
395 /* 16 bits unsigned immediate value */
396 EXTRACT_HELPER(UIMM, 0, 16);
397 /* 5 bits signed immediate value */
398 EXTRACT_HELPER(SIMM5, 16, 5);
399 /* 5 bits signed immediate value */
400 EXTRACT_HELPER(UIMM5, 16, 5);
401 /* Bit count */
402 EXTRACT_HELPER(NB, 11, 5);
403 /* Shift count */
404 EXTRACT_HELPER(SH, 11, 5);
405 /* Vector shift count */
406 EXTRACT_HELPER(VSH, 6, 4);
407 /* Mask start */
408 EXTRACT_HELPER(MB, 6, 5);
409 /* Mask end */
410 EXTRACT_HELPER(ME, 1, 5);
411 /* Trap operand */
412 EXTRACT_HELPER(TO, 21, 5);
413
414 EXTRACT_HELPER(CRM, 12, 8);
415 EXTRACT_HELPER(FM, 17, 8);
416 EXTRACT_HELPER(SR, 16, 4);
417 EXTRACT_HELPER(FPIMM, 12, 4);
418
419 /*** Jump target decoding ***/
420 /* Displacement */
421 EXTRACT_SHELPER(d, 0, 16);
422 /* Immediate address */
423 static inline target_ulong LI(uint32_t opcode)
424 {
425 return (opcode >> 0) & 0x03FFFFFC;
426 }
427
428 static inline uint32_t BD(uint32_t opcode)
429 {
430 return (opcode >> 0) & 0xFFFC;
431 }
432
433 EXTRACT_HELPER(BO, 21, 5);
434 EXTRACT_HELPER(BI, 16, 5);
435 /* Absolute/relative address */
436 EXTRACT_HELPER(AA, 1, 1);
437 /* Link */
438 EXTRACT_HELPER(LK, 0, 1);
439
440 /* Create a mask between <start> and <end> bits */
441 static inline target_ulong MASK(uint32_t start, uint32_t end)
442 {
443 target_ulong ret;
444
445 #if defined(TARGET_PPC64)
446 if (likely(start == 0)) {
447 ret = UINT64_MAX << (63 - end);
448 } else if (likely(end == 63)) {
449 ret = UINT64_MAX >> start;
450 }
451 #else
452 if (likely(start == 0)) {
453 ret = UINT32_MAX << (31 - end);
454 } else if (likely(end == 31)) {
455 ret = UINT32_MAX >> start;
456 }
457 #endif
458 else {
459 ret = (((target_ulong)(-1ULL)) >> (start)) ^
460 (((target_ulong)(-1ULL) >> (end)) >> 1);
461 if (unlikely(start > end))
462 return ~ret;
463 }
464
465 return ret;
466 }
467
468 /*****************************************************************************/
469 /* PowerPC instructions table */
470
471 #if defined(DO_PPC_STATISTICS)
472 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
473 { \
474 .opc1 = op1, \
475 .opc2 = op2, \
476 .opc3 = op3, \
477 .pad = { 0, }, \
478 .handler = { \
479 .inval1 = invl, \
480 .type = _typ, \
481 .type2 = _typ2, \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
484 }, \
485 .oname = stringify(name), \
486 }
487 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
488 { \
489 .opc1 = op1, \
490 .opc2 = op2, \
491 .opc3 = op3, \
492 .pad = { 0, }, \
493 .handler = { \
494 .inval1 = invl1, \
495 .inval2 = invl2, \
496 .type = _typ, \
497 .type2 = _typ2, \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
500 }, \
501 .oname = stringify(name), \
502 }
503 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
504 { \
505 .opc1 = op1, \
506 .opc2 = op2, \
507 .opc3 = op3, \
508 .pad = { 0, }, \
509 .handler = { \
510 .inval1 = invl, \
511 .type = _typ, \
512 .type2 = _typ2, \
513 .handler = &gen_##name, \
514 .oname = onam, \
515 }, \
516 .oname = onam, \
517 }
518 #else
519 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .pad = { 0, }, \
525 .handler = { \
526 .inval1 = invl, \
527 .type = _typ, \
528 .type2 = _typ2, \
529 .handler = &gen_##name, \
530 }, \
531 .oname = stringify(name), \
532 }
533 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
534 { \
535 .opc1 = op1, \
536 .opc2 = op2, \
537 .opc3 = op3, \
538 .pad = { 0, }, \
539 .handler = { \
540 .inval1 = invl1, \
541 .inval2 = invl2, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = stringify(name), \
547 }
548 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
549 { \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .pad = { 0, }, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = onam, \
561 }
562 #endif
563
564 /* SPR load/store helpers */
565 static inline void gen_load_spr(TCGv t, int reg)
566 {
567 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
568 }
569
570 static inline void gen_store_spr(int reg, TCGv t)
571 {
572 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
573 }
574
575 /* Invalid instruction */
576 static void gen_invalid(DisasContext *ctx)
577 {
578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
579 }
580
581 static opc_handler_t invalid_handler = {
582 .inval1 = 0xFFFFFFFF,
583 .inval2 = 0xFFFFFFFF,
584 .type = PPC_NONE,
585 .type2 = PPC_NONE,
586 .handler = gen_invalid,
587 };
588
589 /*** Integer comparison ***/
590
591 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
592 {
593 int l1, l2, l3;
594
595 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
596 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
597 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
598
599 l1 = gen_new_label();
600 l2 = gen_new_label();
601 l3 = gen_new_label();
602 if (s) {
603 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
604 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
605 } else {
606 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
607 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
608 }
609 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
610 tcg_gen_br(l3);
611 gen_set_label(l1);
612 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
613 tcg_gen_br(l3);
614 gen_set_label(l2);
615 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
616 gen_set_label(l3);
617 }
618
619 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
620 {
621 TCGv t0 = tcg_const_local_tl(arg1);
622 gen_op_cmp(arg0, t0, s, crf);
623 tcg_temp_free(t0);
624 }
625
626 #if defined(TARGET_PPC64)
627 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0, t1;
630 t0 = tcg_temp_local_new();
631 t1 = tcg_temp_local_new();
632 if (s) {
633 tcg_gen_ext32s_tl(t0, arg0);
634 tcg_gen_ext32s_tl(t1, arg1);
635 } else {
636 tcg_gen_ext32u_tl(t0, arg0);
637 tcg_gen_ext32u_tl(t1, arg1);
638 }
639 gen_op_cmp(t0, t1, s, crf);
640 tcg_temp_free(t1);
641 tcg_temp_free(t0);
642 }
643
644 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
645 {
646 TCGv t0 = tcg_const_local_tl(arg1);
647 gen_op_cmp32(arg0, t0, s, crf);
648 tcg_temp_free(t0);
649 }
650 #endif
651
652 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
653 {
654 #if defined(TARGET_PPC64)
655 if (!(ctx->sf_mode))
656 gen_op_cmpi32(reg, 0, 1, 0);
657 else
658 #endif
659 gen_op_cmpi(reg, 0, 1, 0);
660 }
661
662 /* cmp */
663 static void gen_cmp(DisasContext *ctx)
664 {
665 #if defined(TARGET_PPC64)
666 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
667 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
668 1, crfD(ctx->opcode));
669 else
670 #endif
671 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 }
674
675 /* cmpi */
676 static void gen_cmpi(DisasContext *ctx)
677 {
678 #if defined(TARGET_PPC64)
679 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
680 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
681 1, crfD(ctx->opcode));
682 else
683 #endif
684 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 }
687
688 /* cmpl */
689 static void gen_cmpl(DisasContext *ctx)
690 {
691 #if defined(TARGET_PPC64)
692 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
693 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
694 0, crfD(ctx->opcode));
695 else
696 #endif
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 }
700
701 /* cmpli */
702 static void gen_cmpli(DisasContext *ctx)
703 {
704 #if defined(TARGET_PPC64)
705 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
706 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 else
709 #endif
710 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 }
713
714 /* isel (PowerPC 2.03 specification) */
715 static void gen_isel(DisasContext *ctx)
716 {
717 int l1, l2;
718 uint32_t bi = rC(ctx->opcode);
719 uint32_t mask;
720 TCGv_i32 t0;
721
722 l1 = gen_new_label();
723 l2 = gen_new_label();
724
725 mask = 1 << (3 - (bi & 0x03));
726 t0 = tcg_temp_new_i32();
727 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
728 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
729 if (rA(ctx->opcode) == 0)
730 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
731 else
732 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
733 tcg_gen_br(l2);
734 gen_set_label(l1);
735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
736 gen_set_label(l2);
737 tcg_temp_free_i32(t0);
738 }
739
740 /*** Integer arithmetic ***/
741
742 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
743 TCGv arg1, TCGv arg2, int sub)
744 {
745 int l1;
746 TCGv t0;
747
748 l1 = gen_new_label();
749 /* Start with XER OV disabled, the most likely case */
750 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
751 t0 = tcg_temp_local_new();
752 tcg_gen_xor_tl(t0, arg0, arg1);
753 #if defined(TARGET_PPC64)
754 if (!ctx->sf_mode)
755 tcg_gen_ext32s_tl(t0, t0);
756 #endif
757 if (sub)
758 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
759 else
760 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
761 tcg_gen_xor_tl(t0, arg1, arg2);
762 #if defined(TARGET_PPC64)
763 if (!ctx->sf_mode)
764 tcg_gen_ext32s_tl(t0, t0);
765 #endif
766 if (sub)
767 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
768 else
769 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
770 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
771 gen_set_label(l1);
772 tcg_temp_free(t0);
773 }
774
775 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
776 TCGv arg2, int sub)
777 {
778 int l1 = gen_new_label();
779
780 #if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode)) {
782 TCGv t0, t1;
783 t0 = tcg_temp_new();
784 t1 = tcg_temp_new();
785
786 tcg_gen_ext32u_tl(t0, arg1);
787 tcg_gen_ext32u_tl(t1, arg2);
788 if (sub) {
789 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
790 } else {
791 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
792 }
793 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
794 gen_set_label(l1);
795 tcg_temp_free(t0);
796 tcg_temp_free(t1);
797 } else
798 #endif
799 {
800 if (sub) {
801 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
802 } else {
803 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
804 }
805 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
806 gen_set_label(l1);
807 }
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, int add_ca, int compute_ca,
813 int compute_ov)
814 {
815 TCGv t0, t1;
816
817 if ((!compute_ca && !compute_ov) ||
818 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
819 t0 = ret;
820 } else {
821 t0 = tcg_temp_local_new();
822 }
823
824 if (add_ca) {
825 t1 = tcg_temp_local_new();
826 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
827 tcg_gen_shri_tl(t1, t1, XER_CA);
828 } else {
829 TCGV_UNUSED(t1);
830 }
831
832 if (compute_ca && compute_ov) {
833 /* Start with XER CA and OV disabled, the most likely case */
834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
835 } else if (compute_ca) {
836 /* Start with XER CA disabled, the most likely case */
837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
838 } else if (compute_ov) {
839 /* Start with XER OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
841 }
842
843 tcg_gen_add_tl(t0, arg1, arg2);
844
845 if (compute_ca) {
846 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
847 }
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, t1);
850 gen_op_arith_compute_ca(ctx, t0, t1, 0);
851 tcg_temp_free(t1);
852 }
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856
857 if (unlikely(Rc(ctx->opcode) != 0))
858 gen_set_Rc0(ctx, t0);
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_local_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
910 }
911 }
912 /* addic addic.*/
913 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
914 int compute_Rc0)
915 {
916 target_long simm = SIMM(ctx->opcode);
917
918 /* Start with XER CA and OV disabled, the most likely case */
919 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
920
921 if (likely(simm != 0)) {
922 TCGv t0 = tcg_temp_local_new();
923 tcg_gen_addi_tl(t0, arg1, simm);
924 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
925 tcg_gen_mov_tl(ret, t0);
926 tcg_temp_free(t0);
927 } else {
928 tcg_gen_mov_tl(ret, arg1);
929 }
930 if (compute_Rc0) {
931 gen_set_Rc0(ctx, ret);
932 }
933 }
934
935 static void gen_addic(DisasContext *ctx)
936 {
937 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
938 }
939
940 static void gen_addic_(DisasContext *ctx)
941 {
942 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
943 }
944
945 /* addis */
946 static void gen_addis(DisasContext *ctx)
947 {
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* lis case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
955 }
956 }
957
958 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
959 TCGv arg2, int sign, int compute_ov)
960 {
961 int l1 = gen_new_label();
962 int l2 = gen_new_label();
963 TCGv_i32 t0 = tcg_temp_local_new_i32();
964 TCGv_i32 t1 = tcg_temp_local_new_i32();
965
966 tcg_gen_trunc_tl_i32(t0, arg1);
967 tcg_gen_trunc_tl_i32(t1, arg2);
968 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
969 if (sign) {
970 int l3 = gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
972 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
973 gen_set_label(l3);
974 tcg_gen_div_i32(t0, t0, t1);
975 } else {
976 tcg_gen_divu_i32(t0, t0, t1);
977 }
978 if (compute_ov) {
979 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
980 }
981 tcg_gen_br(l2);
982 gen_set_label(l1);
983 if (sign) {
984 tcg_gen_sari_i32(t0, t0, 31);
985 } else {
986 tcg_gen_movi_i32(t0, 0);
987 }
988 if (compute_ov) {
989 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
990 }
991 gen_set_label(l2);
992 tcg_gen_extu_i32_tl(ret, t0);
993 tcg_temp_free_i32(t0);
994 tcg_temp_free_i32(t1);
995 if (unlikely(Rc(ctx->opcode) != 0))
996 gen_set_Rc0(ctx, ret);
997 }
998 /* Div functions */
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 static void glue(gen_, name)(DisasContext *ctx) \
1001 { \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1005 }
1006 /* divwu divwu. divwuo divwuo. */
1007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1009 /* divw divw. divwo divwo. */
1010 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1012 #if defined(TARGET_PPC64)
1013 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1014 TCGv arg2, int sign, int compute_ov)
1015 {
1016 int l1 = gen_new_label();
1017 int l2 = gen_new_label();
1018
1019 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1020 if (sign) {
1021 int l3 = gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1023 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1024 gen_set_label(l3);
1025 tcg_gen_div_i64(ret, arg1, arg2);
1026 } else {
1027 tcg_gen_divu_i64(ret, arg1, arg2);
1028 }
1029 if (compute_ov) {
1030 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1031 }
1032 tcg_gen_br(l2);
1033 gen_set_label(l1);
1034 if (sign) {
1035 tcg_gen_sari_i64(ret, arg1, 63);
1036 } else {
1037 tcg_gen_movi_i64(ret, 0);
1038 }
1039 if (compute_ov) {
1040 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1041 }
1042 gen_set_label(l2);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, ret);
1045 }
1046 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1047 static void glue(gen_, name)(DisasContext *ctx) \
1048 { \
1049 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1050 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1051 sign, compute_ov); \
1052 }
1053 /* divwu divwu. divwuo divwuo. */
1054 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1055 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1056 /* divw divw. divwo divwo. */
1057 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1058 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1059 #endif
1060
1061 /* mulhw mulhw. */
1062 static void gen_mulhw(DisasContext *ctx)
1063 {
1064 TCGv_i64 t0, t1;
1065
1066 t0 = tcg_temp_new_i64();
1067 t1 = tcg_temp_new_i64();
1068 #if defined(TARGET_PPC64)
1069 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1070 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1071 tcg_gen_mul_i64(t0, t0, t1);
1072 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1073 #else
1074 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1075 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1076 tcg_gen_mul_i64(t0, t0, t1);
1077 tcg_gen_shri_i64(t0, t0, 32);
1078 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1079 #endif
1080 tcg_temp_free_i64(t0);
1081 tcg_temp_free_i64(t1);
1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1084 }
1085
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext *ctx)
1088 {
1089 TCGv_i64 t0, t1;
1090
1091 t0 = tcg_temp_new_i64();
1092 t1 = tcg_temp_new_i64();
1093 #if defined(TARGET_PPC64)
1094 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1095 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1096 tcg_gen_mul_i64(t0, t0, t1);
1097 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1098 #else
1099 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1100 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1101 tcg_gen_mul_i64(t0, t0, t1);
1102 tcg_gen_shri_i64(t0, t0, 32);
1103 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1104 #endif
1105 tcg_temp_free_i64(t0);
1106 tcg_temp_free_i64(t1);
1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1109 }
1110
1111 /* mullw mullw. */
1112 static void gen_mullw(DisasContext *ctx)
1113 {
1114 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1117 if (unlikely(Rc(ctx->opcode) != 0))
1118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1119 }
1120
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext *ctx)
1123 {
1124 int l1;
1125 TCGv_i64 t0, t1;
1126
1127 t0 = tcg_temp_new_i64();
1128 t1 = tcg_temp_new_i64();
1129 l1 = gen_new_label();
1130 /* Start with XER OV disabled, the most likely case */
1131 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1132 #if defined(TARGET_PPC64)
1133 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1134 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1135 #else
1136 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1137 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1138 #endif
1139 tcg_gen_mul_i64(t0, t0, t1);
1140 #if defined(TARGET_PPC64)
1141 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1142 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1143 #else
1144 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1145 tcg_gen_ext32s_i64(t1, t0);
1146 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1147 #endif
1148 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1149 gen_set_label(l1);
1150 tcg_temp_free_i64(t0);
1151 tcg_temp_free_i64(t1);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1154 }
1155
1156 /* mulli */
1157 static void gen_mulli(DisasContext *ctx)
1158 {
1159 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1160 SIMM(ctx->opcode));
1161 }
1162 #if defined(TARGET_PPC64)
1163 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1164 static void glue(gen_, name)(DisasContext *ctx) \
1165 { \
1166 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1168 if (unlikely(Rc(ctx->opcode) != 0)) \
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1170 }
1171 /* mulhd mulhd. */
1172 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1173 /* mulhdu mulhdu. */
1174 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1175
1176 /* mulld mulld. */
1177 static void gen_mulld(DisasContext *ctx)
1178 {
1179 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1180 cpu_gpr[rB(ctx->opcode)]);
1181 if (unlikely(Rc(ctx->opcode) != 0))
1182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1183 }
1184
1185 /* mulldo mulldo. */
1186 static void gen_mulldo(DisasContext *ctx)
1187 {
1188 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1189 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1190 if (unlikely(Rc(ctx->opcode) != 0)) {
1191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1192 }
1193 }
1194 #endif
1195
1196 /* neg neg. nego nego. */
1197 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1198 int ov_check)
1199 {
1200 int l1 = gen_new_label();
1201 int l2 = gen_new_label();
1202 TCGv t0 = tcg_temp_local_new();
1203 #if defined(TARGET_PPC64)
1204 if (ctx->sf_mode) {
1205 tcg_gen_mov_tl(t0, arg1);
1206 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1207 } else
1208 #endif
1209 {
1210 tcg_gen_ext32s_tl(t0, arg1);
1211 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1212 }
1213 tcg_gen_neg_tl(ret, arg1);
1214 if (ov_check) {
1215 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1216 }
1217 tcg_gen_br(l2);
1218 gen_set_label(l1);
1219 tcg_gen_mov_tl(ret, t0);
1220 if (ov_check) {
1221 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1222 }
1223 gen_set_label(l2);
1224 tcg_temp_free(t0);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, ret);
1227 }
1228
1229 static void gen_neg(DisasContext *ctx)
1230 {
1231 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1232 }
1233
1234 static void gen_nego(DisasContext *ctx)
1235 {
1236 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1237 }
1238
1239 /* Common subf function */
1240 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1241 TCGv arg2, int add_ca, int compute_ca,
1242 int compute_ov)
1243 {
1244 TCGv t0, t1;
1245
1246 if ((!compute_ca && !compute_ov) ||
1247 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1248 t0 = ret;
1249 } else {
1250 t0 = tcg_temp_local_new();
1251 }
1252
1253 if (add_ca) {
1254 t1 = tcg_temp_local_new();
1255 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1256 tcg_gen_shri_tl(t1, t1, XER_CA);
1257 } else {
1258 TCGV_UNUSED(t1);
1259 }
1260
1261 if (compute_ca && compute_ov) {
1262 /* Start with XER CA and OV disabled, the most likely case */
1263 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1264 } else if (compute_ca) {
1265 /* Start with XER CA disabled, the most likely case */
1266 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1267 } else if (compute_ov) {
1268 /* Start with XER OV disabled, the most likely case */
1269 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1270 }
1271
1272 if (add_ca) {
1273 tcg_gen_not_tl(t0, arg1);
1274 tcg_gen_add_tl(t0, t0, arg2);
1275 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1276 tcg_gen_add_tl(t0, t0, t1);
1277 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1278 tcg_temp_free(t1);
1279 } else {
1280 tcg_gen_sub_tl(t0, arg2, arg1);
1281 if (compute_ca) {
1282 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1283 }
1284 }
1285 if (compute_ov) {
1286 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1287 }
1288
1289 if (unlikely(Rc(ctx->opcode) != 0))
1290 gen_set_Rc0(ctx, t0);
1291
1292 if (!TCGV_EQUAL(t0, ret)) {
1293 tcg_gen_mov_tl(ret, t0);
1294 tcg_temp_free(t0);
1295 }
1296 }
1297 /* Sub functions with Two operands functions */
1298 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1299 static void glue(gen_, name)(DisasContext *ctx) \
1300 { \
1301 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1302 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1303 add_ca, compute_ca, compute_ov); \
1304 }
1305 /* Sub functions with one operand and one immediate */
1306 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1307 add_ca, compute_ca, compute_ov) \
1308 static void glue(gen_, name)(DisasContext *ctx) \
1309 { \
1310 TCGv t0 = tcg_const_local_tl(const_val); \
1311 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1312 cpu_gpr[rA(ctx->opcode)], t0, \
1313 add_ca, compute_ca, compute_ov); \
1314 tcg_temp_free(t0); \
1315 }
1316 /* subf subf. subfo subfo. */
1317 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1318 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1319 /* subfc subfc. subfco subfco. */
1320 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1321 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1322 /* subfe subfe. subfeo subfo. */
1323 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1324 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1325 /* subfme subfme. subfmeo subfmeo. */
1326 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1327 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1328 /* subfze subfze. subfzeo subfzeo.*/
1329 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1330 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1331
1332 /* subfic */
1333 static void gen_subfic(DisasContext *ctx)
1334 {
1335 /* Start with XER CA and OV disabled, the most likely case */
1336 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1337 TCGv t0 = tcg_temp_local_new();
1338 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1339 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1340 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1341 tcg_temp_free(t1);
1342 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1343 tcg_temp_free(t0);
1344 }
1345
1346 /*** Integer logical ***/
1347 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1348 static void glue(gen_, name)(DisasContext *ctx) \
1349 { \
1350 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1351 cpu_gpr[rB(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1354 }
1355
1356 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1357 static void glue(gen_, name)(DisasContext *ctx) \
1358 { \
1359 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1360 if (unlikely(Rc(ctx->opcode) != 0)) \
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1362 }
1363
1364 /* and & and. */
1365 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1366 /* andc & andc. */
1367 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1368
1369 /* andi. */
1370 static void gen_andi_(DisasContext *ctx)
1371 {
1372 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1374 }
1375
1376 /* andis. */
1377 static void gen_andis_(DisasContext *ctx)
1378 {
1379 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381 }
1382
1383 /* cntlzw */
1384 static void gen_cntlzw(DisasContext *ctx)
1385 {
1386 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1387 if (unlikely(Rc(ctx->opcode) != 0))
1388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1389 }
1390 /* eqv & eqv. */
1391 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1392 /* extsb & extsb. */
1393 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1394 /* extsh & extsh. */
1395 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1396 /* nand & nand. */
1397 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1398 /* nor & nor. */
1399 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1400
1401 /* or & or. */
1402 static void gen_or(DisasContext *ctx)
1403 {
1404 int rs, ra, rb;
1405
1406 rs = rS(ctx->opcode);
1407 ra = rA(ctx->opcode);
1408 rb = rB(ctx->opcode);
1409 /* Optimisation for mr. ri case */
1410 if (rs != ra || rs != rb) {
1411 if (rs != rb)
1412 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1413 else
1414 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1415 if (unlikely(Rc(ctx->opcode) != 0))
1416 gen_set_Rc0(ctx, cpu_gpr[ra]);
1417 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1418 gen_set_Rc0(ctx, cpu_gpr[rs]);
1419 #if defined(TARGET_PPC64)
1420 } else {
1421 int prio = 0;
1422
1423 switch (rs) {
1424 case 1:
1425 /* Set process priority to low */
1426 prio = 2;
1427 break;
1428 case 6:
1429 /* Set process priority to medium-low */
1430 prio = 3;
1431 break;
1432 case 2:
1433 /* Set process priority to normal */
1434 prio = 4;
1435 break;
1436 #if !defined(CONFIG_USER_ONLY)
1437 case 31:
1438 if (ctx->mem_idx > 0) {
1439 /* Set process priority to very low */
1440 prio = 1;
1441 }
1442 break;
1443 case 5:
1444 if (ctx->mem_idx > 0) {
1445 /* Set process priority to medium-hight */
1446 prio = 5;
1447 }
1448 break;
1449 case 3:
1450 if (ctx->mem_idx > 0) {
1451 /* Set process priority to high */
1452 prio = 6;
1453 }
1454 break;
1455 case 7:
1456 if (ctx->mem_idx > 1) {
1457 /* Set process priority to very high */
1458 prio = 7;
1459 }
1460 break;
1461 #endif
1462 default:
1463 /* nop */
1464 break;
1465 }
1466 if (prio) {
1467 TCGv t0 = tcg_temp_new();
1468 gen_load_spr(t0, SPR_PPR);
1469 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1470 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1471 gen_store_spr(SPR_PPR, t0);
1472 tcg_temp_free(t0);
1473 }
1474 #endif
1475 }
1476 }
1477 /* orc & orc. */
1478 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1479
1480 /* xor & xor. */
1481 static void gen_xor(DisasContext *ctx)
1482 {
1483 /* Optimisation for "set to zero" case */
1484 if (rS(ctx->opcode) != rB(ctx->opcode))
1485 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1486 else
1487 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1488 if (unlikely(Rc(ctx->opcode) != 0))
1489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1490 }
1491
1492 /* ori */
1493 static void gen_ori(DisasContext *ctx)
1494 {
1495 target_ulong uimm = UIMM(ctx->opcode);
1496
1497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498 /* NOP */
1499 /* XXX: should handle special NOPs for POWER series */
1500 return;
1501 }
1502 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1503 }
1504
1505 /* oris */
1506 static void gen_oris(DisasContext *ctx)
1507 {
1508 target_ulong uimm = UIMM(ctx->opcode);
1509
1510 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1511 /* NOP */
1512 return;
1513 }
1514 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1515 }
1516
1517 /* xori */
1518 static void gen_xori(DisasContext *ctx)
1519 {
1520 target_ulong uimm = UIMM(ctx->opcode);
1521
1522 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1523 /* NOP */
1524 return;
1525 }
1526 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1527 }
1528
1529 /* xoris */
1530 static void gen_xoris(DisasContext *ctx)
1531 {
1532 target_ulong uimm = UIMM(ctx->opcode);
1533
1534 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1535 /* NOP */
1536 return;
1537 }
1538 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1539 }
1540
1541 /* popcntb : PowerPC 2.03 specification */
1542 static void gen_popcntb(DisasContext *ctx)
1543 {
1544 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545 }
1546
1547 static void gen_popcntw(DisasContext *ctx)
1548 {
1549 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1550 }
1551
1552 #if defined(TARGET_PPC64)
1553 /* popcntd: PowerPC 2.06 specification */
1554 static void gen_popcntd(DisasContext *ctx)
1555 {
1556 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1557 }
1558 #endif
1559
1560 #if defined(TARGET_PPC64)
1561 /* extsw & extsw. */
1562 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1563
1564 /* cntlzd */
1565 static void gen_cntlzd(DisasContext *ctx)
1566 {
1567 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571 #endif
1572
1573 /*** Integer rotate ***/
1574
1575 /* rlwimi & rlwimi. */
1576 static void gen_rlwimi(DisasContext *ctx)
1577 {
1578 uint32_t mb, me, sh;
1579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
1582 sh = SH(ctx->opcode);
1583 if (likely(sh == 0 && mb == 0 && me == 31)) {
1584 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1585 } else {
1586 target_ulong mask;
1587 TCGv t1;
1588 TCGv t0 = tcg_temp_new();
1589 #if defined(TARGET_PPC64)
1590 TCGv_i32 t2 = tcg_temp_new_i32();
1591 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1592 tcg_gen_rotli_i32(t2, t2, sh);
1593 tcg_gen_extu_i32_i64(t0, t2);
1594 tcg_temp_free_i32(t2);
1595 #else
1596 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1597 #endif
1598 #if defined(TARGET_PPC64)
1599 mb += 32;
1600 me += 32;
1601 #endif
1602 mask = MASK(mb, me);
1603 t1 = tcg_temp_new();
1604 tcg_gen_andi_tl(t0, t0, mask);
1605 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1606 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1607 tcg_temp_free(t0);
1608 tcg_temp_free(t1);
1609 }
1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612 }
1613
1614 /* rlwinm & rlwinm. */
1615 static void gen_rlwinm(DisasContext *ctx)
1616 {
1617 uint32_t mb, me, sh;
1618
1619 sh = SH(ctx->opcode);
1620 mb = MB(ctx->opcode);
1621 me = ME(ctx->opcode);
1622
1623 if (likely(mb == 0 && me == (31 - sh))) {
1624 if (likely(sh == 0)) {
1625 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 } else {
1627 TCGv t0 = tcg_temp_new();
1628 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1629 tcg_gen_shli_tl(t0, t0, sh);
1630 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1631 tcg_temp_free(t0);
1632 }
1633 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1634 TCGv t0 = tcg_temp_new();
1635 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1636 tcg_gen_shri_tl(t0, t0, mb);
1637 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1638 tcg_temp_free(t0);
1639 } else {
1640 TCGv t0 = tcg_temp_new();
1641 #if defined(TARGET_PPC64)
1642 TCGv_i32 t1 = tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1644 tcg_gen_rotli_i32(t1, t1, sh);
1645 tcg_gen_extu_i32_i64(t0, t1);
1646 tcg_temp_free_i32(t1);
1647 #else
1648 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1649 #endif
1650 #if defined(TARGET_PPC64)
1651 mb += 32;
1652 me += 32;
1653 #endif
1654 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1655 tcg_temp_free(t0);
1656 }
1657 if (unlikely(Rc(ctx->opcode) != 0))
1658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1659 }
1660
1661 /* rlwnm & rlwnm. */
1662 static void gen_rlwnm(DisasContext *ctx)
1663 {
1664 uint32_t mb, me;
1665 TCGv t0;
1666 #if defined(TARGET_PPC64)
1667 TCGv_i32 t1, t2;
1668 #endif
1669
1670 mb = MB(ctx->opcode);
1671 me = ME(ctx->opcode);
1672 t0 = tcg_temp_new();
1673 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1674 #if defined(TARGET_PPC64)
1675 t1 = tcg_temp_new_i32();
1676 t2 = tcg_temp_new_i32();
1677 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1678 tcg_gen_trunc_i64_i32(t2, t0);
1679 tcg_gen_rotl_i32(t1, t1, t2);
1680 tcg_gen_extu_i32_i64(t0, t1);
1681 tcg_temp_free_i32(t1);
1682 tcg_temp_free_i32(t2);
1683 #else
1684 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1685 #endif
1686 if (unlikely(mb != 0 || me != 31)) {
1687 #if defined(TARGET_PPC64)
1688 mb += 32;
1689 me += 32;
1690 #endif
1691 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1692 } else {
1693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1694 }
1695 tcg_temp_free(t0);
1696 if (unlikely(Rc(ctx->opcode) != 0))
1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1698 }
1699
1700 #if defined(TARGET_PPC64)
1701 #define GEN_PPC64_R2(name, opc1, opc2) \
1702 static void glue(gen_, name##0)(DisasContext *ctx) \
1703 { \
1704 gen_##name(ctx, 0); \
1705 } \
1706 \
1707 static void glue(gen_, name##1)(DisasContext *ctx) \
1708 { \
1709 gen_##name(ctx, 1); \
1710 }
1711 #define GEN_PPC64_R4(name, opc1, opc2) \
1712 static void glue(gen_, name##0)(DisasContext *ctx) \
1713 { \
1714 gen_##name(ctx, 0, 0); \
1715 } \
1716 \
1717 static void glue(gen_, name##1)(DisasContext *ctx) \
1718 { \
1719 gen_##name(ctx, 0, 1); \
1720 } \
1721 \
1722 static void glue(gen_, name##2)(DisasContext *ctx) \
1723 { \
1724 gen_##name(ctx, 1, 0); \
1725 } \
1726 \
1727 static void glue(gen_, name##3)(DisasContext *ctx) \
1728 { \
1729 gen_##name(ctx, 1, 1); \
1730 }
1731
1732 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1733 uint32_t sh)
1734 {
1735 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1736 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1737 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1738 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1739 } else {
1740 TCGv t0 = tcg_temp_new();
1741 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1742 if (likely(mb == 0 && me == 63)) {
1743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1744 } else {
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 }
1747 tcg_temp_free(t0);
1748 }
1749 if (unlikely(Rc(ctx->opcode) != 0))
1750 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1751 }
1752 /* rldicl - rldicl. */
1753 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1754 {
1755 uint32_t sh, mb;
1756
1757 sh = SH(ctx->opcode) | (shn << 5);
1758 mb = MB(ctx->opcode) | (mbn << 5);
1759 gen_rldinm(ctx, mb, 63, sh);
1760 }
1761 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1762 /* rldicr - rldicr. */
1763 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1764 {
1765 uint32_t sh, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 me = MB(ctx->opcode) | (men << 5);
1769 gen_rldinm(ctx, 0, me, sh);
1770 }
1771 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1772 /* rldic - rldic. */
1773 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1774 {
1775 uint32_t sh, mb;
1776
1777 sh = SH(ctx->opcode) | (shn << 5);
1778 mb = MB(ctx->opcode) | (mbn << 5);
1779 gen_rldinm(ctx, mb, 63 - sh, sh);
1780 }
1781 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1782
1783 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1784 {
1785 TCGv t0;
1786
1787 mb = MB(ctx->opcode);
1788 me = ME(ctx->opcode);
1789 t0 = tcg_temp_new();
1790 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1791 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1792 if (unlikely(mb != 0 || me != 63)) {
1793 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1794 } else {
1795 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1796 }
1797 tcg_temp_free(t0);
1798 if (unlikely(Rc(ctx->opcode) != 0))
1799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1800 }
1801
1802 /* rldcl - rldcl. */
1803 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1804 {
1805 uint32_t mb;
1806
1807 mb = MB(ctx->opcode) | (mbn << 5);
1808 gen_rldnm(ctx, mb, 63);
1809 }
1810 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1811 /* rldcr - rldcr. */
1812 static inline void gen_rldcr(DisasContext *ctx, int men)
1813 {
1814 uint32_t me;
1815
1816 me = MB(ctx->opcode) | (men << 5);
1817 gen_rldnm(ctx, 0, me);
1818 }
1819 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1820 /* rldimi - rldimi. */
1821 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1822 {
1823 uint32_t sh, mb, me;
1824
1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
1827 me = 63 - sh;
1828 if (unlikely(sh == 0 && mb == 0)) {
1829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1830 } else {
1831 TCGv t0, t1;
1832 target_ulong mask;
1833
1834 t0 = tcg_temp_new();
1835 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1836 t1 = tcg_temp_new();
1837 mask = MASK(mb, me);
1838 tcg_gen_andi_tl(t0, t0, mask);
1839 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1840 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1841 tcg_temp_free(t0);
1842 tcg_temp_free(t1);
1843 }
1844 if (unlikely(Rc(ctx->opcode) != 0))
1845 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1846 }
1847 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1848 #endif
1849
1850 /*** Integer shift ***/
1851
1852 /* slw & slw. */
1853 static void gen_slw(DisasContext *ctx)
1854 {
1855 TCGv t0, t1;
1856
1857 t0 = tcg_temp_new();
1858 /* AND rS with a mask that is 0 when rB >= 0x20 */
1859 #if defined(TARGET_PPC64)
1860 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1861 tcg_gen_sari_tl(t0, t0, 0x3f);
1862 #else
1863 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1864 tcg_gen_sari_tl(t0, t0, 0x1f);
1865 #endif
1866 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1867 t1 = tcg_temp_new();
1868 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1869 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1870 tcg_temp_free(t1);
1871 tcg_temp_free(t0);
1872 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1873 if (unlikely(Rc(ctx->opcode) != 0))
1874 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1875 }
1876
1877 /* sraw & sraw. */
1878 static void gen_sraw(DisasContext *ctx)
1879 {
1880 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1881 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1882 if (unlikely(Rc(ctx->opcode) != 0))
1883 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1884 }
1885
1886 /* srawi & srawi. */
1887 static void gen_srawi(DisasContext *ctx)
1888 {
1889 int sh = SH(ctx->opcode);
1890 if (sh != 0) {
1891 int l1, l2;
1892 TCGv t0;
1893 l1 = gen_new_label();
1894 l2 = gen_new_label();
1895 t0 = tcg_temp_local_new();
1896 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1897 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1898 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1899 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1900 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1901 tcg_gen_br(l2);
1902 gen_set_label(l1);
1903 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1904 gen_set_label(l2);
1905 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1906 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1907 tcg_temp_free(t0);
1908 } else {
1909 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1910 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1911 }
1912 if (unlikely(Rc(ctx->opcode) != 0))
1913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1914 }
1915
1916 /* srw & srw. */
1917 static void gen_srw(DisasContext *ctx)
1918 {
1919 TCGv t0, t1;
1920
1921 t0 = tcg_temp_new();
1922 /* AND rS with a mask that is 0 when rB >= 0x20 */
1923 #if defined(TARGET_PPC64)
1924 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1925 tcg_gen_sari_tl(t0, t0, 0x3f);
1926 #else
1927 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1928 tcg_gen_sari_tl(t0, t0, 0x1f);
1929 #endif
1930 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1931 tcg_gen_ext32u_tl(t0, t0);
1932 t1 = tcg_temp_new();
1933 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1934 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1935 tcg_temp_free(t1);
1936 tcg_temp_free(t0);
1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939 }
1940
1941 #if defined(TARGET_PPC64)
1942 /* sld & sld. */
1943 static void gen_sld(DisasContext *ctx)
1944 {
1945 TCGv t0, t1;
1946
1947 t0 = tcg_temp_new();
1948 /* AND rS with a mask that is 0 when rB >= 0x40 */
1949 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1950 tcg_gen_sari_tl(t0, t0, 0x3f);
1951 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1952 t1 = tcg_temp_new();
1953 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1954 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1955 tcg_temp_free(t1);
1956 tcg_temp_free(t0);
1957 if (unlikely(Rc(ctx->opcode) != 0))
1958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1959 }
1960
1961 /* srad & srad. */
1962 static void gen_srad(DisasContext *ctx)
1963 {
1964 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1965 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1966 if (unlikely(Rc(ctx->opcode) != 0))
1967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1968 }
1969 /* sradi & sradi. */
1970 static inline void gen_sradi(DisasContext *ctx, int n)
1971 {
1972 int sh = SH(ctx->opcode) + (n << 5);
1973 if (sh != 0) {
1974 int l1, l2;
1975 TCGv t0;
1976 l1 = gen_new_label();
1977 l2 = gen_new_label();
1978 t0 = tcg_temp_local_new();
1979 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1980 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1981 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1982 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1983 tcg_gen_br(l2);
1984 gen_set_label(l1);
1985 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1986 gen_set_label(l2);
1987 tcg_temp_free(t0);
1988 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1989 } else {
1990 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1991 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1992 }
1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995 }
1996
1997 static void gen_sradi0(DisasContext *ctx)
1998 {
1999 gen_sradi(ctx, 0);
2000 }
2001
2002 static void gen_sradi1(DisasContext *ctx)
2003 {
2004 gen_sradi(ctx, 1);
2005 }
2006
2007 /* srd & srd. */
2008 static void gen_srd(DisasContext *ctx)
2009 {
2010 TCGv t0, t1;
2011
2012 t0 = tcg_temp_new();
2013 /* AND rS with a mask that is 0 when rB >= 0x40 */
2014 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2015 tcg_gen_sari_tl(t0, t0, 0x3f);
2016 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2017 t1 = tcg_temp_new();
2018 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2019 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2020 tcg_temp_free(t1);
2021 tcg_temp_free(t0);
2022 if (unlikely(Rc(ctx->opcode) != 0))
2023 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2024 }
2025 #endif
2026
2027 /*** Floating-Point arithmetic ***/
2028 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2029 static void gen_f##name(DisasContext *ctx) \
2030 { \
2031 if (unlikely(!ctx->fpu_enabled)) { \
2032 gen_exception(ctx, POWERPC_EXCP_FPU); \
2033 return; \
2034 } \
2035 /* NIP cannot be restored if the memory exception comes from an helper */ \
2036 gen_update_nip(ctx, ctx->nip - 4); \
2037 gen_reset_fpstatus(); \
2038 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2039 cpu_fpr[rA(ctx->opcode)], \
2040 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2041 if (isfloat) { \
2042 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2043 cpu_fpr[rD(ctx->opcode)]); \
2044 } \
2045 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2046 Rc(ctx->opcode) != 0); \
2047 }
2048
2049 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2050 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2051 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2052
2053 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2054 static void gen_f##name(DisasContext *ctx) \
2055 { \
2056 if (unlikely(!ctx->fpu_enabled)) { \
2057 gen_exception(ctx, POWERPC_EXCP_FPU); \
2058 return; \
2059 } \
2060 /* NIP cannot be restored if the memory exception comes from an helper */ \
2061 gen_update_nip(ctx, ctx->nip - 4); \
2062 gen_reset_fpstatus(); \
2063 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2064 cpu_fpr[rA(ctx->opcode)], \
2065 cpu_fpr[rB(ctx->opcode)]); \
2066 if (isfloat) { \
2067 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rD(ctx->opcode)]); \
2069 } \
2070 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2071 set_fprf, Rc(ctx->opcode) != 0); \
2072 }
2073 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2074 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2075 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2076
2077 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2078 static void gen_f##name(DisasContext *ctx) \
2079 { \
2080 if (unlikely(!ctx->fpu_enabled)) { \
2081 gen_exception(ctx, POWERPC_EXCP_FPU); \
2082 return; \
2083 } \
2084 /* NIP cannot be restored if the memory exception comes from an helper */ \
2085 gen_update_nip(ctx, ctx->nip - 4); \
2086 gen_reset_fpstatus(); \
2087 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2088 cpu_fpr[rA(ctx->opcode)], \
2089 cpu_fpr[rC(ctx->opcode)]); \
2090 if (isfloat) { \
2091 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2092 cpu_fpr[rD(ctx->opcode)]); \
2093 } \
2094 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2095 set_fprf, Rc(ctx->opcode) != 0); \
2096 }
2097 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2098 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2099 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2100
2101 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2102 static void gen_f##name(DisasContext *ctx) \
2103 { \
2104 if (unlikely(!ctx->fpu_enabled)) { \
2105 gen_exception(ctx, POWERPC_EXCP_FPU); \
2106 return; \
2107 } \
2108 /* NIP cannot be restored if the memory exception comes from an helper */ \
2109 gen_update_nip(ctx, ctx->nip - 4); \
2110 gen_reset_fpstatus(); \
2111 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2112 cpu_fpr[rB(ctx->opcode)]); \
2113 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2114 set_fprf, Rc(ctx->opcode) != 0); \
2115 }
2116
2117 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2118 static void gen_f##name(DisasContext *ctx) \
2119 { \
2120 if (unlikely(!ctx->fpu_enabled)) { \
2121 gen_exception(ctx, POWERPC_EXCP_FPU); \
2122 return; \
2123 } \
2124 /* NIP cannot be restored if the memory exception comes from an helper */ \
2125 gen_update_nip(ctx, ctx->nip - 4); \
2126 gen_reset_fpstatus(); \
2127 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2128 cpu_fpr[rB(ctx->opcode)]); \
2129 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2130 set_fprf, Rc(ctx->opcode) != 0); \
2131 }
2132
2133 /* fadd - fadds */
2134 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2135 /* fdiv - fdivs */
2136 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2137 /* fmul - fmuls */
2138 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2139
2140 /* fre */
2141 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2142
2143 /* fres */
2144 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2145
2146 /* frsqrte */
2147 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2148
2149 /* frsqrtes */
2150 static void gen_frsqrtes(DisasContext *ctx)
2151 {
2152 if (unlikely(!ctx->fpu_enabled)) {
2153 gen_exception(ctx, POWERPC_EXCP_FPU);
2154 return;
2155 }
2156 /* NIP cannot be restored if the memory exception comes from an helper */
2157 gen_update_nip(ctx, ctx->nip - 4);
2158 gen_reset_fpstatus();
2159 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2160 cpu_fpr[rB(ctx->opcode)]);
2161 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2162 cpu_fpr[rD(ctx->opcode)]);
2163 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2164 }
2165
2166 /* fsel */
2167 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2168 /* fsub - fsubs */
2169 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2170 /* Optional: */
2171
2172 /* fsqrt */
2173 static void gen_fsqrt(DisasContext *ctx)
2174 {
2175 if (unlikely(!ctx->fpu_enabled)) {
2176 gen_exception(ctx, POWERPC_EXCP_FPU);
2177 return;
2178 }
2179 /* NIP cannot be restored if the memory exception comes from an helper */
2180 gen_update_nip(ctx, ctx->nip - 4);
2181 gen_reset_fpstatus();
2182 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2183 cpu_fpr[rB(ctx->opcode)]);
2184 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2185 }
2186
2187 static void gen_fsqrts(DisasContext *ctx)
2188 {
2189 if (unlikely(!ctx->fpu_enabled)) {
2190 gen_exception(ctx, POWERPC_EXCP_FPU);
2191 return;
2192 }
2193 /* NIP cannot be restored if the memory exception comes from an helper */
2194 gen_update_nip(ctx, ctx->nip - 4);
2195 gen_reset_fpstatus();
2196 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2197 cpu_fpr[rB(ctx->opcode)]);
2198 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2199 cpu_fpr[rD(ctx->opcode)]);
2200 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2201 }
2202
2203 /*** Floating-Point multiply-and-add ***/
2204 /* fmadd - fmadds */
2205 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2206 /* fmsub - fmsubs */
2207 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2208 /* fnmadd - fnmadds */
2209 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2210 /* fnmsub - fnmsubs */
2211 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2212
2213 /*** Floating-Point round & convert ***/
2214 /* fctiw */
2215 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2216 /* fctiwz */
2217 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2218 /* frsp */
2219 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2220 #if defined(TARGET_PPC64)
2221 /* fcfid */
2222 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2223 /* fctid */
2224 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2225 /* fctidz */
2226 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2227 #endif
2228
2229 /* frin */
2230 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2231 /* friz */
2232 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2233 /* frip */
2234 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2235 /* frim */
2236 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2237
2238 /*** Floating-Point compare ***/
2239
2240 /* fcmpo */
2241 static void gen_fcmpo(DisasContext *ctx)
2242 {
2243 TCGv_i32 crf;
2244 if (unlikely(!ctx->fpu_enabled)) {
2245 gen_exception(ctx, POWERPC_EXCP_FPU);
2246 return;
2247 }
2248 /* NIP cannot be restored if the memory exception comes from an helper */
2249 gen_update_nip(ctx, ctx->nip - 4);
2250 gen_reset_fpstatus();
2251 crf = tcg_const_i32(crfD(ctx->opcode));
2252 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2253 cpu_fpr[rB(ctx->opcode)], crf);
2254 tcg_temp_free_i32(crf);
2255 gen_helper_float_check_status(cpu_env);
2256 }
2257
2258 /* fcmpu */
2259 static void gen_fcmpu(DisasContext *ctx)
2260 {
2261 TCGv_i32 crf;
2262 if (unlikely(!ctx->fpu_enabled)) {
2263 gen_exception(ctx, POWERPC_EXCP_FPU);
2264 return;
2265 }
2266 /* NIP cannot be restored if the memory exception comes from an helper */
2267 gen_update_nip(ctx, ctx->nip - 4);
2268 gen_reset_fpstatus();
2269 crf = tcg_const_i32(crfD(ctx->opcode));
2270 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2271 cpu_fpr[rB(ctx->opcode)], crf);
2272 tcg_temp_free_i32(crf);
2273 gen_helper_float_check_status(cpu_env);
2274 }
2275
2276 /*** Floating-point move ***/
2277 /* fabs */
2278 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2279 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2280
2281 /* fmr - fmr. */
2282 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2283 static void gen_fmr(DisasContext *ctx)
2284 {
2285 if (unlikely(!ctx->fpu_enabled)) {
2286 gen_exception(ctx, POWERPC_EXCP_FPU);
2287 return;
2288 }
2289 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2290 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2291 }
2292
2293 /* fnabs */
2294 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2295 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2296 /* fneg */
2297 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2298 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2299
2300 /*** Floating-Point status & ctrl register ***/
2301
2302 /* mcrfs */
2303 static void gen_mcrfs(DisasContext *ctx)
2304 {
2305 int bfa;
2306
2307 if (unlikely(!ctx->fpu_enabled)) {
2308 gen_exception(ctx, POWERPC_EXCP_FPU);
2309 return;
2310 }
2311 bfa = 4 * (7 - crfS(ctx->opcode));
2312 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2313 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2314 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2315 }
2316
2317 /* mffs */
2318 static void gen_mffs(DisasContext *ctx)
2319 {
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_reset_fpstatus();
2325 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2326 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2327 }
2328
2329 /* mtfsb0 */
2330 static void gen_mtfsb0(DisasContext *ctx)
2331 {
2332 uint8_t crb;
2333
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 crb = 31 - crbD(ctx->opcode);
2339 gen_reset_fpstatus();
2340 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2341 TCGv_i32 t0;
2342 /* NIP cannot be restored if the memory exception comes from an helper */
2343 gen_update_nip(ctx, ctx->nip - 4);
2344 t0 = tcg_const_i32(crb);
2345 gen_helper_fpscr_clrbit(cpu_env, t0);
2346 tcg_temp_free_i32(t0);
2347 }
2348 if (unlikely(Rc(ctx->opcode) != 0)) {
2349 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2350 }
2351 }
2352
2353 /* mtfsb1 */
2354 static void gen_mtfsb1(DisasContext *ctx)
2355 {
2356 uint8_t crb;
2357
2358 if (unlikely(!ctx->fpu_enabled)) {
2359 gen_exception(ctx, POWERPC_EXCP_FPU);
2360 return;
2361 }
2362 crb = 31 - crbD(ctx->opcode);
2363 gen_reset_fpstatus();
2364 /* XXX: we pretend we can only do IEEE floating-point computations */
2365 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2366 TCGv_i32 t0;
2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
2369 t0 = tcg_const_i32(crb);
2370 gen_helper_fpscr_setbit(cpu_env, t0);
2371 tcg_temp_free_i32(t0);
2372 }
2373 if (unlikely(Rc(ctx->opcode) != 0)) {
2374 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2375 }
2376 /* We can raise a differed exception */
2377 gen_helper_float_check_status(cpu_env);
2378 }
2379
2380 /* mtfsf */
2381 static void gen_mtfsf(DisasContext *ctx)
2382 {
2383 TCGv_i32 t0;
2384 int L = ctx->opcode & 0x02000000;
2385
2386 if (unlikely(!ctx->fpu_enabled)) {
2387 gen_exception(ctx, POWERPC_EXCP_FPU);
2388 return;
2389 }
2390 /* NIP cannot be restored if the memory exception comes from an helper */
2391 gen_update_nip(ctx, ctx->nip - 4);
2392 gen_reset_fpstatus();
2393 if (L)
2394 t0 = tcg_const_i32(0xff);
2395 else
2396 t0 = tcg_const_i32(FM(ctx->opcode));
2397 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2398 tcg_temp_free_i32(t0);
2399 if (unlikely(Rc(ctx->opcode) != 0)) {
2400 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2401 }
2402 /* We can raise a differed exception */
2403 gen_helper_float_check_status(cpu_env);
2404 }
2405
2406 /* mtfsfi */
2407 static void gen_mtfsfi(DisasContext *ctx)
2408 {
2409 int bf, sh;
2410 TCGv_i64 t0;
2411 TCGv_i32 t1;
2412
2413 if (unlikely(!ctx->fpu_enabled)) {
2414 gen_exception(ctx, POWERPC_EXCP_FPU);
2415 return;
2416 }
2417 bf = crbD(ctx->opcode) >> 2;
2418 sh = 7 - bf;
2419 /* NIP cannot be restored if the memory exception comes from an helper */
2420 gen_update_nip(ctx, ctx->nip - 4);
2421 gen_reset_fpstatus();
2422 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2423 t1 = tcg_const_i32(1 << sh);
2424 gen_helper_store_fpscr(cpu_env, t0, t1);
2425 tcg_temp_free_i64(t0);
2426 tcg_temp_free_i32(t1);
2427 if (unlikely(Rc(ctx->opcode) != 0)) {
2428 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2429 }
2430 /* We can raise a differed exception */
2431 gen_helper_float_check_status(cpu_env);
2432 }
2433
2434 /*** Addressing modes ***/
2435 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2436 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2437 target_long maskl)
2438 {
2439 target_long simm = SIMM(ctx->opcode);
2440
2441 simm &= ~maskl;
2442 if (rA(ctx->opcode) == 0) {
2443 #if defined(TARGET_PPC64)
2444 if (!ctx->sf_mode) {
2445 tcg_gen_movi_tl(EA, (uint32_t)simm);
2446 } else
2447 #endif
2448 tcg_gen_movi_tl(EA, simm);
2449 } else if (likely(simm != 0)) {
2450 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2451 #if defined(TARGET_PPC64)
2452 if (!ctx->sf_mode) {
2453 tcg_gen_ext32u_tl(EA, EA);
2454 }
2455 #endif
2456 } else {
2457 #if defined(TARGET_PPC64)
2458 if (!ctx->sf_mode) {
2459 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2460 } else
2461 #endif
2462 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2463 }
2464 }
2465
2466 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2467 {
2468 if (rA(ctx->opcode) == 0) {
2469 #if defined(TARGET_PPC64)
2470 if (!ctx->sf_mode) {
2471 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2472 } else
2473 #endif
2474 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2475 } else {
2476 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2477 #if defined(TARGET_PPC64)
2478 if (!ctx->sf_mode) {
2479 tcg_gen_ext32u_tl(EA, EA);
2480 }
2481 #endif
2482 }
2483 }
2484
2485 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2486 {
2487 if (rA(ctx->opcode) == 0) {
2488 tcg_gen_movi_tl(EA, 0);
2489 } else {
2490 #if defined(TARGET_PPC64)
2491 if (!ctx->sf_mode) {
2492 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2493 } else
2494 #endif
2495 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2496 }
2497 }
2498
2499 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2500 target_long val)
2501 {
2502 tcg_gen_addi_tl(ret, arg1, val);
2503 #if defined(TARGET_PPC64)
2504 if (!ctx->sf_mode) {
2505 tcg_gen_ext32u_tl(ret, ret);
2506 }
2507 #endif
2508 }
2509
2510 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2511 {
2512 int l1 = gen_new_label();
2513 TCGv t0 = tcg_temp_new();
2514 TCGv_i32 t1, t2;
2515 /* NIP cannot be restored if the memory exception comes from an helper */
2516 gen_update_nip(ctx, ctx->nip - 4);
2517 tcg_gen_andi_tl(t0, EA, mask);
2518 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2519 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2520 t2 = tcg_const_i32(0);
2521 gen_helper_raise_exception_err(cpu_env, t1, t2);
2522 tcg_temp_free_i32(t1);
2523 tcg_temp_free_i32(t2);
2524 gen_set_label(l1);
2525 tcg_temp_free(t0);
2526 }
2527
2528 /*** Integer load ***/
2529 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2530 {
2531 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2532 }
2533
2534 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2535 {
2536 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2537 }
2538
2539 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2540 {
2541 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2542 if (unlikely(ctx->le_mode)) {
2543 tcg_gen_bswap16_tl(arg1, arg1);
2544 }
2545 }
2546
2547 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2548 {
2549 if (unlikely(ctx->le_mode)) {
2550 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2551 tcg_gen_bswap16_tl(arg1, arg1);
2552 tcg_gen_ext16s_tl(arg1, arg1);
2553 } else {
2554 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2555 }
2556 }
2557
2558 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2559 {
2560 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2561 if (unlikely(ctx->le_mode)) {
2562 tcg_gen_bswap32_tl(arg1, arg1);
2563 }
2564 }
2565
2566 #if defined(TARGET_PPC64)
2567 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2568 {
2569 if (unlikely(ctx->le_mode)) {
2570 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2571 tcg_gen_bswap32_tl(arg1, arg1);
2572 tcg_gen_ext32s_tl(arg1, arg1);
2573 } else
2574 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2575 }
2576 #endif
2577
2578 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2579 {
2580 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2581 if (unlikely(ctx->le_mode)) {
2582 tcg_gen_bswap64_i64(arg1, arg1);
2583 }
2584 }
2585
2586 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2587 {
2588 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2589 }
2590
2591 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2592 {
2593 if (unlikely(ctx->le_mode)) {
2594 TCGv t0 = tcg_temp_new();
2595 tcg_gen_ext16u_tl(t0, arg1);
2596 tcg_gen_bswap16_tl(t0, t0);
2597 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2598 tcg_temp_free(t0);
2599 } else {
2600 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2601 }
2602 }
2603
2604 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2605 {
2606 if (unlikely(ctx->le_mode)) {
2607 TCGv t0 = tcg_temp_new();
2608 tcg_gen_ext32u_tl(t0, arg1);
2609 tcg_gen_bswap32_tl(t0, t0);
2610 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2611 tcg_temp_free(t0);
2612 } else {
2613 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2614 }
2615 }
2616
2617 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2618 {
2619 if (unlikely(ctx->le_mode)) {
2620 TCGv_i64 t0 = tcg_temp_new_i64();
2621 tcg_gen_bswap64_i64(t0, arg1);
2622 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2623 tcg_temp_free_i64(t0);
2624 } else
2625 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2626 }
2627
2628 #define GEN_LD(name, ldop, opc, type) \
2629 static void glue(gen_, name)(DisasContext *ctx) \
2630 { \
2631 TCGv EA; \
2632 gen_set_access_type(ctx, ACCESS_INT); \
2633 EA = tcg_temp_new(); \
2634 gen_addr_imm_index(ctx, EA, 0); \
2635 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2636 tcg_temp_free(EA); \
2637 }
2638
2639 #define GEN_LDU(name, ldop, opc, type) \
2640 static void glue(gen_, name##u)(DisasContext *ctx) \
2641 { \
2642 TCGv EA; \
2643 if (unlikely(rA(ctx->opcode) == 0 || \
2644 rA(ctx->opcode) == rD(ctx->opcode))) { \
2645 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2646 return; \
2647 } \
2648 gen_set_access_type(ctx, ACCESS_INT); \
2649 EA = tcg_temp_new(); \
2650 if (type == PPC_64B) \
2651 gen_addr_imm_index(ctx, EA, 0x03); \
2652 else \
2653 gen_addr_imm_index(ctx, EA, 0); \
2654 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2655 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2656 tcg_temp_free(EA); \
2657 }
2658
2659 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2660 static void glue(gen_, name##ux)(DisasContext *ctx) \
2661 { \
2662 TCGv EA; \
2663 if (unlikely(rA(ctx->opcode) == 0 || \
2664 rA(ctx->opcode) == rD(ctx->opcode))) { \
2665 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2666 return; \
2667 } \
2668 gen_set_access_type(ctx, ACCESS_INT); \
2669 EA = tcg_temp_new(); \
2670 gen_addr_reg_index(ctx, EA); \
2671 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2672 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2673 tcg_temp_free(EA); \
2674 }
2675
2676 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2677 static void glue(gen_, name##x)(DisasContext *ctx) \
2678 { \
2679 TCGv EA; \
2680 gen_set_access_type(ctx, ACCESS_INT); \
2681 EA = tcg_temp_new(); \
2682 gen_addr_reg_index(ctx, EA); \
2683 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2684 tcg_temp_free(EA); \
2685 }
2686 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2687 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2688
2689 #define GEN_LDS(name, ldop, op, type) \
2690 GEN_LD(name, ldop, op | 0x20, type); \
2691 GEN_LDU(name, ldop, op | 0x21, type); \
2692 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2693 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2694
2695 /* lbz lbzu lbzux lbzx */
2696 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2697 /* lha lhau lhaux lhax */
2698 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2699 /* lhz lhzu lhzux lhzx */
2700 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2701 /* lwz lwzu lwzux lwzx */
2702 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2703 #if defined(TARGET_PPC64)
2704 /* lwaux */
2705 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2706 /* lwax */
2707 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2708 /* ldux */
2709 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2710 /* ldx */
2711 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2712
2713 static void gen_ld(DisasContext *ctx)
2714 {
2715 TCGv EA;
2716 if (Rc(ctx->opcode)) {
2717 if (unlikely(rA(ctx->opcode) == 0 ||
2718 rA(ctx->opcode) == rD(ctx->opcode))) {
2719 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2720 return;
2721 }
2722 }
2723 gen_set_access_type(ctx, ACCESS_INT);
2724 EA = tcg_temp_new();
2725 gen_addr_imm_index(ctx, EA, 0x03);
2726 if (ctx->opcode & 0x02) {
2727 /* lwa (lwau is undefined) */
2728 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2729 } else {
2730 /* ld - ldu */
2731 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2732 }
2733 if (Rc(ctx->opcode))
2734 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2735 tcg_temp_free(EA);
2736 }
2737
2738 /* lq */
2739 static void gen_lq(DisasContext *ctx)
2740 {
2741 #if defined(CONFIG_USER_ONLY)
2742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2743 #else
2744 int ra, rd;
2745 TCGv EA;
2746
2747 /* Restore CPU state */
2748 if (unlikely(ctx->mem_idx == 0)) {
2749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2750 return;
2751 }
2752 ra = rA(ctx->opcode);
2753 rd = rD(ctx->opcode);
2754 if (unlikely((rd & 1) || rd == ra)) {
2755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2756 return;
2757 }
2758 if (unlikely(ctx->le_mode)) {
2759 /* Little-endian mode is not handled */
2760 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2761 return;
2762 }
2763 gen_set_access_type(ctx, ACCESS_INT);
2764 EA = tcg_temp_new();
2765 gen_addr_imm_index(ctx, EA, 0x0F);
2766 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2767 gen_addr_add(ctx, EA, EA, 8);
2768 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2769 tcg_temp_free(EA);
2770 #endif
2771 }
2772 #endif
2773
2774 /*** Integer store ***/
2775 #define GEN_ST(name, stop, opc, type) \
2776 static void glue(gen_, name)(DisasContext *ctx) \
2777 { \
2778 TCGv EA; \
2779 gen_set_access_type(ctx, ACCESS_INT); \
2780 EA = tcg_temp_new(); \
2781 gen_addr_imm_index(ctx, EA, 0); \
2782 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2783 tcg_temp_free(EA); \
2784 }
2785
2786 #define GEN_STU(name, stop, opc, type) \
2787 static void glue(gen_, stop##u)(DisasContext *ctx) \
2788 { \
2789 TCGv EA; \
2790 if (unlikely(rA(ctx->opcode) == 0)) { \
2791 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2792 return; \
2793 } \
2794 gen_set_access_type(ctx, ACCESS_INT); \
2795 EA = tcg_temp_new(); \
2796 if (type == PPC_64B) \
2797 gen_addr_imm_index(ctx, EA, 0x03); \
2798 else \
2799 gen_addr_imm_index(ctx, EA, 0); \
2800 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2801 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2802 tcg_temp_free(EA); \
2803 }
2804
2805 #define GEN_STUX(name, stop, opc2, opc3, type) \
2806 static void glue(gen_, name##ux)(DisasContext *ctx) \
2807 { \
2808 TCGv EA; \
2809 if (unlikely(rA(ctx->opcode) == 0)) { \
2810 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2811 return; \
2812 } \
2813 gen_set_access_type(ctx, ACCESS_INT); \
2814 EA = tcg_temp_new(); \
2815 gen_addr_reg_index(ctx, EA); \
2816 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2817 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2818 tcg_temp_free(EA); \
2819 }
2820
2821 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2822 static void glue(gen_, name##x)(DisasContext *ctx) \
2823 { \
2824 TCGv EA; \
2825 gen_set_access_type(ctx, ACCESS_INT); \
2826 EA = tcg_temp_new(); \
2827 gen_addr_reg_index(ctx, EA); \
2828 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2829 tcg_temp_free(EA); \
2830 }
2831 #define GEN_STX(name, stop, opc2, opc3, type) \
2832 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2833
2834 #define GEN_STS(name, stop, op, type) \
2835 GEN_ST(name, stop, op | 0x20, type); \
2836 GEN_STU(name, stop, op | 0x21, type); \
2837 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2838 GEN_STX(name, stop, 0x17, op | 0x00, type)
2839
2840 /* stb stbu stbux stbx */
2841 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2842 /* sth sthu sthux sthx */
2843 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2844 /* stw stwu stwux stwx */
2845 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2846 #if defined(TARGET_PPC64)
2847 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2848 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2849
2850 static void gen_std(DisasContext *ctx)
2851 {
2852 int rs;
2853 TCGv EA;
2854
2855 rs = rS(ctx->opcode);
2856 if ((ctx->opcode & 0x3) == 0x2) {
2857 #if defined(CONFIG_USER_ONLY)
2858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2859 #else
2860 /* stq */
2861 if (unlikely(ctx->mem_idx == 0)) {
2862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2863 return;
2864 }
2865 if (unlikely(rs & 1)) {
2866 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2867 return;
2868 }
2869 if (unlikely(ctx->le_mode)) {
2870 /* Little-endian mode is not handled */
2871 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2872 return;
2873 }
2874 gen_set_access_type(ctx, ACCESS_INT);
2875 EA = tcg_temp_new();
2876 gen_addr_imm_index(ctx, EA, 0x03);
2877 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2878 gen_addr_add(ctx, EA, EA, 8);
2879 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2880 tcg_temp_free(EA);
2881 #endif
2882 } else {
2883 /* std / stdu */
2884 if (Rc(ctx->opcode)) {
2885 if (unlikely(rA(ctx->opcode) == 0)) {
2886 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2887 return;
2888 }
2889 }
2890 gen_set_access_type(ctx, ACCESS_INT);
2891 EA = tcg_temp_new();
2892 gen_addr_imm_index(ctx, EA, 0x03);
2893 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2894 if (Rc(ctx->opcode))
2895 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2896 tcg_temp_free(EA);
2897 }
2898 }
2899 #endif
2900 /*** Integer load and store with byte reverse ***/
2901 /* lhbrx */
2902 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2903 {
2904 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2905 if (likely(!ctx->le_mode)) {
2906 tcg_gen_bswap16_tl(arg1, arg1);
2907 }
2908 }
2909 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2910
2911 /* lwbrx */
2912 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2913 {
2914 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2915 if (likely(!ctx->le_mode)) {
2916 tcg_gen_bswap32_tl(arg1, arg1);
2917 }
2918 }
2919 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2920
2921 #if defined(TARGET_PPC64)
2922 /* ldbrx */
2923 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2924 {
2925 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2926 if (likely(!ctx->le_mode)) {
2927 tcg_gen_bswap64_tl(arg1, arg1);
2928 }
2929 }
2930 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2931 #endif /* TARGET_PPC64 */
2932
2933 /* sthbrx */
2934 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2935 {
2936 if (likely(!ctx->le_mode)) {
2937 TCGv t0 = tcg_temp_new();
2938 tcg_gen_ext16u_tl(t0, arg1);
2939 tcg_gen_bswap16_tl(t0, t0);
2940 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2941 tcg_temp_free(t0);
2942 } else {
2943 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2944 }
2945 }
2946 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2947
2948 /* stwbrx */
2949 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2950 {
2951 if (likely(!ctx->le_mode)) {
2952 TCGv t0 = tcg_temp_new();
2953 tcg_gen_ext32u_tl(t0, arg1);
2954 tcg_gen_bswap32_tl(t0, t0);
2955 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2956 tcg_temp_free(t0);
2957 } else {
2958 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2959 }
2960 }
2961 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2962
2963 #if defined(TARGET_PPC64)
2964 /* stdbrx */
2965 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2966 {
2967 if (likely(!ctx->le_mode)) {
2968 TCGv t0 = tcg_temp_new();
2969 tcg_gen_bswap64_tl(t0, arg1);
2970 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2971 tcg_temp_free(t0);
2972 } else {
2973 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2974 }
2975 }
2976 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2977 #endif /* TARGET_PPC64 */
2978
2979 /*** Integer load and store multiple ***/
2980
2981 /* lmw */
2982 static void gen_lmw(DisasContext *ctx)
2983 {
2984 TCGv t0;
2985 TCGv_i32 t1;
2986 gen_set_access_type(ctx, ACCESS_INT);
2987 /* NIP cannot be restored if the memory exception comes from an helper */
2988 gen_update_nip(ctx, ctx->nip - 4);
2989 t0 = tcg_temp_new();
2990 t1 = tcg_const_i32(rD(ctx->opcode));
2991 gen_addr_imm_index(ctx, t0, 0);
2992 gen_helper_lmw(cpu_env, t0, t1);
2993 tcg_temp_free(t0);
2994 tcg_temp_free_i32(t1);
2995 }
2996
2997 /* stmw */
2998 static void gen_stmw(DisasContext *ctx)
2999 {
3000 TCGv t0;
3001 TCGv_i32 t1;
3002 gen_set_access_type(ctx, ACCESS_INT);
3003 /* NIP cannot be restored if the memory exception comes from an helper */
3004 gen_update_nip(ctx, ctx->nip - 4);
3005 t0 = tcg_temp_new();
3006 t1 = tcg_const_i32(rS(ctx->opcode));
3007 gen_addr_imm_index(ctx, t0, 0);
3008 gen_helper_stmw(cpu_env, t0, t1);
3009 tcg_temp_free(t0);
3010 tcg_temp_free_i32(t1);
3011 }
3012
3013 /*** Integer load and store strings ***/
3014
3015 /* lswi */
3016 /* PowerPC32 specification says we must generate an exception if
3017 * rA is in the range of registers to be loaded.
3018 * In an other hand, IBM says this is valid, but rA won't be loaded.
3019 * For now, I'll follow the spec...
3020 */
3021 static void gen_lswi(DisasContext *ctx)
3022 {
3023 TCGv t0;
3024 TCGv_i32 t1, t2;
3025 int nb = NB(ctx->opcode);
3026 int start = rD(ctx->opcode);
3027 int ra = rA(ctx->opcode);
3028 int nr;
3029
3030 if (nb == 0)
3031 nb = 32;
3032 nr = nb / 4;
3033 if (unlikely(((start + nr) > 32 &&
3034 start <= ra && (start + nr - 32) > ra) ||
3035 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3036 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3037 return;
3038 }
3039 gen_set_access_type(ctx, ACCESS_INT);
3040 /* NIP cannot be restored if the memory exception comes from an helper */
3041 gen_update_nip(ctx, ctx->nip - 4);
3042 t0 = tcg_temp_new();
3043 gen_addr_register(ctx, t0);
3044 t1 = tcg_const_i32(nb);
3045 t2 = tcg_const_i32(start);
3046 gen_helper_lsw(cpu_env, t0, t1, t2);
3047 tcg_temp_free(t0);
3048 tcg_temp_free_i32(t1);
3049 tcg_temp_free_i32(t2);
3050 }
3051
3052 /* lswx */
3053 static void gen_lswx(DisasContext *ctx)
3054 {
3055 TCGv t0;
3056 TCGv_i32 t1, t2, t3;
3057 gen_set_access_type(ctx, ACCESS_INT);
3058 /* NIP cannot be restored if the memory exception comes from an helper */
3059 gen_update_nip(ctx, ctx->nip - 4);
3060 t0 = tcg_temp_new();
3061 gen_addr_reg_index(ctx, t0);
3062 t1 = tcg_const_i32(rD(ctx->opcode));
3063 t2 = tcg_const_i32(rA(ctx->opcode));
3064 t3 = tcg_const_i32(rB(ctx->opcode));
3065 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3066 tcg_temp_free(t0);
3067 tcg_temp_free_i32(t1);
3068 tcg_temp_free_i32(t2);
3069 tcg_temp_free_i32(t3);
3070 }
3071
3072 /* stswi */
3073 static void gen_stswi(DisasContext *ctx)
3074 {
3075 TCGv t0;
3076 TCGv_i32 t1, t2;
3077 int nb = NB(ctx->opcode);
3078 gen_set_access_type(ctx, ACCESS_INT);
3079 /* NIP cannot be restored if the memory exception comes from an helper */
3080 gen_update_nip(ctx, ctx->nip - 4);
3081 t0 = tcg_temp_new();
3082 gen_addr_register(ctx, t0);
3083 if (nb == 0)
3084 nb = 32;
3085 t1 = tcg_const_i32(nb);
3086 t2 = tcg_const_i32(rS(ctx->opcode));
3087 gen_helper_stsw(cpu_env, t0, t1, t2);
3088 tcg_temp_free(t0);
3089 tcg_temp_free_i32(t1);
3090 tcg_temp_free_i32(t2);
3091 }
3092
3093 /* stswx */
3094 static void gen_stswx(DisasContext *ctx)
3095 {
3096 TCGv t0;
3097 TCGv_i32 t1, t2;
3098 gen_set_access_type(ctx, ACCESS_INT);
3099 /* NIP cannot be restored if the memory exception comes from an helper */
3100 gen_update_nip(ctx, ctx->nip - 4);
3101 t0 = tcg_temp_new();
3102 gen_addr_reg_index(ctx, t0);
3103 t1 = tcg_temp_new_i32();
3104 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3105 tcg_gen_andi_i32(t1, t1, 0x7F);
3106 t2 = tcg_const_i32(rS(ctx->opcode));
3107 gen_helper_stsw(cpu_env, t0, t1, t2);
3108 tcg_temp_free(t0);
3109 tcg_temp_free_i32(t1);
3110 tcg_temp_free_i32(t2);
3111 }
3112
3113 /*** Memory synchronisation ***/
3114 /* eieio */
3115 static void gen_eieio(DisasContext *ctx)
3116 {
3117 }
3118
3119 /* isync */
3120 static void gen_isync(DisasContext *ctx)
3121 {
3122 gen_stop_exception(ctx);
3123 }
3124
3125 /* lwarx */
3126 static void gen_lwarx(DisasContext *ctx)
3127 {
3128 TCGv t0;
3129 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3130 gen_set_access_type(ctx, ACCESS_RES);
3131 t0 = tcg_temp_local_new();
3132 gen_addr_reg_index(ctx, t0);
3133 gen_check_align(ctx, t0, 0x03);
3134 gen_qemu_ld32u(ctx, gpr, t0);
3135 tcg_gen_mov_tl(cpu_reserve, t0);
3136 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3137 tcg_temp_free(t0);
3138 }
3139
3140 #if defined(CONFIG_USER_ONLY)
3141 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3142 int reg, int size)
3143 {
3144 TCGv t0 = tcg_temp_new();
3145 uint32_t save_exception = ctx->exception;
3146
3147 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3148 tcg_gen_movi_tl(t0, (size << 5) | reg);
3149 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3150 tcg_temp_free(t0);
3151 gen_update_nip(ctx, ctx->nip-4);
3152 ctx->exception = POWERPC_EXCP_BRANCH;
3153 gen_exception(ctx, POWERPC_EXCP_STCX);
3154 ctx->exception = save_exception;
3155 }
3156 #endif
3157
3158 /* stwcx. */
3159 static void gen_stwcx_(DisasContext *ctx)
3160 {
3161 TCGv t0;
3162 gen_set_access_type(ctx, ACCESS_RES);
3163 t0 = tcg_temp_local_new();
3164 gen_addr_reg_index(ctx, t0);
3165 gen_check_align(ctx, t0, 0x03);
3166 #if defined(CONFIG_USER_ONLY)
3167 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3168 #else
3169 {
3170 int l1;
3171
3172 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3173 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3174 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3175 l1 = gen_new_label();
3176 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3177 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3178 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3179 gen_set_label(l1);
3180 tcg_gen_movi_tl(cpu_reserve, -1);
3181 }
3182 #endif
3183 tcg_temp_free(t0);
3184 }
3185
3186 #if defined(TARGET_PPC64)
3187 /* ldarx */
3188 static void gen_ldarx(DisasContext *ctx)
3189 {
3190 TCGv t0;
3191 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3192 gen_set_access_type(ctx, ACCESS_RES);
3193 t0 = tcg_temp_local_new();
3194 gen_addr_reg_index(ctx, t0);
3195 gen_check_align(ctx, t0, 0x07);
3196 gen_qemu_ld64(ctx, gpr, t0);
3197 tcg_gen_mov_tl(cpu_reserve, t0);
3198 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3199 tcg_temp_free(t0);
3200 }
3201
3202 /* stdcx. */
3203 static void gen_stdcx_(DisasContext *ctx)
3204 {
3205 TCGv t0;
3206 gen_set_access_type(ctx, ACCESS_RES);
3207 t0 = tcg_temp_local_new();
3208 gen_addr_reg_index(ctx, t0);
3209 gen_check_align(ctx, t0, 0x07);
3210 #if defined(CONFIG_USER_ONLY)
3211 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3212 #else
3213 {
3214 int l1;
3215 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3216 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3217 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3218 l1 = gen_new_label();
3219 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3220 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3221 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3222 gen_set_label(l1);
3223 tcg_gen_movi_tl(cpu_reserve, -1);
3224 }
3225 #endif
3226 tcg_temp_free(t0);
3227 }
3228 #endif /* defined(TARGET_PPC64) */
3229
3230 /* sync */
3231 static void gen_sync(DisasContext *ctx)
3232 {
3233 }
3234
3235 /* wait */
3236 static void gen_wait(DisasContext *ctx)
3237 {
3238 TCGv_i32 t0 = tcg_temp_new_i32();
3239 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3240 tcg_temp_free_i32(t0);
3241 /* Stop translation, as the CPU is supposed to sleep from now */
3242 gen_exception_err(ctx, EXCP_HLT, 1);
3243 }
3244
3245 /*** Floating-point load ***/
3246 #define GEN_LDF(name, ldop, opc, type) \
3247 static void glue(gen_, name)(DisasContext *ctx) \
3248 { \
3249 TCGv EA; \
3250 if (unlikely(!ctx->fpu_enabled)) { \
3251 gen_exception(ctx, POWERPC_EXCP_FPU); \
3252 return; \
3253 } \
3254 gen_set_access_type(ctx, ACCESS_FLOAT); \
3255 EA = tcg_temp_new(); \
3256 gen_addr_imm_index(ctx, EA, 0); \
3257 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3258 tcg_temp_free(EA); \
3259 }
3260
3261 #define GEN_LDUF(name, ldop, opc, type) \
3262 static void glue(gen_, name##u)(DisasContext *ctx) \
3263 { \
3264 TCGv EA; \
3265 if (unlikely(!ctx->fpu_enabled)) { \
3266 gen_exception(ctx, POWERPC_EXCP_FPU); \
3267 return; \
3268 } \
3269 if (unlikely(rA(ctx->opcode) == 0)) { \
3270 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3271 return; \
3272 } \
3273 gen_set_access_type(ctx, ACCESS_FLOAT); \
3274 EA = tcg_temp_new(); \
3275 gen_addr_imm_index(ctx, EA, 0); \
3276 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3277 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3278 tcg_temp_free(EA); \
3279 }
3280
3281 #define GEN_LDUXF(name, ldop, opc, type) \
3282 static void glue(gen_, name##ux)(DisasContext *ctx) \
3283 { \
3284 TCGv EA; \
3285 if (unlikely(!ctx->fpu_enabled)) { \
3286 gen_exception(ctx, POWERPC_EXCP_FPU); \
3287 return; \
3288 } \
3289 if (unlikely(rA(ctx->opcode) == 0)) { \
3290 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3291 return; \
3292 } \
3293 gen_set_access_type(ctx, ACCESS_FLOAT); \
3294 EA = tcg_temp_new(); \
3295 gen_addr_reg_index(ctx, EA); \
3296 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3297 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3298 tcg_temp_free(EA); \
3299 }
3300
3301 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3302 static void glue(gen_, name##x)(DisasContext *ctx) \
3303 { \
3304 TCGv EA; \
3305 if (unlikely(!ctx->fpu_enabled)) { \
3306 gen_exception(ctx, POWERPC_EXCP_FPU); \
3307 return; \
3308 } \
3309 gen_set_access_type(ctx, ACCESS_FLOAT); \
3310 EA = tcg_temp_new(); \
3311 gen_addr_reg_index(ctx, EA); \
3312 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3313 tcg_temp_free(EA); \
3314 }
3315
3316 #define GEN_LDFS(name, ldop, op, type) \
3317 GEN_LDF(name, ldop, op | 0x20, type); \
3318 GEN_LDUF(name, ldop, op | 0x21, type); \
3319 GEN_LDUXF(name, ldop, op | 0x01, type); \
3320 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3321
3322 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3323 {
3324 TCGv t0 = tcg_temp_new();
3325 TCGv_i32 t1 = tcg_temp_new_i32();
3326 gen_qemu_ld32u(ctx, t0, arg2);
3327 tcg_gen_trunc_tl_i32(t1, t0);
3328 tcg_temp_free(t0);
3329 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3330 tcg_temp_free_i32(t1);
3331 }
3332
3333 /* lfd lfdu lfdux lfdx */
3334 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3335 /* lfs lfsu lfsux lfsx */
3336 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3337
3338 /*** Floating-point store ***/
3339 #define GEN_STF(name, stop, opc, type) \
3340 static void glue(gen_, name)(DisasContext *ctx) \
3341 { \
3342 TCGv EA; \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3345 return; \
3346 } \
3347 gen_set_access_type(ctx, ACCESS_FLOAT); \
3348 EA = tcg_temp_new(); \
3349 gen_addr_imm_index(ctx, EA, 0); \
3350 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3351 tcg_temp_free(EA); \
3352 }
3353
3354 #define GEN_STUF(name, stop, opc, type) \
3355 static void glue(gen_, name##u)(DisasContext *ctx) \
3356 { \
3357 TCGv EA; \
3358 if (unlikely(!ctx->fpu_enabled)) { \
3359 gen_exception(ctx, POWERPC_EXCP_FPU); \
3360 return; \
3361 } \
3362 if (unlikely(rA(ctx->opcode) == 0)) { \
3363 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3364 return; \
3365 } \
3366 gen_set_access_type(ctx, ACCESS_FLOAT); \
3367 EA = tcg_temp_new(); \
3368 gen_addr_imm_index(ctx, EA, 0); \
3369 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3370 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3372 }
3373
3374 #define GEN_STUXF(name, stop, opc, type) \
3375 static void glue(gen_, name##ux)(DisasContext *ctx) \
3376 { \
3377 TCGv EA; \
3378 if (unlikely(!ctx->fpu_enabled)) { \
3379 gen_exception(ctx, POWERPC_EXCP_FPU); \
3380 return; \
3381 } \
3382 if (unlikely(rA(ctx->opcode) == 0)) { \
3383 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3384 return; \
3385 } \
3386 gen_set_access_type(ctx, ACCESS_FLOAT); \
3387 EA = tcg_temp_new(); \
3388 gen_addr_reg_index(ctx, EA); \
3389 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3390 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3391 tcg_temp_free(EA); \
3392 }
3393
3394 #define GEN_STXF(name, stop, opc2, opc3, type) \
3395 static void glue(gen_, name##x)(DisasContext *ctx) \
3396 { \
3397 TCGv EA; \
3398 if (unlikely(!ctx->fpu_enabled)) { \
3399 gen_exception(ctx, POWERPC_EXCP_FPU); \
3400 return; \
3401 } \
3402 gen_set_access_type(ctx, ACCESS_FLOAT); \
3403 EA = tcg_temp_new(); \
3404 gen_addr_reg_index(ctx, EA); \
3405 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3406 tcg_temp_free(EA); \
3407 }
3408
3409 #define GEN_STFS(name, stop, op, type) \
3410 GEN_STF(name, stop, op | 0x20, type); \
3411 GEN_STUF(name, stop, op | 0x21, type); \
3412 GEN_STUXF(name, stop, op | 0x01, type); \
3413 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3414
3415 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3416 {
3417 TCGv_i32 t0 = tcg_temp_new_i32();
3418 TCGv t1 = tcg_temp_new();
3419 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3420 tcg_gen_extu_i32_tl(t1, t0);
3421 tcg_temp_free_i32(t0);
3422 gen_qemu_st32(ctx, t1, arg2);
3423 tcg_temp_free(t1);
3424 }
3425
3426 /* stfd stfdu stfdux stfdx */
3427 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3428 /* stfs stfsu stfsux stfsx */
3429 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3430
3431 /* Optional: */
3432 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3433 {
3434 TCGv t0 = tcg_temp_new();
3435 tcg_gen_trunc_i64_tl(t0, arg1),
3436 gen_qemu_st32(ctx, t0, arg2);
3437 tcg_temp_free(t0);
3438 }
3439 /* stfiwx */
3440 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3441
3442 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3443 {
3444 #if defined(TARGET_PPC64)
3445 if (ctx->has_cfar)
3446 tcg_gen_movi_tl(cpu_cfar, nip);
3447 #endif
3448 }
3449
3450 /*** Branch ***/
3451 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3452 {
3453 TranslationBlock *tb;
3454 tb = ctx->tb;
3455 #if defined(TARGET_PPC64)
3456 if (!ctx->sf_mode)
3457 dest = (uint32_t) dest;
3458 #endif
3459 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3460 likely(!ctx->singlestep_enabled)) {
3461 tcg_gen_goto_tb(n);
3462 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3463 tcg_gen_exit_tb((tcg_target_long)tb + n);
3464 } else {
3465 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3466 if (unlikely(ctx->singlestep_enabled)) {
3467 if ((ctx->singlestep_enabled &
3468 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3469 ctx->exception == POWERPC_EXCP_BRANCH) {
3470 target_ulong tmp = ctx->nip;
3471 ctx->nip = dest;
3472 gen_exception(ctx, POWERPC_EXCP_TRACE);
3473 ctx->nip = tmp;
3474 }
3475 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3476 gen_debug_exception(ctx);
3477 }
3478 }
3479 tcg_gen_exit_tb(0);
3480 }
3481 }
3482
3483 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3484 {
3485 #if defined(TARGET_PPC64)
3486 if (ctx->sf_mode == 0)
3487 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3488 else
3489 #endif
3490 tcg_gen_movi_tl(cpu_lr, nip);
3491 }
3492
3493 /* b ba bl bla */
3494 static void gen_b(DisasContext *ctx)
3495 {
3496 target_ulong li, target;
3497
3498 ctx->exception = POWERPC_EXCP_BRANCH;
3499 /* sign extend LI */
3500 #if defined(TARGET_PPC64)
3501 if (ctx->sf_mode)
3502 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3503 else
3504 #endif
3505 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3506 if (likely(AA(ctx->opcode) == 0))
3507 target = ctx->nip + li - 4;
3508 else
3509 target = li;
3510 if (LK(ctx->opcode))
3511 gen_setlr(ctx, ctx->nip);
3512 gen_update_cfar(ctx, ctx->nip);
3513 gen_goto_tb(ctx, 0, target);
3514 }
3515
3516 #define BCOND_IM 0
3517 #define BCOND_LR 1
3518 #define BCOND_CTR 2
3519
3520 static inline void gen_bcond(DisasContext *ctx, int type)
3521 {
3522 uint32_t bo = BO(ctx->opcode);
3523 int l1;
3524 TCGv target;
3525
3526 ctx->exception = POWERPC_EXCP_BRANCH;
3527 if (type == BCOND_LR || type == BCOND_CTR) {
3528 target = tcg_temp_local_new();
3529 if (type == BCOND_CTR)
3530 tcg_gen_mov_tl(target, cpu_ctr);
3531 else
3532 tcg_gen_mov_tl(target, cpu_lr);
3533 } else {
3534 TCGV_UNUSED(target);
3535 }
3536 if (LK(ctx->opcode))
3537 gen_setlr(ctx, ctx->nip);
3538 l1 = gen_new_label();
3539 if ((bo & 0x4) == 0) {
3540 /* Decrement and test CTR */
3541 TCGv temp = tcg_temp_new();
3542 if (unlikely(type == BCOND_CTR)) {
3543 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3544 return;
3545 }
3546 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3547 #if defined(TARGET_PPC64)
3548 if (!ctx->sf_mode)
3549 tcg_gen_ext32u_tl(temp, cpu_ctr);
3550 else
3551 #endif
3552 tcg_gen_mov_tl(temp, cpu_ctr);
3553 if (bo & 0x2) {
3554 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3555 } else {
3556 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3557 }
3558 tcg_temp_free(temp);
3559 }
3560 if ((bo & 0x10) == 0) {
3561 /* Test CR */
3562 uint32_t bi = BI(ctx->opcode);
3563 uint32_t mask = 1 << (3 - (bi & 0x03));
3564 TCGv_i32 temp = tcg_temp_new_i32();
3565
3566 if (bo & 0x8) {
3567 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3568 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3569 } else {
3570 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3571 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3572 }
3573 tcg_temp_free_i32(temp);
3574 }
3575 gen_update_cfar(ctx, ctx->nip);
3576 if (type == BCOND_IM) {
3577 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3578 if (likely(AA(ctx->opcode) == 0)) {
3579 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3580 } else {
3581 gen_goto_tb(ctx, 0, li);
3582 }
3583 gen_set_label(l1);
3584 gen_goto_tb(ctx, 1, ctx->nip);
3585 } else {
3586 #if defined(TARGET_PPC64)
3587 if (!(ctx->sf_mode))
3588 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3589 else
3590 #endif
3591 tcg_gen_andi_tl(cpu_nip, target, ~3);
3592 tcg_gen_exit_tb(0);
3593 gen_set_label(l1);
3594 #if defined(TARGET_PPC64)
3595 if (!(ctx->sf_mode))
3596 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3597 else
3598 #endif
3599 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3600 tcg_gen_exit_tb(0);
3601 }
3602 }
3603
3604 static void gen_bc(DisasContext *ctx)
3605 {
3606 gen_bcond(ctx, BCOND_IM);
3607 }
3608
3609 static void gen_bcctr(DisasContext *ctx)
3610 {
3611 gen_bcond(ctx, BCOND_CTR);
3612 }
3613
3614 static void gen_bclr(DisasContext *ctx)
3615 {
3616 gen_bcond(ctx, BCOND_LR);
3617 }
3618
3619 /*** Condition register logical ***/
3620 #define GEN_CRLOGIC(name, tcg_op, opc) \
3621 static void glue(gen_, name)(DisasContext *ctx) \
3622 { \
3623 uint8_t bitmask; \
3624 int sh; \
3625 TCGv_i32 t0, t1; \
3626 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3627 t0 = tcg_temp_new_i32(); \
3628 if (sh > 0) \
3629 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3630 else if (sh < 0) \
3631 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3632 else \
3633 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3634 t1 = tcg_temp_new_i32(); \
3635 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3636 if (sh > 0) \
3637 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3638 else if (sh < 0) \
3639 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3640 else \
3641 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3642 tcg_op(t0, t0, t1); \
3643 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3644 tcg_gen_andi_i32(t0, t0, bitmask); \
3645 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3646 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3647 tcg_temp_free_i32(t0); \
3648 tcg_temp_free_i32(t1); \
3649 }
3650
3651 /* crand */
3652 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3653 /* crandc */
3654 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3655 /* creqv */
3656 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3657 /* crnand */
3658 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3659 /* crnor */
3660 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3661 /* cror */
3662 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3663 /* crorc */
3664 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3665 /* crxor */
3666 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3667
3668 /* mcrf */
3669 static void gen_mcrf(DisasContext *ctx)
3670 {
3671 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3672 }
3673
3674 /*** System linkage ***/
3675
3676 /* rfi (mem_idx only) */
3677 static void gen_rfi(DisasContext *ctx)
3678 {
3679 #if defined(CONFIG_USER_ONLY)
3680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3681 #else
3682 /* Restore CPU state */
3683 if (unlikely(!ctx->mem_idx)) {
3684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3685 return;
3686 }
3687 gen_update_cfar(ctx, ctx->nip);
3688 gen_helper_rfi(cpu_env);
3689 gen_sync_exception(ctx);
3690 #endif
3691 }
3692
3693 #if defined(TARGET_PPC64)
3694 static void gen_rfid(DisasContext *ctx)
3695 {
3696 #if defined(CONFIG_USER_ONLY)
3697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3698 #else
3699 /* Restore CPU state */
3700 if (unlikely(!ctx->mem_idx)) {
3701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3702 return;
3703 }
3704 gen_update_cfar(ctx, ctx->nip);
3705 gen_helper_rfid(cpu_env);
3706 gen_sync_exception(ctx);
3707 #endif
3708 }
3709
3710 static void gen_hrfid(DisasContext *ctx)
3711 {
3712 #if defined(CONFIG_USER_ONLY)
3713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3714 #else
3715 /* Restore CPU state */
3716 if (unlikely(ctx->mem_idx <= 1)) {
3717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3718 return;
3719 }
3720 gen_helper_hrfid(cpu_env);
3721 gen_sync_exception(ctx);
3722 #endif
3723 }
3724 #endif
3725
3726 /* sc */
3727 #if defined(CONFIG_USER_ONLY)
3728 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3729 #else
3730 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3731 #endif
3732 static void gen_sc(DisasContext *ctx)
3733 {
3734 uint32_t lev;
3735
3736 lev = (ctx->opcode >> 5) & 0x7F;
3737 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3738 }
3739
3740 /*** Trap ***/
3741
3742 /* tw */
3743 static void gen_tw(DisasContext *ctx)
3744 {
3745 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3746 /* Update the nip since this might generate a trap exception */
3747 gen_update_nip(ctx, ctx->nip);
3748 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3749 t0);
3750 tcg_temp_free_i32(t0);
3751 }
3752
3753 /* twi */
3754 static void gen_twi(DisasContext *ctx)
3755 {
3756 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3757 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3758 /* Update the nip since this might generate a trap exception */
3759 gen_update_nip(ctx, ctx->nip);
3760 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3761 tcg_temp_free(t0);
3762 tcg_temp_free_i32(t1);
3763 }
3764
3765 #if defined(TARGET_PPC64)
3766 /* td */
3767 static void gen_td(DisasContext *ctx)
3768 {
3769 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3770 /* Update the nip since this might generate a trap exception */
3771 gen_update_nip(ctx, ctx->nip);
3772 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3773 t0);
3774 tcg_temp_free_i32(t0);
3775 }
3776
3777 /* tdi */
3778 static void gen_tdi(DisasContext *ctx)
3779 {
3780 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3781 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3782 /* Update the nip since this might generate a trap exception */
3783 gen_update_nip(ctx, ctx->nip);
3784 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3785 tcg_temp_free(t0);
3786 tcg_temp_free_i32(t1);
3787 }
3788 #endif
3789
3790 /*** Processor control ***/
3791
3792 /* mcrxr */
3793 static void gen_mcrxr(DisasContext *ctx)
3794 {
3795 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3796 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3797 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3798 }
3799
3800 /* mfcr mfocrf */
3801 static void gen_mfcr(DisasContext *ctx)
3802 {
3803 uint32_t crm, crn;
3804
3805 if (likely(ctx->opcode & 0x00100000)) {
3806 crm = CRM(ctx->opcode);
3807 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3808 crn = ctz32 (crm);
3809 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3810 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3811 cpu_gpr[rD(ctx->opcode)], crn * 4);
3812 }
3813 } else {
3814 TCGv_i32 t0 = tcg_temp_new_i32();
3815 tcg_gen_mov_i32(t0, cpu_crf[0]);
3816 tcg_gen_shli_i32(t0, t0, 4);
3817 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3818 tcg_gen_shli_i32(t0, t0, 4);
3819 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3820 tcg_gen_shli_i32(t0, t0, 4);
3821 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3822 tcg_gen_shli_i32(t0, t0, 4);
3823 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3824 tcg_gen_shli_i32(t0, t0, 4);
3825 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3826 tcg_gen_shli_i32(t0, t0, 4);
3827 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3828 tcg_gen_shli_i32(t0, t0, 4);
3829 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3830 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3831 tcg_temp_free_i32(t0);
3832 }
3833 }
3834
3835 /* mfmsr */
3836 static void gen_mfmsr(DisasContext *ctx)
3837 {
3838 #if defined(CONFIG_USER_ONLY)
3839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3840 #else
3841 if (unlikely(!ctx->mem_idx)) {
3842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3843 return;
3844 }
3845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3846 #endif
3847 }
3848
3849 static void spr_noaccess(void *opaque, int gprn, int sprn)
3850 {
3851 #if 0
3852 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3853 printf("ERROR: try to access SPR %d !\n", sprn);
3854 #endif
3855 }
3856 #define SPR_NOACCESS (&spr_noaccess)
3857
3858 /* mfspr */
3859 static inline void gen_op_mfspr(DisasContext *ctx)
3860 {
3861 void (*read_cb)(void *opaque, int gprn, int sprn);
3862 uint32_t sprn = SPR(ctx->opcode);
3863
3864 #if !defined(CONFIG_USER_ONLY)
3865 if (ctx->mem_idx == 2)
3866 read_cb = ctx->spr_cb[sprn].hea_read;
3867 else if (ctx->mem_idx)
3868 read_cb = ctx->spr_cb[sprn].oea_read;
3869 else
3870 #endif
3871 read_cb = ctx->spr_cb[sprn].uea_read;
3872 if (likely(read_cb != NULL)) {
3873 if (likely(read_cb != SPR_NOACCESS)) {
3874 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3875 } else {
3876 /* Privilege exception */
3877 /* This is a hack to avoid warnings when running Linux:
3878 * this OS breaks the PowerPC virtualisation model,
3879 * allowing userland application to read the PVR
3880 */
3881 if (sprn != SPR_PVR) {
3882 qemu_log("Trying to read privileged spr %d %03x at "
3883 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3884 printf("Trying to read privileged spr %d %03x at "
3885 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3886 }
3887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3888 }
3889 } else {
3890 /* Not defined */
3891 qemu_log("Trying to read invalid spr %d %03x at "
3892 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3893 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3894 sprn, sprn, ctx->nip);
3895 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3896 }
3897 }
3898
3899 static void gen_mfspr(DisasContext *ctx)
3900 {
3901 gen_op_mfspr(ctx);
3902 }
3903
3904 /* mftb */
3905 static void gen_mftb(DisasContext *ctx)
3906 {
3907 gen_op_mfspr(ctx);
3908 }
3909
3910 /* mtcrf mtocrf*/
3911 static void gen_mtcrf(DisasContext *ctx)
3912 {
3913 uint32_t crm, crn;
3914
3915 crm = CRM(ctx->opcode);
3916 if (likely((ctx->opcode & 0x00100000))) {
3917 if (crm && ((crm & (crm - 1)) == 0)) {
3918 TCGv_i32 temp = tcg_temp_new_i32();
3919 crn = ctz32 (crm);
3920 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3921 tcg_gen_shri_i32(temp, temp, crn * 4);
3922 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3923 tcg_temp_free_i32(temp);
3924 }
3925 } else {
3926 TCGv_i32 temp = tcg_temp_new_i32();
3927 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3928 for (crn = 0 ; crn < 8 ; crn++) {
3929 if (crm & (1 << crn)) {
3930 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3931 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3932 }
3933 }
3934 tcg_temp_free_i32(temp);
3935 }
3936 }
3937
3938 /* mtmsr */
3939 #if defined(TARGET_PPC64)
3940 static void gen_mtmsrd(DisasContext *ctx)
3941 {
3942 #if defined(CONFIG_USER_ONLY)
3943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3944 #else
3945 if (unlikely(!ctx->mem_idx)) {
3946 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3947 return;
3948 }
3949 if (ctx->opcode & 0x00010000) {
3950 /* Special form that does not need any synchronisation */
3951 TCGv t0 = tcg_temp_new();
3952 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3953 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3954 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3955 tcg_temp_free(t0);
3956 } else {
3957 /* XXX: we need to update nip before the store
3958 * if we enter power saving mode, we will exit the loop
3959 * directly from ppc_store_msr
3960 */
3961 gen_update_nip(ctx, ctx->nip);
3962 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3963 /* Must stop the translation as machine state (may have) changed */
3964 /* Note that mtmsr is not always defined as context-synchronizing */
3965 gen_stop_exception(ctx);
3966 }
3967 #endif
3968 }
3969 #endif
3970
3971 static void gen_mtmsr(DisasContext *ctx)
3972 {
3973 #if defined(CONFIG_USER_ONLY)
3974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3975 #else
3976 if (unlikely(!ctx->mem_idx)) {
3977 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3978 return;
3979 }
3980 if (ctx->opcode & 0x00010000) {
3981 /* Special form that does not need any synchronisation */
3982 TCGv t0 = tcg_temp_new();
3983 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3984 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3985 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3986 tcg_temp_free(t0);
3987 } else {
3988 TCGv msr = tcg_temp_new();
3989
3990 /* XXX: we need to update nip before the store
3991 * if we enter power saving mode, we will exit the loop
3992 * directly from ppc_store_msr
3993 */
3994 gen_update_nip(ctx, ctx->nip);
3995 #if defined(TARGET_PPC64)
3996 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3997 #else
3998 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3999 #endif
4000 gen_helper_store_msr(cpu_env, msr);
4001 /* Must stop the translation as machine state (may have) changed */
4002 /* Note that mtmsr is not always defined as context-synchronizing */
4003 gen_stop_exception(ctx);
4004 }
4005 #endif
4006 }
4007
4008 /* mtspr */
4009 static void gen_mtspr(DisasContext *ctx)
4010 {
4011 void (*write_cb)(void *opaque, int sprn, int gprn);
4012 uint32_t sprn = SPR(ctx->opcode);
4013
4014 #if !defined(CONFIG_USER_ONLY)
4015 if (ctx->mem_idx == 2)
4016 write_cb = ctx->spr_cb[sprn].hea_write;
4017 else if (ctx->mem_idx)
4018 write_cb = ctx->spr_cb[sprn].oea_write;
4019 else
4020 #endif
4021 write_cb = ctx->spr_cb[sprn].uea_write;
4022 if (likely(write_cb != NULL)) {
4023 if (likely(write_cb != SPR_NOACCESS)) {
4024 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4025 } else {
4026 /* Privilege exception */
4027 qemu_log("Trying to write privileged spr %d %03x at "
4028 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4029 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4030 "\n", sprn, sprn, ctx->nip);
4031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4032 }
4033 } else {
4034 /* Not defined */
4035 qemu_log("Trying to write invalid spr %d %03x at "
4036 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4037 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4038 sprn, sprn, ctx->nip);
4039 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4040 }
4041 }
4042
4043 /*** Cache management ***/
4044
4045 /* dcbf */
4046 static void gen_dcbf(DisasContext *ctx)
4047 {
4048 /* XXX: specification says this is treated as a load by the MMU */
4049 TCGv t0;
4050 gen_set_access_type(ctx, ACCESS_CACHE);
4051 t0 = tcg_temp_new();
4052 gen_addr_reg_index(ctx, t0);
4053 gen_qemu_ld8u(ctx, t0, t0);
4054 tcg_temp_free(t0);
4055 }
4056
4057 /* dcbi (Supervisor only) */
4058 static void gen_dcbi(DisasContext *ctx)
4059 {
4060 #if defined(CONFIG_USER_ONLY)
4061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4062 #else
4063 TCGv EA, val;
4064 if (unlikely(!ctx->mem_idx)) {
4065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4066 return;
4067 }
4068 EA = tcg_temp_new();
4069 gen_set_access_type(ctx, ACCESS_CACHE);
4070 gen_addr_reg_index(ctx, EA);
4071 val = tcg_temp_new();
4072 /* XXX: specification says this should be treated as a store by the MMU */
4073 gen_qemu_ld8u(ctx, val, EA);
4074 gen_qemu_st8(ctx, val, EA);
4075 tcg_temp_free(val);
4076 tcg_temp_free(EA);
4077 #endif
4078 }
4079
4080 /* dcdst */
4081 static void gen_dcbst(DisasContext *ctx)
4082 {
4083 /* XXX: specification say this is treated as a load by the MMU */
4084 TCGv t0;
4085 gen_set_access_type(ctx, ACCESS_CACHE);
4086 t0 = tcg_temp_new();
4087 gen_addr_reg_index(ctx, t0);
4088 gen_qemu_ld8u(ctx, t0, t0);
4089 tcg_temp_free(t0);
4090 }
4091
4092 /* dcbt */
4093 static void gen_dcbt(DisasContext *ctx)
4094 {
4095 /* interpreted as no-op */
4096 /* XXX: specification say this is treated as a load by the MMU
4097 * but does not generate any exception
4098 */
4099 }
4100
4101 /* dcbtst */
4102 static void gen_dcbtst(DisasContext *ctx)
4103 {
4104 /* interpreted as no-op */
4105 /* XXX: specification say this is treated as a load by the MMU
4106 * but does not generate any exception
4107 */
4108 }
4109
4110 /* dcbz */
4111 static void gen_dcbz(DisasContext *ctx)
4112 {
4113 TCGv t0;
4114 gen_set_access_type(ctx, ACCESS_CACHE);
4115 /* NIP cannot be restored if the memory exception comes from an helper */
4116 gen_update_nip(ctx, ctx->nip - 4);
4117 t0 = tcg_temp_new();
4118 gen_addr_reg_index(ctx, t0);
4119 gen_helper_dcbz(cpu_env, t0);
4120 tcg_temp_free(t0);
4121 }
4122
4123 static void gen_dcbz_970(DisasContext *ctx)
4124 {
4125 TCGv t0;
4126 gen_set_access_type(ctx, ACCESS_CACHE);
4127 /* NIP cannot be restored if the memory exception comes from an helper */
4128 gen_update_nip(ctx, ctx->nip - 4);
4129 t0 = tcg_temp_new();
4130 gen_addr_reg_index(ctx, t0);
4131 if (ctx->opcode & 0x00200000)
4132 gen_helper_dcbz(cpu_env, t0);
4133 else
4134 gen_helper_dcbz_970(cpu_env, t0);
4135 tcg_temp_free(t0);
4136 }
4137
4138 /* dst / dstt */
4139 static void gen_dst(DisasContext *ctx)
4140 {
4141 if (rA(ctx->opcode) == 0) {
4142 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4143 } else {
4144 /* interpreted as no-op */
4145 }
4146 }
4147
4148 /* dstst /dststt */
4149 static void gen_dstst(DisasContext *ctx)
4150 {
4151 if (rA(ctx->opcode) == 0) {
4152 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4153 } else {
4154 /* interpreted as no-op */
4155 }
4156
4157 }
4158
4159 /* dss / dssall */
4160 static void gen_dss(DisasContext *ctx)
4161 {
4162 /* interpreted as no-op */
4163 }
4164
4165 /* icbi */
4166 static void gen_icbi(DisasContext *ctx)
4167 {
4168 TCGv t0;
4169 gen_set_access_type(ctx, ACCESS_CACHE);
4170 /* NIP cannot be restored if the memory exception comes from an helper */
4171 gen_update_nip(ctx, ctx->nip - 4);
4172 t0 = tcg_temp_new();
4173 gen_addr_reg_index(ctx, t0);
4174 gen_helper_icbi(cpu_env, t0);
4175 tcg_temp_free(t0);
4176 }
4177
4178 /* Optional: */
4179 /* dcba */
4180 static void gen_dcba(DisasContext *ctx)
4181 {
4182 /* interpreted as no-op */
4183 /* XXX: specification say this is treated as a store by the MMU
4184 * but does not generate any exception
4185 */
4186 }
4187
4188 /*** Segment register manipulation ***/
4189 /* Supervisor only: */
4190
4191 /* mfsr */
4192 static void gen_mfsr(DisasContext *ctx)
4193 {
4194 #if defined(CONFIG_USER_ONLY)
4195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4196 #else
4197 TCGv t0;
4198 if (unlikely(!ctx->mem_idx)) {
4199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4200 return;
4201 }
4202 t0 = tcg_const_tl(SR(ctx->opcode));
4203 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4204 tcg_temp_free(t0);
4205 #endif
4206 }
4207
4208 /* mfsrin */
4209 static void gen_mfsrin(DisasContext *ctx)
4210 {
4211 #if defined(CONFIG_USER_ONLY)
4212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4213 #else
4214 TCGv t0;
4215 if (unlikely(!ctx->mem_idx)) {
4216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4217 return;
4218 }
4219 t0 = tcg_temp_new();
4220 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4221 tcg_gen_andi_tl(t0, t0, 0xF);
4222 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4223 tcg_temp_free(t0);
4224 #endif
4225 }
4226
4227 /* mtsr */
4228 static void gen_mtsr(DisasContext *ctx)
4229 {
4230 #if defined(CONFIG_USER_ONLY)
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232 #else
4233 TCGv t0;
4234 if (unlikely(!ctx->mem_idx)) {
4235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4236 return;
4237 }
4238 t0 = tcg_const_tl(SR(ctx->opcode));
4239 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4240 tcg_temp_free(t0);
4241 #endif
4242 }
4243
4244 /* mtsrin */
4245 static void gen_mtsrin(DisasContext *ctx)
4246 {
4247 #if defined(CONFIG_USER_ONLY)
4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4249 #else
4250 TCGv t0;
4251 if (unlikely(!ctx->mem_idx)) {
4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4253 return;
4254 }
4255 t0 = tcg_temp_new();
4256 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4257 tcg_gen_andi_tl(t0, t0, 0xF);
4258 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4259 tcg_temp_free(t0);
4260 #endif
4261 }
4262
4263 #if defined(TARGET_PPC64)
4264 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4265
4266 /* mfsr */
4267 static void gen_mfsr_64b(DisasContext *ctx)
4268 {
4269 #if defined(CONFIG_USER_ONLY)
4270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4271 #else
4272 TCGv t0;
4273 if (unlikely(!ctx->mem_idx)) {
4274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4275 return;
4276 }
4277 t0 = tcg_const_tl(SR(ctx->opcode));
4278 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4279 tcg_temp_free(t0);
4280 #endif
4281 }
4282
4283 /* mfsrin */
4284 static void gen_mfsrin_64b(DisasContext *ctx)
4285 {
4286 #if defined(CONFIG_USER_ONLY)
4287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4288 #else
4289 TCGv t0;
4290 if (unlikely(!ctx->mem_idx)) {
4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4292 return;
4293 }
4294 t0 = tcg_temp_new();
4295 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4296 tcg_gen_andi_tl(t0, t0, 0xF);
4297 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4298 tcg_temp_free(t0);
4299 #endif
4300 }
4301
4302 /* mtsr */
4303 static void gen_mtsr_64b(DisasContext *ctx)
4304 {
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4307 #else
4308 TCGv t0;
4309 if (unlikely(!ctx->mem_idx)) {
4310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4311 return;
4312 }
4313 t0 = tcg_const_tl(SR(ctx->opcode));
4314 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4315 tcg_temp_free(t0);
4316 #endif
4317 }
4318
4319 /* mtsrin */
4320 static void gen_mtsrin_64b(DisasContext *ctx)
4321 {
4322 #if defined(CONFIG_USER_ONLY)
4323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4324 #else
4325 TCGv t0;
4326 if (unlikely(!ctx->mem_idx)) {
4327 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4328 return;
4329 }
4330 t0 = tcg_temp_new();
4331 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4332 tcg_gen_andi_tl(t0, t0, 0xF);
4333 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4334 tcg_temp_free(t0);
4335 #endif
4336 }
4337
4338 /* slbmte */
4339 static void gen_slbmte(DisasContext *ctx)
4340 {
4341 #if defined(CONFIG_USER_ONLY)
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4343 #else
4344 if (unlikely(!ctx->mem_idx)) {
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4346 return;
4347 }
4348 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4349 cpu_gpr[rS(ctx->opcode)]);
4350 #endif
4351 }
4352
4353 static void gen_slbmfee(DisasContext *ctx)
4354 {
4355 #if defined(CONFIG_USER_ONLY)
4356 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4357 #else
4358 if (unlikely(!ctx->mem_idx)) {
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4360 return;
4361 }
4362 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4363 cpu_gpr[rB(ctx->opcode)]);
4364 #endif
4365 }
4366
4367 static void gen_slbmfev(DisasContext *ctx)
4368 {
4369 #if defined(CONFIG_USER_ONLY)
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4371 #else
4372 if (unlikely(!ctx->mem_idx)) {
4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4374 return;
4375 }
4376 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4377 cpu_gpr[rB(ctx->opcode)]);
4378 #endif
4379 }
4380 #endif /* defined(TARGET_PPC64) */
4381
4382 /*** Lookaside buffer management ***/
4383 /* Optional & mem_idx only: */
4384
4385 /* tlbia */
4386 static void gen_tlbia(DisasContext *ctx)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4390 #else
4391 if (unlikely(!ctx->mem_idx)) {
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4393 return;
4394 }
4395 gen_helper_tlbia(cpu_env);
4396 #endif
4397 }
4398
4399 /* tlbiel */
4400 static void gen_tlbiel(DisasContext *ctx)
4401 {
4402 #if defined(CONFIG_USER_ONLY)
4403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4404 #else
4405 if (unlikely(!ctx->mem_idx)) {
4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4407 return;
4408 }
4409 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4410 #endif
4411 }
4412
4413 /* tlbie */
4414 static void gen_tlbie(DisasContext *ctx)
4415 {
4416 #if defined(CONFIG_USER_ONLY)
4417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4418 #else
4419 if (unlikely(!ctx->mem_idx)) {
4420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4421 return;
4422 }
4423 #if defined(TARGET_PPC64)
4424 if (!ctx->sf_mode) {
4425 TCGv t0 = tcg_temp_new();
4426 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4427 gen_helper_tlbie(cpu_env, t0);
4428 tcg_temp_free(t0);
4429 } else
4430 #endif
4431 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4432 #endif
4433 }
4434
4435 /* tlbsync */
4436 static void gen_tlbsync(DisasContext *ctx)
4437 {
4438 #if defined(CONFIG_USER_ONLY)
4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4440 #else
4441 if (unlikely(!ctx->mem_idx)) {
4442 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4443 return;
4444 }
4445 /* This has no effect: it should ensure that all previous
4446 * tlbie have completed
4447 */
4448 gen_stop_exception(ctx);
4449 #endif
4450 }
4451
4452 #if defined(TARGET_PPC64)
4453 /* slbia */
4454 static void gen_slbia(DisasContext *ctx)
4455 {
4456 #if defined(CONFIG_USER_ONLY)
4457 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4458 #else
4459 if (unlikely(!ctx->mem_idx)) {
4460 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4461 return;
4462 }
4463 gen_helper_slbia(cpu_env);
4464 #endif
4465 }
4466
4467 /* slbie */
4468 static void gen_slbie(DisasContext *ctx)
4469 {
4470 #if defined(CONFIG_USER_ONLY)
4471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4472 #else
4473 if (unlikely(!ctx->mem_idx)) {
4474 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4475 return;
4476 }
4477 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4478 #endif
4479 }
4480 #endif
4481
4482 /*** External control ***/
4483 /* Optional: */
4484
4485 /* eciwx */
4486 static void gen_eciwx(DisasContext *ctx)
4487 {
4488 TCGv t0;
4489 /* Should check EAR[E] ! */
4490 gen_set_access_type(ctx, ACCESS_EXT);
4491 t0 = tcg_temp_new();
4492 gen_addr_reg_index(ctx, t0);
4493 gen_check_align(ctx, t0, 0x03);
4494 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4495 tcg_temp_free(t0);
4496 }
4497
4498 /* ecowx */
4499 static void gen_ecowx(DisasContext *ctx)
4500 {
4501 TCGv t0;
4502 /* Should check EAR[E] ! */
4503 gen_set_access_type(ctx, ACCESS_EXT);
4504 t0 = tcg_temp_new();
4505 gen_addr_reg_index(ctx, t0);
4506 gen_check_align(ctx, t0, 0x03);
4507 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4508 tcg_temp_free(t0);
4509 }
4510
4511 /* PowerPC 601 specific instructions */
4512
4513 /* abs - abs. */
4514 static void gen_abs(DisasContext *ctx)
4515 {
4516 int l1 = gen_new_label();
4517 int l2 = gen_new_label();
4518 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4519 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4520 tcg_gen_br(l2);
4521 gen_set_label(l1);
4522 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4523 gen_set_label(l2);
4524 if (unlikely(Rc(ctx->opcode) != 0))
4525 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4526 }
4527
4528 /* abso - abso. */
4529 static void gen_abso(DisasContext *ctx)
4530 {
4531 int l1 = gen_new_label();
4532 int l2 = gen_new_label();
4533 int l3 = gen_new_label();
4534 /* Start with XER OV disabled, the most likely case */
4535 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4536 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4537 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4538 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4539 tcg_gen_br(l2);
4540 gen_set_label(l1);
4541 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4542 tcg_gen_br(l3);
4543 gen_set_label(l2);
4544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4545 gen_set_label(l3);
4546 if (unlikely(Rc(ctx->opcode) != 0))
4547 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4548 }
4549
4550 /* clcs */
4551 static void gen_clcs(DisasContext *ctx)
4552 {
4553 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4554 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4555 tcg_temp_free_i32(t0);
4556 /* Rc=1 sets CR0 to an undefined state */
4557 }
4558
4559 /* div - div. */
4560 static void gen_div(DisasContext *ctx)
4561 {
4562 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4563 cpu_gpr[rB(ctx->opcode)]);
4564 if (unlikely(Rc(ctx->opcode) != 0))
4565 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4566 }
4567
4568 /* divo - divo. */
4569 static void gen_divo(DisasContext *ctx)
4570 {
4571 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4572 cpu_gpr[rB(ctx->opcode)]);
4573 if (unlikely(Rc(ctx->opcode) != 0))
4574 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4575 }
4576
4577 /* divs - divs. */
4578 static void gen_divs(DisasContext *ctx)
4579 {
4580 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4581 cpu_gpr[rB(ctx->opcode)]);
4582 if (unlikely(Rc(ctx->opcode) != 0))
4583 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4584 }
4585
4586 /* divso - divso. */
4587 static void gen_divso(DisasContext *ctx)
4588 {
4589 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4590 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4591 if (unlikely(Rc(ctx->opcode) != 0))
4592 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4593 }
4594
4595 /* doz - doz. */
4596 static void gen_doz(DisasContext *ctx)
4597 {
4598 int l1 = gen_new_label();
4599 int l2 = gen_new_label();
4600 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4601 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4602 tcg_gen_br(l2);
4603 gen_set_label(l1);
4604 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4605 gen_set_label(l2);
4606 if (unlikely(Rc(ctx->opcode) != 0))
4607 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4608 }
4609
4610 /* dozo - dozo. */
4611 static void gen_dozo(DisasContext *ctx)
4612 {
4613 int l1 = gen_new_label();
4614 int l2 = gen_new_label();
4615 TCGv t0 = tcg_temp_new();
4616 TCGv t1 = tcg_temp_new();
4617 TCGv t2 = tcg_temp_new();
4618 /* Start with XER OV disabled, the most likely case */
4619 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4620 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4621 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4622 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4623 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4624 tcg_gen_andc_tl(t1, t1, t2);
4625 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4626 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4627 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4628 tcg_gen_br(l2);
4629 gen_set_label(l1);
4630 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4631 gen_set_label(l2);
4632 tcg_temp_free(t0);
4633 tcg_temp_free(t1);
4634 tcg_temp_free(t2);
4635 if (unlikely(Rc(ctx->opcode) != 0))
4636 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4637 }
4638
4639 /* dozi */
4640 static void gen_dozi(DisasContext *ctx)
4641 {
4642 target_long simm = SIMM(ctx->opcode);
4643 int l1 = gen_new_label();
4644 int l2 = gen_new_label();
4645 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4646 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4647 tcg_gen_br(l2);
4648 gen_set_label(l1);
4649 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4650 gen_set_label(l2);
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4653 }
4654
4655 /* lscbx - lscbx. */
4656 static void gen_lscbx(DisasContext *ctx)
4657 {
4658 TCGv t0 = tcg_temp_new();
4659 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4660 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4661 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4662
4663 gen_addr_reg_index(ctx, t0);
4664 /* NIP cannot be restored if the memory exception comes from an helper */
4665 gen_update_nip(ctx, ctx->nip - 4);
4666 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4667 tcg_temp_free_i32(t1);
4668 tcg_temp_free_i32(t2);
4669 tcg_temp_free_i32(t3);
4670 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4671 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4672 if (unlikely(Rc(ctx->opcode) != 0))
4673 gen_set_Rc0(ctx, t0);
4674 tcg_temp_free(t0);
4675 }
4676
4677 /* maskg - maskg. */
4678 static void gen_maskg(DisasContext *ctx)
4679 {
4680 int l1 = gen_new_label();
4681 TCGv t0 = tcg_temp_new();
4682 TCGv t1 = tcg_temp_new();
4683 TCGv t2 = tcg_temp_new();
4684 TCGv t3 = tcg_temp_new();
4685 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4686 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4687 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4688 tcg_gen_addi_tl(t2, t0, 1);
4689 tcg_gen_shr_tl(t2, t3, t2);
4690 tcg_gen_shr_tl(t3, t3, t1);
4691 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4692 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4693 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4694 gen_set_label(l1);
4695 tcg_temp_free(t0);
4696 tcg_temp_free(t1);
4697 tcg_temp_free(t2);
4698 tcg_temp_free(t3);
4699 if (unlikely(Rc(ctx->opcode) != 0))
4700 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4701 }
4702
4703 /* maskir - maskir. */
4704 static void gen_maskir(DisasContext *ctx)
4705 {
4706 TCGv t0 = tcg_temp_new();
4707 TCGv t1 = tcg_temp_new();
4708 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4709 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4710 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4711 tcg_temp_free(t0);
4712 tcg_temp_free(t1);
4713 if (unlikely(Rc(ctx->opcode) != 0))
4714 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4715 }
4716
4717 /* mul - mul. */
4718 static void gen_mul(DisasContext *ctx)
4719 {
4720 TCGv_i64 t0 = tcg_temp_new_i64();
4721 TCGv_i64 t1 = tcg_temp_new_i64();
4722 TCGv t2 = tcg_temp_new();
4723 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4724 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4725 tcg_gen_mul_i64(t0, t0, t1);
4726 tcg_gen_trunc_i64_tl(t2, t0);
4727 gen_store_spr(SPR_MQ, t2);
4728 tcg_gen_shri_i64(t1, t0, 32);
4729 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4730 tcg_temp_free_i64(t0);
4731 tcg_temp_free_i64(t1);
4732 tcg_temp_free(t2);
4733 if (unlikely(Rc(ctx->opcode) != 0))
4734 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4735 }
4736
4737 /* mulo - mulo. */
4738 static void gen_mulo(DisasContext *ctx)
4739 {
4740 int l1 = gen_new_label();
4741 TCGv_i64 t0 = tcg_temp_new_i64();
4742 TCGv_i64 t1 = tcg_temp_new_i64();
4743 TCGv t2 = tcg_temp_new();
4744 /* Start with XER OV disabled, the most likely case */
4745 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4746 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4747 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4748 tcg_gen_mul_i64(t0, t0, t1);
4749 tcg_gen_trunc_i64_tl(t2, t0);
4750 gen_store_spr(SPR_MQ, t2);
4751 tcg_gen_shri_i64(t1, t0, 32);
4752 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4753 tcg_gen_ext32s_i64(t1, t0);
4754 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4755 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4756 gen_set_label(l1);
4757 tcg_temp_free_i64(t0);
4758 tcg_temp_free_i64(t1);
4759 tcg_temp_free(t2);
4760 if (unlikely(Rc(ctx->opcode) != 0))
4761 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4762 }
4763
4764 /* nabs - nabs. */
4765 static void gen_nabs(DisasContext *ctx)
4766 {
4767 int l1 = gen_new_label();
4768 int l2 = gen_new_label();
4769 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4770 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4771 tcg_gen_br(l2);
4772 gen_set_label(l1);
4773 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4774 gen_set_label(l2);
4775 if (unlikely(Rc(ctx->opcode) != 0))
4776 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4777 }
4778
4779 /* nabso - nabso. */
4780 static void gen_nabso(DisasContext *ctx)
4781 {
4782 int l1 = gen_new_label();
4783 int l2 = gen_new_label();
4784 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4786 tcg_gen_br(l2);
4787 gen_set_label(l1);
4788 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4789 gen_set_label(l2);
4790 /* nabs never overflows */
4791 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4792 if (unlikely(Rc(ctx->opcode) != 0))
4793 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4794 }
4795
4796 /* rlmi - rlmi. */
4797 static void gen_rlmi(DisasContext *ctx)
4798 {
4799 uint32_t mb = MB(ctx->opcode);
4800 uint32_t me = ME(ctx->opcode);
4801 TCGv t0 = tcg_temp_new();
4802 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4803 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4804 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4805 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4806 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4807 tcg_temp_free(t0);
4808 if (unlikely(Rc(ctx->opcode) != 0))
4809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4810 }
4811
4812 /* rrib - rrib. */
4813 static void gen_rrib(DisasContext *ctx)
4814 {
4815 TCGv t0 = tcg_temp_new();
4816 TCGv t1 = tcg_temp_new();
4817 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4818 tcg_gen_movi_tl(t1, 0x80000000);
4819 tcg_gen_shr_tl(t1, t1, t0);
4820 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4821 tcg_gen_and_tl(t0, t0, t1);
4822 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4823 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4824 tcg_temp_free(t0);
4825 tcg_temp_free(t1);
4826 if (unlikely(Rc(ctx->opcode) != 0))
4827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4828 }
4829
4830 /* sle - sle. */
4831 static void gen_sle(DisasContext *ctx)
4832 {
4833 TCGv t0 = tcg_temp_new();
4834 TCGv t1 = tcg_temp_new();
4835 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4836 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4837 tcg_gen_subfi_tl(t1, 32, t1);
4838 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4839 tcg_gen_or_tl(t1, t0, t1);
4840 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4841 gen_store_spr(SPR_MQ, t1);
4842 tcg_temp_free(t0);
4843 tcg_temp_free(t1);
4844 if (unlikely(Rc(ctx->opcode) != 0))
4845 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4846 }
4847
4848 /* sleq - sleq. */
4849 static void gen_sleq(DisasContext *ctx)
4850 {
4851 TCGv t0 = tcg_temp_new();
4852 TCGv t1 = tcg_temp_new();
4853 TCGv t2 = tcg_temp_new();
4854 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4855 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4856 tcg_gen_shl_tl(t2, t2, t0);
4857 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4858 gen_load_spr(t1, SPR_MQ);
4859 gen_store_spr(SPR_MQ, t0);
4860 tcg_gen_and_tl(t0, t0, t2);
4861 tcg_gen_andc_tl(t1, t1, t2);
4862 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4863 tcg_temp_free(t0);
4864 tcg_temp_free(t1);
4865 tcg_temp_free(t2);
4866 if (unlikely(Rc(ctx->opcode) != 0))
4867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4868 }
4869
4870 /* sliq - sliq. */
4871 static void gen_sliq(DisasContext *ctx)
4872 {
4873 int sh = SH(ctx->opcode);
4874 TCGv t0 = tcg_temp_new();
4875 TCGv t1 = tcg_temp_new();
4876 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4877 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4878 tcg_gen_or_tl(t1, t0, t1);
4879 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4880 gen_store_spr(SPR_MQ, t1);
4881 tcg_temp_free(t0);
4882 tcg_temp_free(t1);
4883 if (unlikely(Rc(ctx->opcode) != 0))
4884 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4885 }
4886
4887 /* slliq - slliq. */
4888 static void gen_slliq(DisasContext *ctx)
4889 {
4890 int sh = SH(ctx->opcode);
4891 TCGv t0 = tcg_temp_new();
4892 TCGv t1 = tcg_temp_new();
4893 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4894 gen_load_spr(t1, SPR_MQ);
4895 gen_store_spr(SPR_MQ, t0);
4896 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4897 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4898 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4899 tcg_temp_free(t0);
4900 tcg_temp_free(t1);
4901 if (unlikely(Rc(ctx->opcode) != 0))
4902 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4903 }
4904
4905 /* sllq - sllq. */
4906 static void gen_sllq(DisasContext *ctx)
4907 {
4908 int l1 = gen_new_label();
4909 int l2 = gen_new_label();
4910 TCGv t0 = tcg_temp_local_new();
4911 TCGv t1 = tcg_temp_local_new();
4912 TCGv t2 = tcg_temp_local_new();
4913 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4914 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4915 tcg_gen_shl_tl(t1, t1, t2);
4916 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4917 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4918 gen_load_spr(t0, SPR_MQ);
4919 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4920 tcg_gen_br(l2);
4921 gen_set_label(l1);
4922 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4923 gen_load_spr(t2, SPR_MQ);
4924 tcg_gen_andc_tl(t1, t2, t1);
4925 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4926 gen_set_label(l2);
4927 tcg_temp_free(t0);
4928 tcg_temp_free(t1);
4929 tcg_temp_free(t2);
4930 if (unlikely(Rc(ctx->opcode) != 0))
4931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4932 }
4933
4934 /* slq - slq. */
4935 static void gen_slq(DisasContext *ctx)
4936 {
4937 int l1 = gen_new_label();
4938 TCGv t0 = tcg_temp_new();
4939 TCGv t1 = tcg_temp_new();
4940 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4941 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4942 tcg_gen_subfi_tl(t1, 32, t1);
4943 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4944 tcg_gen_or_tl(t1, t0, t1);
4945 gen_store_spr(SPR_MQ, t1);
4946 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4947 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4948 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4949 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4950 gen_set_label(l1);
4951 tcg_temp_free(t0);
4952 tcg_temp_free(t1);
4953 if (unlikely(Rc(ctx->opcode) != 0))
4954 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4955 }
4956
4957 /* sraiq - sraiq. */
4958 static void gen_sraiq(DisasContext *ctx)
4959 {
4960 int sh = SH(ctx->opcode);
4961 int l1 = gen_new_label();
4962 TCGv t0 = tcg_temp_new();
4963 TCGv t1 = tcg_temp_new();
4964 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4965 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4966 tcg_gen_or_tl(t0, t0, t1);
4967 gen_store_spr(SPR_MQ, t0);
4968 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4969 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4970 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4971 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4972 gen_set_label(l1);
4973 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4974 tcg_temp_free(t0);
4975 tcg_temp_free(t1);
4976 if (unlikely(Rc(ctx->opcode) != 0))
4977 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4978 }
4979
4980 /* sraq - sraq. */
4981 static void gen_sraq(DisasContext *ctx)
4982 {
4983 int l1 = gen_new_label();
4984 int l2 = gen_new_label();
4985 TCGv t0 = tcg_temp_new();
4986 TCGv t1 = tcg_temp_local_new();
4987 TCGv t2 = tcg_temp_local_new();
4988 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4989 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4990 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4991 tcg_gen_subfi_tl(t2, 32, t2);
4992 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4993 tcg_gen_or_tl(t0, t0, t2);
4994 gen_store_spr(SPR_MQ, t0);
4995 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4996 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4997 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4998 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4999 gen_set_label(l1);
5000 tcg_temp_free(t0);
5001 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5002 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
5003 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5004 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5005 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
5006 gen_set_label(l2);
5007 tcg_temp_free(t1);
5008 tcg_temp_free(t2);
5009 if (unlikely(Rc(ctx->opcode) != 0))
5010 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5011 }
5012
5013 /* sre - sre. */
5014 static void gen_sre(DisasContext *ctx)
5015 {
5016 TCGv t0 = tcg_temp_new();
5017 TCGv t1 = tcg_temp_new();
5018 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5019 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5020 tcg_gen_subfi_tl(t1, 32, t1);
5021 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5022 tcg_gen_or_tl(t1, t0, t1);
5023 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5024 gen_store_spr(SPR_MQ, t1);
5025 tcg_temp_free(t0);
5026 tcg_temp_free(t1);
5027 if (unlikely(Rc(ctx->opcode) != 0))
5028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5029 }
5030
5031 /* srea - srea. */
5032 static void gen_srea(DisasContext *ctx)
5033 {
5034 TCGv t0 = tcg_temp_new();
5035 TCGv t1 = tcg_temp_new();
5036 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5037 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5038 gen_store_spr(SPR_MQ, t0);
5039 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5040 tcg_temp_free(t0);
5041 tcg_temp_free(t1);
5042 if (unlikely(Rc(ctx->opcode) != 0))
5043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5044 }
5045
5046 /* sreq */
5047 static void gen_sreq(DisasContext *ctx)
5048 {
5049 TCGv t0 = tcg_temp_new();
5050 TCGv t1 = tcg_temp_new();
5051 TCGv t2 = tcg_temp_new();
5052 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5053 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5054 tcg_gen_shr_tl(t1, t1, t0);
5055 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5056 gen_load_spr(t2, SPR_MQ);
5057 gen_store_spr(SPR_MQ, t0);
5058 tcg_gen_and_tl(t0, t0, t1);
5059 tcg_gen_andc_tl(t2, t2, t1);
5060 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5061 tcg_temp_free(t0);
5062 tcg_temp_free(t1);
5063 tcg_temp_free(t2);
5064 if (unlikely(Rc(ctx->opcode) != 0))
5065 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5066 }
5067
5068 /* sriq */
5069 static void gen_sriq(DisasContext *ctx)
5070 {
5071 int sh = SH(ctx->opcode);
5072 TCGv t0 = tcg_temp_new();
5073 TCGv t1 = tcg_temp_new();
5074 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5075 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5076 tcg_gen_or_tl(t1, t0, t1);
5077 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5078 gen_store_spr(SPR_MQ, t1);
5079 tcg_temp_free(t0);
5080 tcg_temp_free(t1);
5081 if (unlikely(Rc(ctx->opcode) != 0))
5082 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5083 }
5084
5085 /* srliq */
5086 static void gen_srliq(DisasContext *ctx)
5087 {
5088 int sh = SH(ctx->opcode);
5089 TCGv t0 = tcg_temp_new();
5090 TCGv t1 = tcg_temp_new();
5091 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5092 gen_load_spr(t1, SPR_MQ);
5093 gen_store_spr(SPR_MQ, t0);
5094 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5095 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5096 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5097 tcg_temp_free(t0);
5098 tcg_temp_free(t1);
5099 if (unlikely(Rc(ctx->opcode) != 0))
5100 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5101 }
5102
5103 /* srlq */
5104 static void gen_srlq(DisasContext *ctx)
5105 {
5106 int l1 = gen_new_label();
5107 int l2 = gen_new_label();
5108 TCGv t0 = tcg_temp_local_new();
5109 TCGv t1 = tcg_temp_local_new();
5110 TCGv t2 = tcg_temp_local_new();
5111 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5112 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5113 tcg_gen_shr_tl(t2, t1, t2);
5114 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5115 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5116 gen_load_spr(t0, SPR_MQ);
5117 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5118 tcg_gen_br(l2);
5119 gen_set_label(l1);
5120 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5121 tcg_gen_and_tl(t0, t0, t2);
5122 gen_load_spr(t1, SPR_MQ);
5123 tcg_gen_andc_tl(t1, t1, t2);
5124 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5125 gen_set_label(l2);
5126 tcg_temp_free(t0);
5127 tcg_temp_free(t1);
5128 tcg_temp_free(t2);
5129 if (unlikely(Rc(ctx->opcode) != 0))
5130 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5131 }
5132
5133 /* srq */
5134 static void gen_srq(DisasContext *ctx)
5135 {
5136 int l1 = gen_new_label();
5137 TCGv t0 = tcg_temp_new();
5138 TCGv t1 = tcg_temp_new();
5139 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5140 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5141 tcg_gen_subfi_tl(t1, 32, t1);
5142 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5143 tcg_gen_or_tl(t1, t0, t1);
5144 gen_store_spr(SPR_MQ, t1);
5145 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5146 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5147 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5148 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5149 gen_set_label(l1);
5150 tcg_temp_free(t0);
5151 tcg_temp_free(t1);
5152 if (unlikely(Rc(ctx->opcode) != 0))
5153 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5154 }
5155
5156 /* PowerPC 602 specific instructions */
5157
5158 /* dsa */
5159 static void gen_dsa(DisasContext *ctx)
5160 {
5161 /* XXX: TODO */
5162 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5163 }
5164
5165 /* esa */
5166 static void gen_esa(DisasContext *ctx)
5167 {
5168 /* XXX: TODO */
5169 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5170 }
5171
5172 /* mfrom */
5173 static void gen_mfrom(DisasContext *ctx)
5174 {
5175 #if defined(CONFIG_USER_ONLY)
5176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5177 #else
5178 if (unlikely(!ctx->mem_idx)) {
5179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5180 return;
5181 }
5182 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5183 #endif
5184 }
5185
5186 /* 602 - 603 - G2 TLB management */
5187
5188 /* tlbld */
5189 static void gen_tlbld_6xx(DisasContext *ctx)
5190 {
5191 #if defined(CONFIG_USER_ONLY)
5192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5193 #else
5194 if (unlikely(!ctx->mem_idx)) {
5195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5196 return;
5197 }
5198 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5199 #endif
5200 }
5201
5202 /* tlbli */
5203 static void gen_tlbli_6xx(DisasContext *ctx)
5204 {
5205 #if defined(CONFIG_USER_ONLY)
5206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5207 #else
5208 if (unlikely(!ctx->mem_idx)) {
5209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5210 return;
5211 }
5212 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5213 #endif
5214 }
5215
5216 /* 74xx TLB management */
5217
5218 /* tlbld */
5219 static void gen_tlbld_74xx(DisasContext *ctx)
5220 {
5221 #if defined(CONFIG_USER_ONLY)
5222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5223 #else
5224 if (unlikely(!ctx->mem_idx)) {
5225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5226 return;
5227 }
5228 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5229 #endif
5230 }
5231
5232 /* tlbli */
5233 static void gen_tlbli_74xx(DisasContext *ctx)
5234 {
5235 #if defined(CONFIG_USER_ONLY)
5236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5237 #else
5238 if (unlikely(!ctx->mem_idx)) {
5239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5240 return;
5241 }
5242 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5243 #endif
5244 }
5245
5246 /* POWER instructions not in PowerPC 601 */
5247
5248 /* clf */
5249 static void gen_clf(DisasContext *ctx)
5250 {
5251 /* Cache line flush: implemented as no-op */
5252 }
5253
5254 /* cli */
5255 static void gen_cli(DisasContext *ctx)
5256 {
5257 /* Cache line invalidate: privileged and treated as no-op */
5258 #if defined(CONFIG_USER_ONLY)
5259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5260 #else
5261 if (unlikely(!ctx->mem_idx)) {
5262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5263 return;
5264 }
5265 #endif
5266 }
5267
5268 /* dclst */
5269 static void gen_dclst(DisasContext *ctx)
5270 {
5271 /* Data cache line store: treated as no-op */
5272 }
5273
5274 static void gen_mfsri(DisasContext *ctx)
5275 {
5276 #if defined(CONFIG_USER_ONLY)
5277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5278 #else
5279 int ra = rA(ctx->opcode);
5280 int rd = rD(ctx->opcode);
5281 TCGv t0;
5282 if (unlikely(!ctx->mem_idx)) {
5283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5284 return;
5285 }
5286 t0 = tcg_temp_new();
5287 gen_addr_reg_index(ctx, t0);
5288 tcg_gen_shri_tl(t0, t0, 28);
5289 tcg_gen_andi_tl(t0, t0, 0xF);
5290 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5291 tcg_temp_free(t0);
5292 if (ra != 0 && ra != rd)
5293 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5294 #endif
5295 }
5296
5297 static void gen_rac(DisasContext *ctx)
5298 {
5299 #if defined(CONFIG_USER_ONLY)
5300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5301 #else
5302 TCGv t0;
5303 if (unlikely(!ctx->mem_idx)) {
5304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5305 return;
5306 }
5307 t0 = tcg_temp_new();
5308 gen_addr_reg_index(ctx, t0);
5309 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5310 tcg_temp_free(t0);
5311 #endif
5312 }
5313
5314 static void gen_rfsvc(DisasContext *ctx)
5315 {
5316 #if defined(CONFIG_USER_ONLY)
5317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5318 #else
5319 if (unlikely(!ctx->mem_idx)) {
5320 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5321 return;
5322 }
5323 gen_helper_rfsvc(cpu_env);
5324 gen_sync_exception(ctx);
5325 #endif
5326 }
5327
5328 /* svc is not implemented for now */
5329
5330 /* POWER2 specific instructions */
5331 /* Quad manipulation (load/store two floats at a time) */
5332
5333 /* lfq */
5334 static void gen_lfq(DisasContext *ctx)
5335 {
5336 int rd = rD(ctx->opcode);
5337 TCGv t0;
5338 gen_set_access_type(ctx, ACCESS_FLOAT);
5339 t0 = tcg_temp_new();
5340 gen_addr_imm_index(ctx, t0, 0);
5341 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5342 gen_addr_add(ctx, t0, t0, 8);
5343 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5344 tcg_temp_free(t0);
5345 }
5346
5347 /* lfqu */
5348 static void gen_lfqu(DisasContext *ctx)
5349 {
5350 int ra = rA(ctx->opcode);
5351 int rd = rD(ctx->opcode);
5352 TCGv t0, t1;
5353 gen_set_access_type(ctx, ACCESS_FLOAT);
5354 t0 = tcg_temp_new();
5355 t1 = tcg_temp_new();
5356 gen_addr_imm_index(ctx, t0, 0);
5357 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5358 gen_addr_add(ctx, t1, t0, 8);
5359 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5360 if (ra != 0)
5361 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5362 tcg_temp_free(t0);
5363 tcg_temp_free(t1);
5364 }
5365
5366 /* lfqux */
5367 static void gen_lfqux(DisasContext *ctx)
5368 {
5369 int ra = rA(ctx->opcode);
5370 int rd = rD(ctx->opcode);
5371 gen_set_access_type(ctx, ACCESS_FLOAT);
5372 TCGv t0, t1;
5373 t0 = tcg_temp_new();
5374 gen_addr_reg_index(ctx, t0);
5375 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5376 t1 = tcg_temp_new();
5377 gen_addr_add(ctx, t1, t0, 8);
5378 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5379 tcg_temp_free(t1);
5380 if (ra != 0)
5381 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5382 tcg_temp_free(t0);
5383 }
5384
5385 /* lfqx */
5386 static void gen_lfqx(DisasContext *ctx)
5387 {
5388 int rd = rD(ctx->opcode);
5389 TCGv t0;
5390 gen_set_access_type(ctx, ACCESS_FLOAT);
5391 t0 = tcg_temp_new();
5392 gen_addr_reg_index(ctx, t0);
5393 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5394 gen_addr_add(ctx, t0, t0, 8);
5395 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5396 tcg_temp_free(t0);
5397 }
5398
5399 /* stfq */
5400 static void gen_stfq(DisasContext *ctx)
5401 {
5402 int rd = rD(ctx->opcode);
5403 TCGv t0;
5404 gen_set_access_type(ctx, ACCESS_FLOAT);
5405 t0 = tcg_temp_new();
5406 gen_addr_imm_index(ctx, t0, 0);
5407 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5408 gen_addr_add(ctx, t0, t0, 8);
5409 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5410 tcg_temp_free(t0);
5411 }
5412
5413 /* stfqu */
5414 static void gen_stfqu(DisasContext *ctx)
5415 {
5416 int ra = rA(ctx->opcode);
5417 int rd = rD(ctx->opcode);
5418 TCGv t0, t1;
5419 gen_set_access_type(ctx, ACCESS_FLOAT);
5420 t0 = tcg_temp_new();
5421 gen_addr_imm_index(ctx, t0, 0);
5422 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5423 t1 = tcg_temp_new();
5424 gen_addr_add(ctx, t1, t0, 8);
5425 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5426 tcg_temp_free(t1);
5427 if (ra != 0)
5428 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5429 tcg_temp_free(t0);
5430 }
5431
5432 /* stfqux */
5433 static void gen_stfqux(DisasContext *ctx)
5434 {
5435 int ra = rA(ctx->opcode);
5436 int rd = rD(ctx->opcode);
5437 TCGv t0, t1;
5438 gen_set_access_type(ctx, ACCESS_FLOAT);
5439 t0 = tcg_temp_new();
5440 gen_addr_reg_index(ctx, t0);
5441 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5442 t1 = tcg_temp_new();
5443 gen_addr_add(ctx, t1, t0, 8);
5444 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5445 tcg_temp_free(t1);
5446 if (ra != 0)
5447 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5448 tcg_temp_free(t0);
5449 }
5450
5451 /* stfqx */
5452 static void gen_stfqx(DisasContext *ctx)
5453 {
5454 int rd = rD(ctx->opcode);
5455 TCGv t0;
5456 gen_set_access_type(ctx, ACCESS_FLOAT);
5457 t0 = tcg_temp_new();
5458 gen_addr_reg_index(ctx, t0);
5459 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5460 gen_addr_add(ctx, t0, t0, 8);
5461 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5462 tcg_temp_free(t0);
5463 }
5464
5465 /* BookE specific instructions */
5466
5467 /* XXX: not implemented on 440 ? */
5468 static void gen_mfapidi(DisasContext *ctx)
5469 {
5470 /* XXX: TODO */
5471 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5472 }
5473
5474 /* XXX: not implemented on 440 ? */
5475 static void gen_tlbiva(DisasContext *ctx)
5476 {
5477 #if defined(CONFIG_USER_ONLY)
5478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5479 #else
5480 TCGv t0;
5481 if (unlikely(!ctx->mem_idx)) {
5482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5483 return;
5484 }
5485 t0 = tcg_temp_new();
5486 gen_addr_reg_index(ctx, t0);
5487 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5488 tcg_temp_free(t0);
5489 #endif
5490 }
5491
5492 /* All 405 MAC instructions are translated here */
5493 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5494 int ra, int rb, int rt, int Rc)
5495 {
5496 TCGv t0, t1;
5497
5498 t0 = tcg_temp_local_new();
5499 t1 = tcg_temp_local_new();
5500
5501 switch (opc3 & 0x0D) {
5502 case 0x05:
5503 /* macchw - macchw. - macchwo - macchwo. */
5504 /* macchws - macchws. - macchwso - macchwso. */
5505 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5506 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5507 /* mulchw - mulchw. */
5508 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5509 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5510 tcg_gen_ext16s_tl(t1, t1);
5511 break;
5512 case 0x04:
5513 /* macchwu - macchwu. - macchwuo - macchwuo. */
5514 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5515 /* mulchwu - mulchwu. */
5516 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5517 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5518 tcg_gen_ext16u_tl(t1, t1);
5519 break;
5520 case 0x01:
5521 /* machhw - machhw. - machhwo - machhwo. */
5522 /* machhws - machhws. - machhwso - machhwso. */
5523 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5524 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5525 /* mulhhw - mulhhw. */
5526 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5527 tcg_gen_ext16s_tl(t0, t0);
5528 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5529 tcg_gen_ext16s_tl(t1, t1);
5530 break;
5531 case 0x00:
5532 /* machhwu - machhwu. - machhwuo - machhwuo. */
5533 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5534 /* mulhhwu - mulhhwu. */
5535 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5536 tcg_gen_ext16u_tl(t0, t0);
5537 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5538 tcg_gen_ext16u_tl(t1, t1);
5539 break;
5540 case 0x0D:
5541 /* maclhw - maclhw. - maclhwo - maclhwo. */
5542 /* maclhws - maclhws. - maclhwso - maclhwso. */
5543 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5544 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5545 /* mullhw - mullhw. */
5546 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5547 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5548 break;
5549 case 0x0C:
5550 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5551 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5552 /* mullhwu - mullhwu. */
5553 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5554 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5555 break;
5556 }
5557 if (opc2 & 0x04) {
5558 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5559 tcg_gen_mul_tl(t1, t0, t1);
5560 if (opc2 & 0x02) {
5561 /* nmultiply-and-accumulate (0x0E) */
5562 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5563 } else {
5564 /* multiply-and-accumulate (0x0C) */
5565 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5566 }
5567
5568 if (opc3 & 0x12) {
5569 /* Check overflow and/or saturate */
5570 int l1 = gen_new_label();
5571
5572 if (opc3 & 0x10) {
5573 /* Start with XER OV disabled, the most likely case */
5574 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5575 }
5576 if (opc3 & 0x01) {
5577 /* Signed */
5578 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5579 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5580 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5581 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5582 if (opc3 & 0x02) {
5583 /* Saturate */
5584 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5585 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5586 }
5587 } else {
5588 /* Unsigned */
5589 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5590 if (opc3 & 0x02) {
5591 /* Saturate */
5592 tcg_gen_movi_tl(t0, UINT32_MAX);
5593 }
5594 }
5595 if (opc3 & 0x10) {
5596 /* Check overflow */
5597 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5598 }
5599 gen_set_label(l1);
5600 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5601 }
5602 } else {
5603 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5604 }
5605 tcg_temp_free(t0);
5606 tcg_temp_free(t1);
5607 if (unlikely(Rc) != 0) {
5608 /* Update Rc0 */
5609 gen_set_Rc0(ctx, cpu_gpr[rt]);
5610 }
5611 }
5612
5613 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5614 static void glue(gen_, name)(DisasContext *ctx) \
5615 { \
5616 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5617 rD(ctx->opcode), Rc(ctx->opcode)); \
5618 }
5619
5620 /* macchw - macchw. */
5621 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5622 /* macchwo - macchwo. */
5623 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5624 /* macchws - macchws. */
5625 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5626 /* macchwso - macchwso. */
5627 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5628 /* macchwsu - macchwsu. */
5629 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5630 /* macchwsuo - macchwsuo. */
5631 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5632 /* macchwu - macchwu. */
5633 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5634 /* macchwuo - macchwuo. */
5635 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5636 /* machhw - machhw. */
5637 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5638 /* machhwo - machhwo. */
5639 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5640 /* machhws - machhws. */
5641 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5642 /* machhwso - machhwso. */
5643 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5644 /* machhwsu - machhwsu. */
5645 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5646 /* machhwsuo - machhwsuo. */
5647 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5648 /* machhwu - machhwu. */
5649 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5650 /* machhwuo - machhwuo. */
5651 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5652 /* maclhw - maclhw. */
5653 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5654 /* maclhwo - maclhwo. */
5655 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5656 /* maclhws - maclhws. */
5657 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5658 /* maclhwso - maclhwso. */
5659 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5660 /* maclhwu - maclhwu. */
5661 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5662 /* maclhwuo - maclhwuo. */
5663 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5664 /* maclhwsu - maclhwsu. */
5665 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5666 /* maclhwsuo - maclhwsuo. */
5667 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5668 /* nmacchw - nmacchw. */
5669 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5670 /* nmacchwo - nmacchwo. */
5671 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5672 /* nmacchws - nmacchws. */
5673 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5674 /* nmacchwso - nmacchwso. */
5675 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5676 /* nmachhw - nmachhw. */
5677 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5678 /* nmachhwo - nmachhwo. */
5679 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5680 /* nmachhws - nmachhws. */
5681 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5682 /* nmachhwso - nmachhwso. */
5683 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5684 /* nmaclhw - nmaclhw. */
5685 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5686 /* nmaclhwo - nmaclhwo. */
5687 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5688 /* nmaclhws - nmaclhws. */
5689 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5690 /* nmaclhwso - nmaclhwso. */
5691 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5692
5693 /* mulchw - mulchw. */
5694 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5695 /* mulchwu - mulchwu. */
5696 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5697 /* mulhhw - mulhhw. */
5698 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5699 /* mulhhwu - mulhhwu. */
5700 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5701 /* mullhw - mullhw. */
5702 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5703 /* mullhwu - mullhwu. */
5704 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5705
5706 /* mfdcr */
5707 static void gen_mfdcr(DisasContext *ctx)
5708 {
5709 #if defined(CONFIG_USER_ONLY)
5710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5711 #else
5712 TCGv dcrn;
5713 if (unlikely(!ctx->mem_idx)) {
5714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5715 return;
5716 }
5717 /* NIP cannot be restored if the memory exception comes from an helper */
5718 gen_update_nip(ctx, ctx->nip - 4);
5719 dcrn = tcg_const_tl(SPR(ctx->opcode));
5720 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5721 tcg_temp_free(dcrn);
5722 #endif
5723 }
5724
5725 /* mtdcr */
5726 static void gen_mtdcr(DisasContext *ctx)
5727 {
5728 #if defined(CONFIG_USER_ONLY)
5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5730 #else
5731 TCGv dcrn;
5732 if (unlikely(!ctx->mem_idx)) {
5733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5734 return;
5735 }
5736 /* NIP cannot be restored if the memory exception comes from an helper */
5737 gen_update_nip(ctx, ctx->nip - 4);
5738 dcrn = tcg_const_tl(SPR(ctx->opcode));
5739 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5740 tcg_temp_free(dcrn);
5741 #endif
5742 }
5743
5744 /* mfdcrx */
5745 /* XXX: not implemented on 440 ? */
5746 static void gen_mfdcrx(DisasContext *ctx)
5747 {
5748 #if defined(CONFIG_USER_ONLY)
5749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5750 #else
5751 if (unlikely(!ctx->mem_idx)) {
5752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5753 return;
5754 }
5755 /* NIP cannot be restored if the memory exception comes from an helper */
5756 gen_update_nip(ctx, ctx->nip - 4);
5757 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5758 cpu_gpr[rA(ctx->opcode)]);
5759 /* Note: Rc update flag set leads to undefined state of Rc0 */
5760 #endif
5761 }
5762
5763 /* mtdcrx */
5764 /* XXX: not implemented on 440 ? */
5765 static void gen_mtdcrx(DisasContext *ctx)
5766 {
5767 #if defined(CONFIG_USER_ONLY)
5768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5769 #else
5770 if (unlikely(!ctx->mem_idx)) {
5771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5772 return;
5773 }
5774 /* NIP cannot be restored if the memory exception comes from an helper */
5775 gen_update_nip(ctx, ctx->nip - 4);
5776 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5777 cpu_gpr[rS(ctx->opcode)]);
5778 /* Note: Rc update flag set leads to undefined state of Rc0 */
5779 #endif
5780 }
5781
5782 /* mfdcrux (PPC 460) : user-mode access to DCR */
5783 static void gen_mfdcrux(DisasContext *ctx)
5784 {
5785 /* NIP cannot be restored if the memory exception comes from an helper */
5786 gen_update_nip(ctx, ctx->nip - 4);
5787 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5788 cpu_gpr[rA(ctx->opcode)]);
5789 /* Note: Rc update flag set leads to undefined state of Rc0 */
5790 }
5791
5792 /* mtdcrux (PPC 460) : user-mode access to DCR */
5793 static void gen_mtdcrux(DisasContext *ctx)
5794 {
5795 /* NIP cannot be restored if the memory exception comes from an helper */
5796 gen_update_nip(ctx, ctx->nip - 4);
5797 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5798 cpu_gpr[rS(ctx->opcode)]);
5799 /* Note: Rc update flag set leads to undefined state of Rc0 */
5800 }
5801
5802 /* dccci */
5803 static void gen_dccci(DisasContext *ctx)
5804 {
5805 #if defined(CONFIG_USER_ONLY)
5806 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5807 #else
5808 if (unlikely(!ctx->mem_idx)) {
5809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5810 return;
5811 }
5812 /* interpreted as no-op */
5813 #endif
5814 }
5815
5816 /* dcread */
5817 static void gen_dcread(DisasContext *ctx)
5818 {
5819 #if defined(CONFIG_USER_ONLY)
5820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5821 #else
5822 TCGv EA, val;
5823 if (unlikely(!ctx->mem_idx)) {
5824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5825 return;
5826 }
5827 gen_set_access_type(ctx, ACCESS_CACHE);
5828 EA = tcg_temp_new();
5829 gen_addr_reg_index(ctx, EA);
5830 val = tcg_temp_new();
5831 gen_qemu_ld32u(ctx, val, EA);
5832 tcg_temp_free(val);
5833 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5834 tcg_temp_free(EA);
5835 #endif
5836 }
5837
5838 /* icbt */
5839 static void gen_icbt_40x(DisasContext *ctx)
5840 {
5841 /* interpreted as no-op */
5842 /* XXX: specification say this is treated as a load by the MMU
5843 * but does not generate any exception
5844 */
5845 }
5846
5847 /* iccci */
5848 static void gen_iccci(DisasContext *ctx)
5849 {
5850 #if defined(CONFIG_USER_ONLY)
5851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5852 #else
5853 if (unlikely(!ctx->mem_idx)) {
5854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5855 return;
5856 }
5857 /* interpreted as no-op */
5858 #endif
5859 }
5860
5861 /* icread */
5862 static void gen_icread(DisasContext *ctx)
5863 {
5864 #if defined(CONFIG_USER_ONLY)
5865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5866 #else
5867 if (unlikely(!ctx->mem_idx)) {
5868 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5869 return;
5870 }
5871 /* interpreted as no-op */
5872 #endif
5873 }
5874
5875 /* rfci (mem_idx only) */
5876 static void gen_rfci_40x(DisasContext *ctx)
5877 {
5878 #if defined(CONFIG_USER_ONLY)
5879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5880 #else
5881 if (unlikely(!ctx->mem_idx)) {
5882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5883 return;
5884 }
5885 /* Restore CPU state */
5886 gen_helper_40x_rfci(cpu_env);
5887 gen_sync_exception(ctx);
5888 #endif
5889 }
5890
5891 static void gen_rfci(DisasContext *ctx)
5892 {
5893 #if defined(CONFIG_USER_ONLY)
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 #else
5896 if (unlikely(!ctx->mem_idx)) {
5897 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5898 return;
5899 }
5900 /* Restore CPU state */
5901 gen_helper_rfci(cpu_env);
5902 gen_sync_exception(ctx);
5903 #endif
5904 }
5905
5906 /* BookE specific */
5907
5908 /* XXX: not implemented on 440 ? */
5909 static void gen_rfdi(DisasContext *ctx)
5910 {
5911 #if defined(CONFIG_USER_ONLY)
5912 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5913 #else
5914 if (unlikely(!ctx->mem_idx)) {
5915 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5916 return;
5917 }
5918 /* Restore CPU state */
5919 gen_helper_rfdi(cpu_env);
5920 gen_sync_exception(ctx);
5921 #endif
5922 }
5923
5924 /* XXX: not implemented on 440 ? */
5925 static void gen_rfmci(DisasContext *ctx)
5926 {
5927 #if defined(CONFIG_USER_ONLY)
5928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5929 #else
5930 if (unlikely(!ctx->mem_idx)) {
5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5932 return;
5933 }
5934 /* Restore CPU state */
5935 gen_helper_rfmci(cpu_env);
5936 gen_sync_exception(ctx);
5937 #endif
5938 }
5939
5940 /* TLB management - PowerPC 405 implementation */
5941
5942 /* tlbre */
5943 static void gen_tlbre_40x(DisasContext *ctx)
5944 {
5945 #if defined(CONFIG_USER_ONLY)
5946 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5947 #else
5948 if (unlikely(!ctx->mem_idx)) {
5949 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5950 return;
5951 }
5952 switch (rB(ctx->opcode)) {
5953 case 0:
5954 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5955 cpu_gpr[rA(ctx->opcode)]);
5956 break;
5957 case 1:
5958 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5959 cpu_gpr[rA(ctx->opcode)]);
5960 break;
5961 default:
5962 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5963 break;
5964 }
5965 #endif
5966 }
5967
5968 /* tlbsx - tlbsx. */
5969 static void gen_tlbsx_40x(DisasContext *ctx)
5970 {
5971 #if defined(CONFIG_USER_ONLY)
5972 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5973 #else
5974 TCGv t0;
5975 if (unlikely(!ctx->mem_idx)) {
5976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5977 return;
5978 }
5979 t0 = tcg_temp_new();
5980 gen_addr_reg_index(ctx, t0);
5981 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5982 tcg_temp_free(t0);
5983 if (Rc(ctx->opcode)) {
5984 int l1 = gen_new_label();
5985 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5986 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5987 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5988 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5989 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5990 gen_set_label(l1);
5991 }
5992 #endif
5993 }
5994
5995 /* tlbwe */
5996 static void gen_tlbwe_40x(DisasContext *ctx)
5997 {
5998 #if defined(CONFIG_USER_ONLY)
5999 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6000 #else
6001 if (unlikely(!ctx->mem_idx)) {
6002 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6003 return;
6004 }
6005 switch (rB(ctx->opcode)) {
6006 case 0:
6007 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6008 cpu_gpr[rS(ctx->opcode)]);
6009 break;
6010 case 1:
6011 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6012 cpu_gpr[rS(ctx->opcode)]);
6013 break;
6014 default:
6015 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6016 break;
6017 }
6018 #endif
6019 }
6020
6021 /* TLB management - PowerPC 440 implementation */
6022
6023 /* tlbre */
6024 static void gen_tlbre_440(DisasContext *ctx)
6025 {
6026 #if defined(CONFIG_USER_ONLY)
6027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6028 #else
6029 if (unlikely(!ctx->mem_idx)) {
6030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6031 return;
6032 }
6033 switch (rB(ctx->opcode)) {
6034 case 0:
6035 case 1:
6036 case 2:
6037 {
6038 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6039 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6040 t0, cpu_gpr[rA(ctx->opcode)]);
6041 tcg_temp_free_i32(t0);
6042 }
6043 break;
6044 default:
6045 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6046 break;
6047 }
6048 #endif
6049 }
6050
6051 /* tlbsx - tlbsx. */
6052 static void gen_tlbsx_440(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6056 #else
6057 TCGv t0;
6058 if (unlikely(!ctx->mem_idx)) {
6059 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6060 return;
6061 }
6062 t0 = tcg_temp_new();
6063 gen_addr_reg_index(ctx, t0);
6064 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6065 tcg_temp_free(t0);
6066 if (Rc(ctx->opcode)) {
6067 int l1 = gen_new_label();
6068 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6069 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6070 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6071 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6072 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6073 gen_set_label(l1);
6074 }
6075 #endif
6076 }
6077
6078 /* tlbwe */
6079 static void gen_tlbwe_440(DisasContext *ctx)
6080 {
6081 #if defined(CONFIG_USER_ONLY)
6082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6083 #else
6084 if (unlikely(!ctx->mem_idx)) {
6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6086 return;
6087 }
6088 switch (rB(ctx->opcode)) {
6089 case 0:
6090 case 1:
6091 case 2:
6092 {
6093 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6094 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6095 cpu_gpr[rS(ctx->opcode)]);
6096 tcg_temp_free_i32(t0);
6097 }
6098 break;
6099 default:
6100 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6101 break;
6102 }
6103 #endif
6104 }
6105
6106 /* TLB management - PowerPC BookE 2.06 implementation */
6107
6108 /* tlbre */
6109 static void gen_tlbre_booke206(DisasContext *ctx)
6110 {
6111 #if defined(CONFIG_USER_ONLY)
6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6113 #else
6114 if (unlikely(!ctx->mem_idx)) {
6115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6116 return;
6117 }
6118
6119 gen_helper_booke206_tlbre(cpu_env);
6120 #endif
6121 }
6122
6123 /* tlbsx - tlbsx. */
6124 static void gen_tlbsx_booke206(DisasContext *ctx)
6125 {
6126 #if defined(CONFIG_USER_ONLY)
6127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6128 #else
6129 TCGv t0;
6130 if (unlikely(!ctx->mem_idx)) {
6131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6132 return;
6133 }
6134
6135 if (rA(ctx->opcode)) {
6136 t0 = tcg_temp_new();
6137 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6138 } else {
6139 t0 = tcg_const_tl(0);
6140 }
6141
6142 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6143 gen_helper_booke206_tlbsx(cpu_env, t0);
6144 #endif
6145 }
6146
6147 /* tlbwe */
6148 static void gen_tlbwe_booke206(DisasContext *ctx)
6149 {
6150 #if defined(CONFIG_USER_ONLY)
6151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6152 #else
6153 if (unlikely(!ctx->mem_idx)) {
6154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6155 return;
6156 }
6157 gen_update_nip(ctx, ctx->nip - 4);
6158 gen_helper_booke206_tlbwe(cpu_env);
6159 #endif
6160 }
6161
6162 static void gen_tlbivax_booke206(DisasContext *ctx)
6163 {
6164 #if defined(CONFIG_USER_ONLY)
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6166 #else
6167 TCGv t0;
6168 if (unlikely(!ctx->mem_idx)) {
6169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6170 return;
6171 }
6172
6173 t0 = tcg_temp_new();
6174 gen_addr_reg_index(ctx, t0);
6175
6176 gen_helper_booke206_tlbivax(cpu_env, t0);
6177 #endif
6178 }
6179
6180 static void gen_tlbilx_booke206(DisasContext *ctx)
6181 {
6182 #if defined(CONFIG_USER_ONLY)
6183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6184 #else
6185 TCGv t0;
6186 if (unlikely(!ctx->mem_idx)) {
6187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6188 return;
6189 }
6190
6191 t0 = tcg_temp_new();
6192 gen_addr_reg_index(ctx, t0);
6193
6194 switch((ctx->opcode >> 21) & 0x3) {
6195 case 0:
6196 gen_helper_booke206_tlbilx0(cpu_env, t0);
6197 break;
6198 case 1:
6199 gen_helper_booke206_tlbilx1(cpu_env, t0);
6200 break;
6201 case 3:
6202 gen_helper_booke206_tlbilx3(cpu_env, t0);
6203 break;
6204 default:
6205 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6206 break;
6207 }
6208
6209 tcg_temp_free(t0);
6210 #endif
6211 }
6212
6213
6214 /* wrtee */
6215 static void gen_wrtee(DisasContext *ctx)
6216 {
6217 #if defined(CONFIG_USER_ONLY)
6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6219 #else
6220 TCGv t0;
6221 if (unlikely(!ctx->mem_idx)) {
6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6223 return;
6224 }
6225 t0 = tcg_temp_new();
6226 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6227 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6228 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6229 tcg_temp_free(t0);
6230 /* Stop translation to have a chance to raise an exception
6231 * if we just set msr_ee to 1
6232 */
6233 gen_stop_exception(ctx);
6234 #endif
6235 }
6236
6237 /* wrteei */
6238 static void gen_wrteei(DisasContext *ctx)
6239 {
6240 #if defined(CONFIG_USER_ONLY)
6241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6242 #else
6243 if (unlikely(!ctx->mem_idx)) {
6244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6245 return;
6246 }
6247 if (ctx->opcode & 0x00008000) {
6248 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6249 /* Stop translation to have a chance to raise an exception */
6250 gen_stop_exception(ctx);
6251 } else {
6252 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6253 }
6254 #endif
6255 }
6256
6257 /* PowerPC 440 specific instructions */
6258
6259 /* dlmzb */
6260 static void gen_dlmzb(DisasContext *ctx)
6261 {
6262 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6263 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6264 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6265 tcg_temp_free_i32(t0);
6266 }
6267
6268 /* mbar replaces eieio on 440 */
6269 static void gen_mbar(DisasContext *ctx)
6270 {
6271 /* interpreted as no-op */
6272 }
6273
6274 /* msync replaces sync on 440 */
6275 static void gen_msync_4xx(DisasContext *ctx)
6276 {
6277 /* interpreted as no-op */
6278 }
6279
6280 /* icbt */
6281 static void gen_icbt_440(DisasContext *ctx)
6282 {
6283 /* interpreted as no-op */
6284 /* XXX: specification say this is treated as a load by the MMU
6285 * but does not generate any exception
6286 */
6287 }
6288
6289 /* Embedded.Processor Control */
6290
6291 static void gen_msgclr(DisasContext *ctx)
6292 {
6293 #if defined(CONFIG_USER_ONLY)
6294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6295 #else
6296 if (unlikely(ctx->mem_idx == 0)) {
6297 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6298 return;
6299 }
6300
6301 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6302 #endif
6303 }
6304
6305 static void gen_msgsnd(DisasContext *ctx)
6306 {
6307 #if defined(CONFIG_USER_ONLY)
6308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6309 #else
6310 if (unlikely(ctx->mem_idx == 0)) {
6311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6312 return;
6313 }
6314
6315 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6316 #endif
6317 }
6318
6319 /*** Altivec vector extension ***/
6320 /* Altivec registers moves */
6321
6322 static inline TCGv_ptr gen_avr_ptr(int reg)
6323 {
6324 TCGv_ptr r = tcg_temp_new_ptr();
6325 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6326 return r;
6327 }
6328
6329 #define GEN_VR_LDX(name, opc2, opc3) \
6330 static void glue(gen_, name)(DisasContext *ctx) \
6331 { \
6332 TCGv EA; \
6333 if (unlikely(!ctx->altivec_enabled)) { \
6334 gen_exception(ctx, POWERPC_EXCP_VPU); \
6335 return; \
6336 } \
6337 gen_set_access_type(ctx, ACCESS_INT); \
6338 EA = tcg_temp_new(); \
6339 gen_addr_reg_index(ctx, EA); \
6340 tcg_gen_andi_tl(EA, EA, ~0xf); \
6341 if (ctx->le_mode) { \
6342 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6343 tcg_gen_addi_tl(EA, EA, 8); \
6344 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6345 } else { \
6346 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6347 tcg_gen_addi_tl(EA, EA, 8); \
6348 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6349 } \
6350 tcg_temp_free(EA); \
6351 }
6352
6353 #define GEN_VR_STX(name, opc2, opc3) \
6354 static void gen_st##name(DisasContext *ctx) \
6355 { \
6356 TCGv EA; \
6357 if (unlikely(!ctx->altivec_enabled)) { \
6358 gen_exception(ctx, POWERPC_EXCP_VPU); \
6359 return; \
6360 } \
6361 gen_set_access_type(ctx, ACCESS_INT); \
6362 EA = tcg_temp_new(); \
6363 gen_addr_reg_index(ctx, EA); \
6364 tcg_gen_andi_tl(EA, EA, ~0xf); \
6365 if (ctx->le_mode) { \
6366 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6367 tcg_gen_addi_tl(EA, EA, 8); \
6368 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6369 } else { \
6370 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6371 tcg_gen_addi_tl(EA, EA, 8); \
6372 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6373 } \
6374 tcg_temp_free(EA); \
6375 }
6376
6377 #define GEN_VR_LVE(name, opc2, opc3) \
6378 static void gen_lve##name(DisasContext *ctx) \
6379 { \
6380 TCGv EA; \
6381 TCGv_ptr rs; \
6382 if (unlikely(!ctx->altivec_enabled)) { \
6383 gen_exception(ctx, POWERPC_EXCP_VPU); \
6384 return; \
6385 } \
6386 gen_set_access_type(ctx, ACCESS_INT); \
6387 EA = tcg_temp_new(); \
6388 gen_addr_reg_index(ctx, EA); \
6389 rs = gen_avr_ptr(rS(ctx->opcode)); \
6390 gen_helper_lve##name(cpu_env, rs, EA); \
6391 tcg_temp_free(EA); \
6392 tcg_temp_free_ptr(rs); \
6393 }
6394
6395 #define GEN_VR_STVE(name, opc2, opc3) \
6396 static void gen_stve##name(DisasContext *ctx) \
6397 { \
6398 TCGv EA; \
6399 TCGv_ptr rs; \
6400 if (unlikely(!ctx->altivec_enabled)) { \
6401 gen_exception(ctx, POWERPC_EXCP_VPU); \
6402 return; \
6403 } \
6404 gen_set_access_type(ctx, ACCESS_INT); \
6405 EA = tcg_temp_new(); \
6406 gen_addr_reg_index(ctx, EA); \
6407 rs = gen_avr_ptr(rS(ctx->opcode)); \
6408 gen_helper_stve##name(cpu_env, rs, EA); \
6409 tcg_temp_free(EA); \
6410 tcg_temp_free_ptr(rs); \
6411 }
6412
6413 GEN_VR_LDX(lvx, 0x07, 0x03);
6414 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6415 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6416
6417 GEN_VR_LVE(bx, 0x07, 0x00);
6418 GEN_VR_LVE(hx, 0x07, 0x01);
6419 GEN_VR_LVE(wx, 0x07, 0x02);
6420
6421 GEN_VR_STX(svx, 0x07, 0x07);
6422 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6423 GEN_VR_STX(svxl, 0x07, 0x0F);
6424
6425 GEN_VR_STVE(bx, 0x07, 0x04);
6426 GEN_VR_STVE(hx, 0x07, 0x05);
6427 GEN_VR_STVE(wx, 0x07, 0x06);
6428
6429 static void gen_lvsl(DisasContext *ctx)
6430 {
6431 TCGv_ptr rd;
6432 TCGv EA;
6433 if (unlikely(!ctx->altivec_enabled)) {
6434 gen_exception(ctx, POWERPC_EXCP_VPU);
6435 return;
6436 }
6437 EA = tcg_temp_new();
6438 gen_addr_reg_index(ctx, EA);
6439 rd = gen_avr_ptr(rD(ctx->opcode));
6440 gen_helper_lvsl(rd, EA);
6441 tcg_temp_free(EA);
6442 tcg_temp_free_ptr(rd);
6443 }
6444
6445 static void gen_lvsr(DisasContext *ctx)
6446 {
6447 TCGv_ptr rd;
6448 TCGv EA;
6449 if (unlikely(!ctx->altivec_enabled)) {
6450 gen_exception(ctx, POWERPC_EXCP_VPU);
6451 return;
6452 }
6453 EA = tcg_temp_new();
6454 gen_addr_reg_index(ctx, EA);
6455 rd = gen_avr_ptr(rD(ctx->opcode));
6456 gen_helper_lvsr(rd, EA);
6457 tcg_temp_free(EA);
6458 tcg_temp_free_ptr(rd);
6459 }
6460
6461 static void gen_mfvscr(DisasContext *ctx)
6462 {
6463 TCGv_i32 t;
6464 if (unlikely(!ctx->altivec_enabled)) {
6465 gen_exception(ctx, POWERPC_EXCP_VPU);
6466 return;
6467 }
6468 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6469 t = tcg_temp_new_i32();
6470 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6471 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6472 tcg_temp_free_i32(t);
6473 }
6474
6475 static void gen_mtvscr(DisasContext *ctx)
6476 {
6477 TCGv_ptr p;
6478 if (unlikely(!ctx->altivec_enabled)) {
6479 gen_exception(ctx, POWERPC_EXCP_VPU);
6480 return;
6481 }
6482 p = gen_avr_ptr(rD(ctx->opcode));
6483 gen_helper_mtvscr(cpu_env, p);
6484 tcg_temp_free_ptr(p);
6485 }
6486
6487 /* Logical operations */
6488 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6489 static void glue(gen_, name)(DisasContext *ctx) \
6490 { \
6491 if (unlikely(!ctx->altivec_enabled)) { \
6492 gen_exception(ctx, POWERPC_EXCP_VPU); \
6493 return; \
6494 } \
6495 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6496 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6497 }
6498
6499 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6500 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6501 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6502 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6503 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6504
6505 #define GEN_VXFORM(name, opc2, opc3) \
6506 static void glue(gen_, name)(DisasContext *ctx) \
6507 { \
6508 TCGv_ptr ra, rb, rd; \
6509 if (unlikely(!ctx->altivec_enabled)) { \
6510 gen_exception(ctx, POWERPC_EXCP_VPU); \
6511 return; \
6512 } \
6513 ra = gen_avr_ptr(rA(ctx->opcode)); \
6514 rb = gen_avr_ptr(rB(ctx->opcode)); \
6515 rd = gen_avr_ptr(rD(ctx->opcode)); \
6516 gen_helper_##name (rd, ra, rb); \
6517 tcg_temp_free_ptr(ra); \
6518 tcg_temp_free_ptr(rb); \
6519 tcg_temp_free_ptr(rd); \
6520 }
6521
6522 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6523 static void glue(gen_, name)(DisasContext *ctx) \
6524 { \
6525 TCGv_ptr ra, rb, rd; \
6526 if (unlikely(!ctx->altivec_enabled)) { \
6527 gen_exception(ctx, POWERPC_EXCP_VPU); \
6528 return; \
6529 } \
6530 ra = gen_avr_ptr(rA(ctx->opcode)); \
6531 rb = gen_avr_ptr(rB(ctx->opcode)); \
6532 rd = gen_avr_ptr(rD(ctx->opcode)); \
6533 gen_helper_##name(rd, cpu_env, ra, rb); \
6534 tcg_temp_free_ptr(ra); \
6535 tcg_temp_free_ptr(rb); \
6536 tcg_temp_free_ptr(rd); \
6537 }
6538
6539 GEN_VXFORM(vaddubm, 0, 0);
6540 GEN_VXFORM(vadduhm, 0, 1);
6541 GEN_VXFORM(vadduwm, 0, 2);
6542 GEN_VXFORM(vsububm, 0, 16);
6543 GEN_VXFORM(vsubuhm, 0, 17);
6544 GEN_VXFORM(vsubuwm, 0, 18);
6545 GEN_VXFORM(vmaxub, 1, 0);
6546 GEN_VXFORM(vmaxuh, 1, 1);
6547 GEN_VXFORM(vmaxuw, 1, 2);
6548 GEN_VXFORM(vmaxsb, 1, 4);
6549 GEN_VXFORM(vmaxsh, 1, 5);
6550 GEN_VXFORM(vmaxsw, 1, 6);
6551 GEN_VXFORM(vminub, 1, 8);
6552 GEN_VXFORM(vminuh, 1, 9);
6553 GEN_VXFORM(vminuw, 1, 10);
6554 GEN_VXFORM(vminsb, 1, 12);
6555 GEN_VXFORM(vminsh, 1, 13);
6556 GEN_VXFORM(vminsw, 1, 14);
6557 GEN_VXFORM(vavgub, 1, 16);
6558 GEN_VXFORM(vavguh, 1, 17);
6559 GEN_VXFORM(vavguw, 1, 18);
6560 GEN_VXFORM(vavgsb, 1, 20);
6561 GEN_VXFORM(vavgsh, 1, 21);
6562 GEN_VXFORM(vavgsw, 1, 22);
6563 GEN_VXFORM(vmrghb, 6, 0);
6564 GEN_VXFORM(vmrghh, 6, 1);
6565 GEN_VXFORM(vmrghw, 6, 2);
6566 GEN_VXFORM(vmrglb, 6, 4);
6567 GEN_VXFORM(vmrglh, 6, 5);
6568 GEN_VXFORM(vmrglw, 6, 6);
6569 GEN_VXFORM(vmuloub, 4, 0);
6570 GEN_VXFORM(vmulouh, 4, 1);
6571 GEN_VXFORM(vmulosb, 4, 4);
6572 GEN_VXFORM(vmulosh, 4, 5);
6573 GEN_VXFORM(vmuleub, 4, 8);
6574 GEN_VXFORM(vmuleuh, 4, 9);
6575 GEN_VXFORM(vmulesb, 4, 12);
6576 GEN_VXFORM(vmulesh, 4, 13);
6577 GEN_VXFORM(vslb, 2, 4);
6578 GEN_VXFORM(vslh, 2, 5);
6579 GEN_VXFORM(vslw, 2, 6);
6580 GEN_VXFORM(vsrb, 2, 8);
6581 GEN_VXFORM(vsrh, 2, 9);
6582 GEN_VXFORM(vsrw, 2, 10);
6583 GEN_VXFORM(vsrab, 2, 12);
6584 GEN_VXFORM(vsrah, 2, 13);
6585 GEN_VXFORM(vsraw, 2, 14);
6586 GEN_VXFORM(vslo, 6, 16);
6587 GEN_VXFORM(vsro, 6, 17);
6588 GEN_VXFORM(vaddcuw, 0, 6);
6589 GEN_VXFORM(vsubcuw, 0, 22);
6590 GEN_VXFORM_ENV(vaddubs, 0, 8);
6591 GEN_VXFORM_ENV(vadduhs, 0, 9);
6592 GEN_VXFORM_ENV(vadduws, 0, 10);
6593 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6594 GEN_VXFORM_ENV(vaddshs, 0, 13);
6595 GEN_VXFORM_ENV(vaddsws, 0, 14);
6596 GEN_VXFORM_ENV(vsububs, 0, 24);
6597 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6598 GEN_VXFORM_ENV(vsubuws, 0, 26);
6599 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6600 GEN_VXFORM_ENV(vsubshs, 0, 29);
6601 GEN_VXFORM_ENV(vsubsws, 0, 30);
6602 GEN_VXFORM(vrlb, 2, 0);
6603 GEN_VXFORM(vrlh, 2, 1);
6604 GEN_VXFORM(vrlw, 2, 2);
6605 GEN_VXFORM(vsl, 2, 7);
6606 GEN_VXFORM(vsr, 2, 11);
6607 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6608 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6609 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6610 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6611 GEN_VXFORM_ENV(vpkshus, 7, 4);
6612 GEN_VXFORM_ENV(vpkswus, 7, 5);
6613 GEN_VXFORM_ENV(vpkshss, 7, 6);
6614 GEN_VXFORM_ENV(vpkswss, 7, 7);
6615 GEN_VXFORM(vpkpx, 7, 12);
6616 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6617 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6618 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6619 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6620 GEN_VXFORM_ENV(vsumsws, 4, 30);
6621 GEN_VXFORM_ENV(vaddfp, 5, 0);
6622 GEN_VXFORM_ENV(vsubfp, 5, 1);
6623 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6624 GEN_VXFORM_ENV(vminfp, 5, 17);
6625
6626 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6627 static void glue(gen_, name)(DisasContext *ctx) \
6628 { \
6629 TCGv_ptr ra, rb, rd; \
6630 if (unlikely(!ctx->altivec_enabled)) { \
6631 gen_exception(ctx, POWERPC_EXCP_VPU); \
6632 return; \
6633 } \
6634 ra = gen_avr_ptr(rA(ctx->opcode)); \
6635 rb = gen_avr_ptr(rB(ctx->opcode)); \
6636 rd = gen_avr_ptr(rD(ctx->opcode)); \
6637 gen_helper_##opname(cpu_env, rd, ra, rb); \
6638 tcg_temp_free_ptr(ra); \
6639 tcg_temp_free_ptr(rb); \
6640 tcg_temp_free_ptr(rd); \
6641 }
6642
6643 #define GEN_VXRFORM(name, opc2, opc3) \
6644 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6645 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6646
6647 GEN_VXRFORM(vcmpequb, 3, 0)
6648 GEN_VXRFORM(vcmpequh, 3, 1)
6649 GEN_VXRFORM(vcmpequw, 3, 2)
6650 GEN_VXRFORM(vcmpgtsb, 3, 12)
6651 GEN_VXRFORM(vcmpgtsh, 3, 13)
6652 GEN_VXRFORM(vcmpgtsw, 3, 14)
6653 GEN_VXRFORM(vcmpgtub, 3, 8)
6654 GEN_VXRFORM(vcmpgtuh, 3, 9)
6655 GEN_VXRFORM(vcmpgtuw, 3, 10)
6656 GEN_VXRFORM(vcmpeqfp, 3, 3)
6657 GEN_VXRFORM(vcmpgefp, 3, 7)
6658 GEN_VXRFORM(vcmpgtfp, 3, 11)
6659 GEN_VXRFORM(vcmpbfp, 3, 15)
6660
6661 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6662 static void glue(gen_, name)(DisasContext *ctx) \
6663 { \
6664 TCGv_ptr rd; \
6665 TCGv_i32 simm; \
6666 if (unlikely(!ctx->altivec_enabled)) { \
6667 gen_exception(ctx, POWERPC_EXCP_VPU); \
6668 return; \
6669 } \
6670 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6671 rd = gen_avr_ptr(rD(ctx->opcode)); \
6672 gen_helper_##name (rd, simm); \
6673 tcg_temp_free_i32(simm); \
6674 tcg_temp_free_ptr(rd); \
6675 }
6676
6677 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6678 GEN_VXFORM_SIMM(vspltish, 6, 13);
6679 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6680
6681 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6682 static void glue(gen_, name)(DisasContext *ctx) \
6683 { \
6684 TCGv_ptr rb, rd; \
6685 if (unlikely(!ctx->altivec_enabled)) { \
6686 gen_exception(ctx, POWERPC_EXCP_VPU); \
6687 return; \
6688 } \
6689 rb = gen_avr_ptr(rB(ctx->opcode)); \
6690 rd = gen_avr_ptr(rD(ctx->opcode)); \
6691 gen_helper_##name (rd, rb); \
6692 tcg_temp_free_ptr(rb); \
6693 tcg_temp_free_ptr(rd); \
6694 }
6695
6696 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6697 static void glue(gen_, name)(DisasContext *ctx) \
6698 { \
6699 TCGv_ptr rb, rd; \
6700 \
6701 if (unlikely(!ctx->altivec_enabled)) { \
6702 gen_exception(ctx, POWERPC_EXCP_VPU); \
6703 return; \
6704 } \
6705 rb = gen_avr_ptr(rB(ctx->opcode)); \
6706 rd = gen_avr_ptr(rD(ctx->opcode)); \
6707 gen_helper_##name(cpu_env, rd, rb); \
6708 tcg_temp_free_ptr(rb); \
6709 tcg_temp_free_ptr(rd); \
6710 }
6711
6712 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6713 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6714 GEN_VXFORM_NOA(vupklsb, 7, 10);
6715 GEN_VXFORM_NOA(vupklsh, 7, 11);
6716 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6717 GEN_VXFORM_NOA(vupklpx, 7, 15);
6718 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6719 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6720 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6721 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6722 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6723 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6724 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6725 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6726
6727 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6728 static void glue(gen_, name)(DisasContext *ctx) \
6729 { \
6730 TCGv_ptr rd; \
6731 TCGv_i32 simm; \
6732 if (unlikely(!ctx->altivec_enabled)) { \
6733 gen_exception(ctx, POWERPC_EXCP_VPU); \
6734 return; \
6735 } \
6736 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6737 rd = gen_avr_ptr(rD(ctx->opcode)); \
6738 gen_helper_##name (rd, simm); \
6739 tcg_temp_free_i32(simm); \
6740 tcg_temp_free_ptr(rd); \
6741 }
6742
6743 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6744 static void glue(gen_, name)(DisasContext *ctx) \
6745 { \
6746 TCGv_ptr rb, rd; \
6747 TCGv_i32 uimm; \
6748 if (unlikely(!ctx->altivec_enabled)) { \
6749 gen_exception(ctx, POWERPC_EXCP_VPU); \
6750 return; \
6751 } \
6752 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6753 rb = gen_avr_ptr(rB(ctx->opcode)); \
6754 rd = gen_avr_ptr(rD(ctx->opcode)); \
6755 gen_helper_##name (rd, rb, uimm); \
6756 tcg_temp_free_i32(uimm); \
6757 tcg_temp_free_ptr(rb); \
6758 tcg_temp_free_ptr(rd); \
6759 }
6760
6761 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6762 static void glue(gen_, name)(DisasContext *ctx) \
6763 { \
6764 TCGv_ptr rb, rd; \
6765 TCGv_i32 uimm; \
6766 \
6767 if (unlikely(!ctx->altivec_enabled)) { \
6768 gen_exception(ctx, POWERPC_EXCP_VPU); \
6769 return; \
6770 } \
6771 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6772 rb = gen_avr_ptr(rB(ctx->opcode)); \
6773 rd = gen_avr_ptr(rD(ctx->opcode)); \
6774 gen_helper_##name(cpu_env, rd, rb, uimm); \
6775 tcg_temp_free_i32(uimm); \
6776 tcg_temp_free_ptr(rb); \
6777 tcg_temp_free_ptr(rd); \
6778 }
6779
6780 GEN_VXFORM_UIMM(vspltb, 6, 8);
6781 GEN_VXFORM_UIMM(vsplth, 6, 9);
6782 GEN_VXFORM_UIMM(vspltw, 6, 10);
6783 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6784 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6785 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6786 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6787
6788 static void gen_vsldoi(DisasContext *ctx)
6789 {
6790 TCGv_ptr ra, rb, rd;
6791 TCGv_i32 sh;
6792 if (unlikely(!ctx->altivec_enabled)) {
6793 gen_exception(ctx, POWERPC_EXCP_VPU);
6794 return;
6795 }
6796 ra = gen_avr_ptr(rA(ctx->opcode));
6797 rb = gen_avr_ptr(rB(ctx->opcode));
6798 rd = gen_avr_ptr(rD(ctx->opcode));
6799 sh = tcg_const_i32(VSH(ctx->opcode));
6800 gen_helper_vsldoi (rd, ra, rb, sh);
6801 tcg_temp_free_ptr(ra);
6802 tcg_temp_free_ptr(rb);
6803 tcg_temp_free_ptr(rd);
6804 tcg_temp_free_i32(sh);
6805 }
6806
6807 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6808 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6809 { \
6810 TCGv_ptr ra, rb, rc, rd; \
6811 if (unlikely(!ctx->altivec_enabled)) { \
6812 gen_exception(ctx, POWERPC_EXCP_VPU); \
6813 return; \
6814 } \
6815 ra = gen_avr_ptr(rA(ctx->opcode)); \
6816 rb = gen_avr_ptr(rB(ctx->opcode)); \
6817 rc = gen_avr_ptr(rC(ctx->opcode)); \
6818 rd = gen_avr_ptr(rD(ctx->opcode)); \
6819 if (Rc(ctx->opcode)) { \
6820 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6821 } else { \
6822 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6823 } \
6824 tcg_temp_free_ptr(ra); \
6825 tcg_temp_free_ptr(rb); \
6826 tcg_temp_free_ptr(rc); \
6827 tcg_temp_free_ptr(rd); \
6828 }
6829
6830 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6831
6832 static void gen_vmladduhm(DisasContext *ctx)
6833 {
6834 TCGv_ptr ra, rb, rc, rd;
6835 if (unlikely(!ctx->altivec_enabled)) {
6836 gen_exception(ctx, POWERPC_EXCP_VPU);
6837 return;
6838 }
6839 ra = gen_avr_ptr(rA(ctx->opcode));
6840 rb = gen_avr_ptr(rB(ctx->opcode));
6841 rc = gen_avr_ptr(rC(ctx->opcode));
6842 rd = gen_avr_ptr(rD(ctx->opcode));
6843 gen_helper_vmladduhm(rd, ra, rb, rc);
6844 tcg_temp_free_ptr(ra);
6845 tcg_temp_free_ptr(rb);
6846 tcg_temp_free_ptr(rc);
6847 tcg_temp_free_ptr(rd);
6848 }
6849
6850 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6851 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6852 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6853 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6854 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6855
6856 /*** SPE extension ***/
6857 /* Register moves */
6858
6859
6860 static inline void gen_evmra(DisasContext *ctx)
6861 {
6862
6863 if (unlikely(!ctx->spe_enabled)) {
6864 gen_exception(ctx, POWERPC_EXCP_SPEU);
6865 return;
6866 }
6867
6868 #if defined(TARGET_PPC64)
6869 /* rD := rA */
6870 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6871
6872 /* spe_acc := rA */
6873 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6874 cpu_env,
6875 offsetof(CPUPPCState, spe_acc));
6876 #else
6877 TCGv_i64 tmp = tcg_temp_new_i64();
6878
6879 /* tmp := rA_lo + rA_hi << 32 */
6880 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6881
6882 /* spe_acc := tmp */
6883 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6884 tcg_temp_free_i64(tmp);
6885
6886 /* rD := rA */
6887 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6888 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6889 #endif
6890 }
6891
6892 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6893 {
6894 #if defined(TARGET_PPC64)
6895 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6896 #else
6897 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6898 #endif
6899 }
6900
6901 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6902 {
6903 #if defined(TARGET_PPC64)
6904 tcg_gen_mov_i64(cpu_gpr[reg], t);
6905 #else
6906 TCGv_i64 tmp = tcg_temp_new_i64();
6907 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6908 tcg_gen_shri_i64(tmp, t, 32);
6909 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6910 tcg_temp_free_i64(tmp);
6911 #endif
6912 }
6913
6914 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6915 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6916 { \
6917 if (Rc(ctx->opcode)) \
6918 gen_##name1(ctx); \
6919 else \
6920 gen_##name0(ctx); \
6921 }
6922
6923 /* Handler for undefined SPE opcodes */
6924 static inline void gen_speundef(DisasContext *ctx)
6925 {
6926 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6927 }
6928
6929 /* SPE logic */
6930 #if defined(TARGET_PPC64)
6931 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6932 static inline void gen_##name(DisasContext *ctx) \
6933 { \
6934 if (unlikely(!ctx->spe_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6936 return; \
6937 } \
6938 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6939 cpu_gpr[rB(ctx->opcode)]); \
6940 }
6941 #else
6942 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6943 static inline void gen_##name(DisasContext *ctx) \
6944 { \
6945 if (unlikely(!ctx->spe_enabled)) { \
6946 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6947 return; \
6948 } \
6949 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6950 cpu_gpr[rB(ctx->opcode)]); \
6951 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6952 cpu_gprh[rB(ctx->opcode)]); \
6953 }
6954 #endif
6955
6956 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6957 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6958 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6959 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6960 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6961 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6962 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6963 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6964
6965 /* SPE logic immediate */
6966 #if defined(TARGET_PPC64)
6967 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6968 static inline void gen_##name(DisasContext *ctx) \
6969 { \
6970 if (unlikely(!ctx->spe_enabled)) { \
6971 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6972 return; \
6973 } \
6974 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6975 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6976 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6977 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6978 tcg_opi(t0, t0, rB(ctx->opcode)); \
6979 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6980 tcg_gen_trunc_i64_i32(t1, t2); \
6981 tcg_temp_free_i64(t2); \
6982 tcg_opi(t1, t1, rB(ctx->opcode)); \
6983 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6984 tcg_temp_free_i32(t0); \
6985 tcg_temp_free_i32(t1); \
6986 }
6987 #else
6988 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6989 static inline void gen_##name(DisasContext *ctx) \
6990 { \
6991 if (unlikely(!ctx->spe_enabled)) { \
6992 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6993 return; \
6994 } \
6995 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6996 rB(ctx->opcode)); \
6997 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6998 rB(ctx->opcode)); \
6999 }
7000 #endif
7001 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7002 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7003 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7004 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7005
7006 /* SPE arithmetic */
7007 #if defined(TARGET_PPC64)
7008 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7009 static inline void gen_##name(DisasContext *ctx) \
7010 { \
7011 if (unlikely(!ctx->spe_enabled)) { \
7012 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7013 return; \
7014 } \
7015 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7016 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7017 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7018 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7019 tcg_op(t0, t0); \
7020 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7021 tcg_gen_trunc_i64_i32(t1, t2); \
7022 tcg_temp_free_i64(t2); \
7023 tcg_op(t1, t1); \
7024 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7025 tcg_temp_free_i32(t0); \
7026 tcg_temp_free_i32(t1); \
7027 }
7028 #else
7029 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7030 static inline void gen_##name(DisasContext *ctx) \
7031 { \
7032 if (unlikely(!ctx->spe_enabled)) { \
7033 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7034 return; \
7035 } \
7036 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7037 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7038 }
7039 #endif
7040
7041 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7042 {
7043 int l1 = gen_new_label();
7044 int l2 = gen_new_label();
7045
7046 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7047 tcg_gen_neg_i32(ret, arg1);
7048 tcg_gen_br(l2);
7049 gen_set_label(l1);
7050 tcg_gen_mov_i32(ret, arg1);
7051 gen_set_label(l2);
7052 }
7053 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7054 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7055 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7056 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7057 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7058 {
7059 tcg_gen_addi_i32(ret, arg1, 0x8000);
7060 tcg_gen_ext16u_i32(ret, ret);
7061 }
7062 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7063 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7064 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7065
7066 #if defined(TARGET_PPC64)
7067 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7068 static inline void gen_##name(DisasContext *ctx) \
7069 { \
7070 if (unlikely(!ctx->spe_enabled)) { \
7071 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7072 return; \
7073 } \
7074 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7075 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7076 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7077 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7078 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7079 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7080 tcg_op(t0, t0, t2); \
7081 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7082 tcg_gen_trunc_i64_i32(t1, t3); \
7083 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7084 tcg_gen_trunc_i64_i32(t2, t3); \
7085 tcg_temp_free_i64(t3); \
7086 tcg_op(t1, t1, t2); \
7087 tcg_temp_free_i32(t2); \
7088 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7089 tcg_temp_free_i32(t0); \
7090 tcg_temp_free_i32(t1); \
7091 }
7092 #else
7093 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7094 static inline void gen_##name(DisasContext *ctx) \
7095 { \
7096 if (unlikely(!ctx->spe_enabled)) { \
7097 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7098 return; \
7099 } \
7100 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7101 cpu_gpr[rB(ctx->opcode)]); \
7102 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7103 cpu_gprh[rB(ctx->opcode)]); \
7104 }
7105 #endif
7106
7107 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7108 {
7109 TCGv_i32 t0;
7110 int l1, l2;
7111
7112 l1 = gen_new_label();
7113 l2 = gen_new_label();
7114 t0 = tcg_temp_local_new_i32();
7115 /* No error here: 6 bits are used */
7116 tcg_gen_andi_i32(t0, arg2, 0x3F);
7117 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7118 tcg_gen_shr_i32(ret, arg1, t0);
7119 tcg_gen_br(l2);
7120 gen_set_label(l1);
7121 tcg_gen_movi_i32(ret, 0);
7122 gen_set_label(l2);
7123 tcg_temp_free_i32(t0);
7124 }
7125 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7126 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7127 {
7128 TCGv_i32 t0;
7129 int l1, l2;
7130
7131 l1 = gen_new_label();
7132 l2 = gen_new_label();
7133 t0 = tcg_temp_local_new_i32();
7134 /* No error here: 6 bits are used */
7135 tcg_gen_andi_i32(t0, arg2, 0x3F);
7136 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7137 tcg_gen_sar_i32(ret, arg1, t0);
7138 tcg_gen_br(l2);
7139 gen_set_label(l1);
7140 tcg_gen_movi_i32(ret, 0);
7141 gen_set_label(l2);
7142 tcg_temp_free_i32(t0);
7143 }
7144 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7145 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7146 {
7147 TCGv_i32 t0;
7148 int l1, l2;
7149
7150 l1 = gen_new_label();
7151 l2 = gen_new_label();
7152 t0 = tcg_temp_local_new_i32();
7153 /* No error here: 6 bits are used */
7154 tcg_gen_andi_i32(t0, arg2, 0x3F);
7155 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7156 tcg_gen_shl_i32(ret, arg1, t0);
7157 tcg_gen_br(l2);
7158 gen_set_label(l1);
7159 tcg_gen_movi_i32(ret, 0);
7160 gen_set_label(l2);
7161 tcg_temp_free_i32(t0);
7162 }
7163 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7164 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7165 {
7166 TCGv_i32 t0 = tcg_temp_new_i32();
7167 tcg_gen_andi_i32(t0, arg2, 0x1F);
7168 tcg_gen_rotl_i32(ret, arg1, t0);
7169 tcg_temp_free_i32(t0);
7170 }
7171 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7172 static inline void gen_evmergehi(DisasContext *ctx)
7173 {
7174 if (unlikely(!ctx->spe_enabled)) {
7175 gen_exception(ctx, POWERPC_EXCP_SPEU);
7176 return;
7177 }
7178 #if defined(TARGET_PPC64)
7179 TCGv t0 = tcg_temp_new();
7180 TCGv t1 = tcg_temp_new();
7181 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7182 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7183 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7184 tcg_temp_free(t0);
7185 tcg_temp_free(t1);
7186 #else
7187 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7188 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7189 #endif
7190 }
7191 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7192 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7193 {
7194 tcg_gen_sub_i32(ret, arg2, arg1);
7195 }
7196 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7197
7198 /* SPE arithmetic immediate */
7199 #if defined(TARGET_PPC64)
7200 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7201 static inline void gen_##name(DisasContext *ctx) \
7202 { \
7203 if (unlikely(!ctx->spe_enabled)) { \
7204 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7205 return; \
7206 } \
7207 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7208 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7209 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7210 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7211 tcg_op(t0, t0, rA(ctx->opcode)); \
7212 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7213 tcg_gen_trunc_i64_i32(t1, t2); \
7214 tcg_temp_free_i64(t2); \
7215 tcg_op(t1, t1, rA(ctx->opcode)); \
7216 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7217 tcg_temp_free_i32(t0); \
7218 tcg_temp_free_i32(t1); \
7219 }
7220 #else
7221 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7222 static inline void gen_##name(DisasContext *ctx) \
7223 { \
7224 if (unlikely(!ctx->spe_enabled)) { \
7225 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7226 return; \
7227 } \
7228 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7229 rA(ctx->opcode)); \
7230 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7231 rA(ctx->opcode)); \
7232 }
7233 #endif
7234 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7235 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7236
7237 /* SPE comparison */
7238 #if defined(TARGET_PPC64)
7239 #define GEN_SPEOP_COMP(name, tcg_cond) \
7240 static inline void gen_##name(DisasContext *ctx) \
7241 { \
7242 if (unlikely(!ctx->spe_enabled)) { \
7243 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7244 return; \
7245 } \
7246 int l1 = gen_new_label(); \
7247 int l2 = gen_new_label(); \
7248 int l3 = gen_new_label(); \
7249 int l4 = gen_new_label(); \
7250 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7251 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7252 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7253 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7254 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7255 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7256 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7257 tcg_gen_br(l2); \
7258 gen_set_label(l1); \
7259 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7260 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7261 gen_set_label(l2); \
7262 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7263 tcg_gen_trunc_i64_i32(t0, t2); \
7264 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7265 tcg_gen_trunc_i64_i32(t1, t2); \
7266 tcg_temp_free_i64(t2); \
7267 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7268 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7269 ~(CRF_CH | CRF_CH_AND_CL)); \
7270 tcg_gen_br(l4); \
7271 gen_set_label(l3); \
7272 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7273 CRF_CH | CRF_CH_OR_CL); \
7274 gen_set_label(l4); \
7275 tcg_temp_free_i32(t0); \
7276 tcg_temp_free_i32(t1); \
7277 }
7278 #else
7279 #define GEN_SPEOP_COMP(name, tcg_cond) \
7280 static inline void gen_##name(DisasContext *ctx) \
7281 { \
7282 if (unlikely(!ctx->spe_enabled)) { \
7283 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7284 return; \
7285 } \
7286 int l1 = gen_new_label(); \
7287 int l2 = gen_new_label(); \
7288 int l3 = gen_new_label(); \
7289 int l4 = gen_new_label(); \
7290 \
7291 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7292 cpu_gpr[rB(ctx->opcode)], l1); \
7293 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7294 tcg_gen_br(l2); \
7295 gen_set_label(l1); \
7296 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7297 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7298 gen_set_label(l2); \
7299 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7300 cpu_gprh[rB(ctx->opcode)], l3); \
7301 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7302 ~(CRF_CH | CRF_CH_AND_CL)); \
7303 tcg_gen_br(l4); \
7304 gen_set_label(l3); \
7305 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7306 CRF_CH | CRF_CH_OR_CL); \
7307 gen_set_label(l4); \
7308 }
7309 #endif
7310 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7311 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7312 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7313 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7314 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7315
7316 /* SPE misc */
7317 static inline void gen_brinc(DisasContext *ctx)
7318 {
7319 /* Note: brinc is usable even if SPE is disabled */
7320 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7321 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7322 }
7323 static inline void gen_evmergelo(DisasContext *ctx)
7324 {
7325 if (unlikely(!ctx->spe_enabled)) {
7326 gen_exception(ctx, POWERPC_EXCP_SPEU);
7327 return;
7328 }
7329 #if defined(TARGET_PPC64)
7330 TCGv t0 = tcg_temp_new();
7331 TCGv t1 = tcg_temp_new();
7332 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7333 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7334 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7335 tcg_temp_free(t0);
7336 tcg_temp_free(t1);
7337 #else
7338 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7339 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7340 #endif
7341 }
7342 static inline void gen_evmergehilo(DisasContext *ctx)
7343 {
7344 if (unlikely(!ctx->spe_enabled)) {
7345 gen_exception(ctx, POWERPC_EXCP_SPEU);
7346 return;
7347 }
7348 #if defined(TARGET_PPC64)
7349 TCGv t0 = tcg_temp_new();
7350 TCGv t1 = tcg_temp_new();
7351 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7352 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7353 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7354 tcg_temp_free(t0);
7355 tcg_temp_free(t1);
7356 #else
7357 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7358 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7359 #endif
7360 }
7361 static inline void gen_evmergelohi(DisasContext *ctx)
7362 {
7363 if (unlikely(!ctx->spe_enabled)) {
7364 gen_exception(ctx, POWERPC_EXCP_SPEU);
7365 return;
7366 }
7367 #if defined(TARGET_PPC64)
7368 TCGv t0 = tcg_temp_new();
7369 TCGv t1 = tcg_temp_new();
7370 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7371 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7372 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7373 tcg_temp_free(t0);
7374 tcg_temp_free(t1);
7375 #else
7376 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7377 TCGv_i32 tmp = tcg_temp_new_i32();
7378 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7379 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7380 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7381 tcg_temp_free_i32(tmp);
7382 } else {
7383 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7384 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7385 }
7386 #endif
7387 }
7388 static inline void gen_evsplati(DisasContext *ctx)
7389 {
7390 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7391
7392 #if defined(TARGET_PPC64)
7393 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7394 #else
7395 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7396 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7397 #endif
7398 }
7399 static inline void gen_evsplatfi(DisasContext *ctx)
7400 {
7401 uint64_t imm = rA(ctx->opcode) << 27;
7402
7403 #if defined(TARGET_PPC64)
7404 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7405 #else
7406 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7407 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7408 #endif
7409 }
7410
7411 static inline void gen_evsel(DisasContext *ctx)
7412 {
7413 int l1 = gen_new_label();
7414 int l2 = gen_new_label();
7415 int l3 = gen_new_label();
7416 int l4 = gen_new_label();
7417 TCGv_i32 t0 = tcg_temp_local_new_i32();
7418 #if defined(TARGET_PPC64)
7419 TCGv t1 = tcg_temp_local_new();
7420 TCGv t2 = tcg_temp_local_new();
7421 #endif
7422 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7423 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7424 #if defined(TARGET_PPC64)
7425 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7426 #else
7427 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7428 #endif
7429 tcg_gen_br(l2);
7430 gen_set_label(l1);
7431 #if defined(TARGET_PPC64)
7432 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7433 #else
7434 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7435 #endif
7436 gen_set_label(l2);
7437 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7438 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7439 #if defined(TARGET_PPC64)
7440 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7441 #else
7442 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7443 #endif
7444 tcg_gen_br(l4);
7445 gen_set_label(l3);
7446 #if defined(TARGET_PPC64)
7447 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7448 #else
7449 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7450 #endif
7451 gen_set_label(l4);
7452 tcg_temp_free_i32(t0);
7453 #if defined(TARGET_PPC64)
7454 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7455 tcg_temp_free(t1);
7456 tcg_temp_free(t2);
7457 #endif
7458 }
7459
7460 static void gen_evsel0(DisasContext *ctx)
7461 {
7462 gen_evsel(ctx);
7463 }
7464
7465 static void gen_evsel1(DisasContext *ctx)
7466 {
7467 gen_evsel(ctx);
7468 }
7469
7470 static void gen_evsel2(DisasContext *ctx)
7471 {
7472 gen_evsel(ctx);
7473 }
7474
7475 static void gen_evsel3(DisasContext *ctx)
7476 {
7477 gen_evsel(ctx);
7478 }
7479
7480 /* Multiply */
7481
7482 static inline void gen_evmwumi(DisasContext *ctx)
7483 {
7484 TCGv_i64 t0, t1;
7485
7486 if (unlikely(!ctx->spe_enabled)) {
7487 gen_exception(ctx, POWERPC_EXCP_SPEU);
7488 return;
7489 }
7490
7491 t0 = tcg_temp_new_i64();
7492 t1 = tcg_temp_new_i64();
7493
7494 /* t0 := rA; t1 := rB */
7495 #if defined(TARGET_PPC64)
7496 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7497 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7498 #else
7499 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7500 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7501 #endif
7502
7503 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7504
7505 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7506
7507 tcg_temp_free_i64(t0);
7508 tcg_temp_free_i64(t1);
7509 }
7510
7511 static inline void gen_evmwumia(DisasContext *ctx)
7512 {
7513 TCGv_i64 tmp;
7514
7515 if (unlikely(!ctx->spe_enabled)) {
7516 gen_exception(ctx, POWERPC_EXCP_SPEU);
7517 return;
7518 }
7519
7520 gen_evmwumi(ctx); /* rD := rA * rB */
7521
7522 tmp = tcg_temp_new_i64();
7523
7524 /* acc := rD */
7525 gen_load_gpr64(tmp, rD(ctx->opcode));
7526 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7527 tcg_temp_free_i64(tmp);
7528 }
7529
7530 static inline void gen_evmwumiaa(DisasContext *ctx)
7531 {
7532 TCGv_i64 acc;
7533 TCGv_i64 tmp;
7534
7535 if (unlikely(!ctx->spe_enabled)) {
7536 gen_exception(ctx, POWERPC_EXCP_SPEU);
7537 return;
7538 }
7539
7540 gen_evmwumi(ctx); /* rD := rA * rB */
7541
7542 acc = tcg_temp_new_i64();
7543 tmp = tcg_temp_new_i64();
7544
7545 /* tmp := rD */
7546 gen_load_gpr64(tmp, rD(ctx->opcode));
7547
7548 /* Load acc */
7549 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7550
7551 /* acc := tmp + acc */
7552 tcg_gen_add_i64(acc, acc, tmp);
7553
7554 /* Store acc */
7555 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7556
7557 /* rD := acc */
7558 gen_store_gpr64(rD(ctx->opcode), acc);
7559
7560 tcg_temp_free_i64(acc);
7561 tcg_temp_free_i64(tmp);
7562 }
7563
7564 static inline void gen_evmwsmi(DisasContext *ctx)
7565 {
7566 TCGv_i64 t0, t1;
7567
7568 if (unlikely(!ctx->spe_enabled)) {
7569 gen_exception(ctx, POWERPC_EXCP_SPEU);
7570 return;
7571 }
7572
7573 t0 = tcg_temp_new_i64();
7574 t1 = tcg_temp_new_i64();
7575
7576 /* t0 := rA; t1 := rB */
7577 #if defined(TARGET_PPC64)
7578 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7579 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7580 #else
7581 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7582 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7583 #endif
7584
7585 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7586
7587 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7588
7589 tcg_temp_free_i64(t0);
7590 tcg_temp_free_i64(t1);
7591 }
7592
7593 static inline void gen_evmwsmia(DisasContext *ctx)
7594 {
7595 TCGv_i64 tmp;
7596
7597 gen_evmwsmi(ctx); /* rD := rA * rB */
7598
7599 tmp = tcg_temp_new_i64();
7600
7601 /* acc := rD */
7602 gen_load_gpr64(tmp, rD(ctx->opcode));
7603 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7604
7605 tcg_temp_free_i64(tmp);
7606 }
7607
7608 static inline void gen_evmwsmiaa(DisasContext *ctx)
7609 {
7610 TCGv_i64 acc = tcg_temp_new_i64();
7611 TCGv_i64 tmp = tcg_temp_new_i64();
7612
7613 gen_evmwsmi(ctx); /* rD := rA * rB */
7614
7615 acc = tcg_temp_new_i64();
7616 tmp = tcg_temp_new_i64();
7617
7618 /* tmp := rD */
7619 gen_load_gpr64(tmp, rD(ctx->opcode));
7620
7621 /* Load acc */
7622 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7623
7624 /* acc := tmp + acc */
7625 tcg_gen_add_i64(acc, acc, tmp);
7626
7627 /* Store acc */
7628 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7629
7630 /* rD := acc */
7631 gen_store_gpr64(rD(ctx->opcode), acc);
7632
7633 tcg_temp_free_i64(acc);
7634 tcg_temp_free_i64(tmp);
7635 }
7636
7637 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7638 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7639 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7640 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7641 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7642 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7643 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7644 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7645 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7646 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7647 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7648 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7649 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7650 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7651 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7652 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7653 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7654 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7655 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7656 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7657 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7658 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7659 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7660 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7661 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7662 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7663 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7664 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7665 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7666
7667 /* SPE load and stores */
7668 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7669 {
7670 target_ulong uimm = rB(ctx->opcode);
7671
7672 if (rA(ctx->opcode) == 0) {
7673 tcg_gen_movi_tl(EA, uimm << sh);
7674 } else {
7675 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7676 #if defined(TARGET_PPC64)
7677 if (!ctx->sf_mode) {
7678 tcg_gen_ext32u_tl(EA, EA);
7679 }
7680 #endif
7681 }
7682 }
7683
7684 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7685 {
7686 #if defined(TARGET_PPC64)
7687 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7688 #else
7689 TCGv_i64 t0 = tcg_temp_new_i64();
7690 gen_qemu_ld64(ctx, t0, addr);
7691 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7692 tcg_gen_shri_i64(t0, t0, 32);
7693 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7694 tcg_temp_free_i64(t0);
7695 #endif
7696 }
7697
7698 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7699 {
7700 #if defined(TARGET_PPC64)
7701 TCGv t0 = tcg_temp_new();
7702 gen_qemu_ld32u(ctx, t0, addr);
7703 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7704 gen_addr_add(ctx, addr, addr, 4);
7705 gen_qemu_ld32u(ctx, t0, addr);
7706 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7707 tcg_temp_free(t0);
7708 #else
7709 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7710 gen_addr_add(ctx, addr, addr, 4);
7711 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7712 #endif
7713 }
7714
7715 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7716 {
7717 TCGv t0 = tcg_temp_new();
7718 #if defined(TARGET_PPC64)
7719 gen_qemu_ld16u(ctx, t0, addr);
7720 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7721 gen_addr_add(ctx, addr, addr, 2);
7722 gen_qemu_ld16u(ctx, t0, addr);
7723 tcg_gen_shli_tl(t0, t0, 32);
7724 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7725 gen_addr_add(ctx, addr, addr, 2);
7726 gen_qemu_ld16u(ctx, t0, addr);
7727 tcg_gen_shli_tl(t0, t0, 16);
7728 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7729 gen_addr_add(ctx, addr, addr, 2);
7730 gen_qemu_ld16u(ctx, t0, addr);
7731 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7732 #else
7733 gen_qemu_ld16u(ctx, t0, addr);
7734 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7735 gen_addr_add(ctx, addr, addr, 2);
7736 gen_qemu_ld16u(ctx, t0, addr);
7737 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7738 gen_addr_add(ctx, addr, addr, 2);
7739 gen_qemu_ld16u(ctx, t0, addr);
7740 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7741 gen_addr_add(ctx, addr, addr, 2);
7742 gen_qemu_ld16u(ctx, t0, addr);
7743 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7744 #endif
7745 tcg_temp_free(t0);
7746 }
7747
7748 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7749 {
7750 TCGv t0 = tcg_temp_new();
7751 gen_qemu_ld16u(ctx, t0, addr);
7752 #if defined(TARGET_PPC64)
7753 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7754 tcg_gen_shli_tl(t0, t0, 16);
7755 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7756 #else
7757 tcg_gen_shli_tl(t0, t0, 16);
7758 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7760 #endif
7761 tcg_temp_free(t0);
7762 }
7763
7764 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7765 {
7766 TCGv t0 = tcg_temp_new();
7767 gen_qemu_ld16u(ctx, t0, addr);
7768 #if defined(TARGET_PPC64)
7769 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7770 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7771 #else
7772 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7774 #endif
7775 tcg_temp_free(t0);
7776 }
7777
7778 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7779 {
7780 TCGv t0 = tcg_temp_new();
7781 gen_qemu_ld16s(ctx, t0, addr);
7782 #if defined(TARGET_PPC64)
7783 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7784 tcg_gen_ext32u_tl(t0, t0);
7785 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7786 #else
7787 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7788 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7789 #endif
7790 tcg_temp_free(t0);
7791 }
7792
7793 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7794 {
7795 TCGv t0 = tcg_temp_new();
7796 #if defined(TARGET_PPC64)
7797 gen_qemu_ld16u(ctx, t0, addr);
7798 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7799 gen_addr_add(ctx, addr, addr, 2);
7800 gen_qemu_ld16u(ctx, t0, addr);
7801 tcg_gen_shli_tl(t0, t0, 16);
7802 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7803 #else
7804 gen_qemu_ld16u(ctx, t0, addr);
7805 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7806 gen_addr_add(ctx, addr, addr, 2);
7807 gen_qemu_ld16u(ctx, t0, addr);
7808 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7809 #endif
7810 tcg_temp_free(t0);
7811 }
7812
7813 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7814 {
7815 #if defined(TARGET_PPC64)
7816 TCGv t0 = tcg_temp_new();
7817 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7818 gen_addr_add(ctx, addr, addr, 2);
7819 gen_qemu_ld16u(ctx, t0, addr);
7820 tcg_gen_shli_tl(t0, t0, 32);
7821 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7822 tcg_temp_free(t0);
7823 #else
7824 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7825 gen_addr_add(ctx, addr, addr, 2);
7826 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7827 #endif
7828 }
7829
7830 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7831 {
7832 #if defined(TARGET_PPC64)
7833 TCGv t0 = tcg_temp_new();
7834 gen_qemu_ld16s(ctx, t0, addr);
7835 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7836 gen_addr_add(ctx, addr, addr, 2);
7837 gen_qemu_ld16s(ctx, t0, addr);
7838 tcg_gen_shli_tl(t0, t0, 32);
7839 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7840 tcg_temp_free(t0);
7841 #else
7842 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7843 gen_addr_add(ctx, addr, addr, 2);
7844 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7845 #endif
7846 }
7847
7848 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7849 {
7850 TCGv t0 = tcg_temp_new();
7851 gen_qemu_ld32u(ctx, t0, addr);
7852 #if defined(TARGET_PPC64)
7853 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7854 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7855 #else
7856 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7857 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7858 #endif
7859 tcg_temp_free(t0);
7860 }
7861
7862 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7863 {
7864 TCGv t0 = tcg_temp_new();
7865 #if defined(TARGET_PPC64)
7866 gen_qemu_ld16u(ctx, t0, addr);
7867 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7868 tcg_gen_shli_tl(t0, t0, 32);
7869 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7870 gen_addr_add(ctx, addr, addr, 2);
7871 gen_qemu_ld16u(ctx, t0, addr);
7872 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7873 tcg_gen_shli_tl(t0, t0, 16);
7874 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7875 #else
7876 gen_qemu_ld16u(ctx, t0, addr);
7877 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7878 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7879 gen_addr_add(ctx, addr, addr, 2);
7880 gen_qemu_ld16u(ctx, t0, addr);
7881 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7882 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7883 #endif
7884 tcg_temp_free(t0);
7885 }
7886
7887 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7888 {
7889 #if defined(TARGET_PPC64)
7890 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7891 #else
7892 TCGv_i64 t0 = tcg_temp_new_i64();
7893 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7894 gen_qemu_st64(ctx, t0, addr);
7895 tcg_temp_free_i64(t0);
7896 #endif
7897 }
7898
7899 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7900 {
7901 #if defined(TARGET_PPC64)
7902 TCGv t0 = tcg_temp_new();
7903 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7904 gen_qemu_st32(ctx, t0, addr);
7905 tcg_temp_free(t0);
7906 #else
7907 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7908 #endif
7909 gen_addr_add(ctx, addr, addr, 4);
7910 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7911 }
7912
7913 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7914 {
7915 TCGv t0 = tcg_temp_new();
7916 #if defined(TARGET_PPC64)
7917 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7918 #else
7919 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7920 #endif
7921 gen_qemu_st16(ctx, t0, addr);
7922 gen_addr_add(ctx, addr, addr, 2);
7923 #if defined(TARGET_PPC64)
7924 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7925 gen_qemu_st16(ctx, t0, addr);
7926 #else
7927 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7928 #endif
7929 gen_addr_add(ctx, addr, addr, 2);
7930 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7931 gen_qemu_st16(ctx, t0, addr);
7932 tcg_temp_free(t0);
7933 gen_addr_add(ctx, addr, addr, 2);
7934 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7935 }
7936
7937 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7938 {
7939 TCGv t0 = tcg_temp_new();
7940 #if defined(TARGET_PPC64)
7941 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7942 #else
7943 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7944 #endif
7945 gen_qemu_st16(ctx, t0, addr);
7946 gen_addr_add(ctx, addr, addr, 2);
7947 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7948 gen_qemu_st16(ctx, t0, addr);
7949 tcg_temp_free(t0);
7950 }
7951
7952 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7953 {
7954 #if defined(TARGET_PPC64)
7955 TCGv t0 = tcg_temp_new();
7956 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7957 gen_qemu_st16(ctx, t0, addr);
7958 tcg_temp_free(t0);
7959 #else
7960 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7961 #endif
7962 gen_addr_add(ctx, addr, addr, 2);
7963 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7964 }
7965
7966 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7967 {
7968 #if defined(TARGET_PPC64)
7969 TCGv t0 = tcg_temp_new();
7970 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7971 gen_qemu_st32(ctx, t0, addr);
7972 tcg_temp_free(t0);
7973 #else
7974 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7975 #endif
7976 }
7977
7978 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7979 {
7980 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7981 }
7982
7983 #define GEN_SPEOP_LDST(name, opc2, sh) \
7984 static void glue(gen_, name)(DisasContext *ctx) \
7985 { \
7986 TCGv t0; \
7987 if (unlikely(!ctx->spe_enabled)) { \
7988 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7989 return; \
7990 } \
7991 gen_set_access_type(ctx, ACCESS_INT); \
7992 t0 = tcg_temp_new(); \
7993 if (Rc(ctx->opcode)) { \
7994 gen_addr_spe_imm_index(ctx, t0, sh); \
7995 } else { \
7996 gen_addr_reg_index(ctx, t0); \
7997 } \
7998 gen_op_##name(ctx, t0); \
7999 tcg_temp_free(t0); \
8000 }
8001
8002 GEN_SPEOP_LDST(evldd, 0x00, 3);
8003 GEN_SPEOP_LDST(evldw, 0x01, 3);
8004 GEN_SPEOP_LDST(evldh, 0x02, 3);
8005 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8006 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8007 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8008 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8009 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8010 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8011 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8012 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8013
8014 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8015 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8016 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8017 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8018 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8019 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8020 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8021
8022 /* Multiply and add - TODO */
8023 #if 0
8024 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8025 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8026 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8027 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8028 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8029 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8030 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8031 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8032 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8033 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8034 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8035 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8036
8037 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8038 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8039 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8040 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8041 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8042 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8043 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8044 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8045 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8046 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8047 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8048 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8049
8050 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8051 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8052 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8053 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8054 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8055
8056 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8057 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8058 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8059 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8060 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8061 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8062 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8063 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8064 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8065 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8066 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8067 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8068
8069 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8070 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8071 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8072 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8073
8074 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8075 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8076 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8077 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8078 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8079 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8080 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8081 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8082 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8083 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8084 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8085 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8086
8087 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8088 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8089 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8090 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8091 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8092 #endif
8093
8094 /*** SPE floating-point extension ***/
8095 #if defined(TARGET_PPC64)
8096 #define GEN_SPEFPUOP_CONV_32_32(name) \
8097 static inline void gen_##name(DisasContext *ctx) \
8098 { \
8099 TCGv_i32 t0; \
8100 TCGv t1; \
8101 t0 = tcg_temp_new_i32(); \
8102 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8103 gen_helper_##name(t0, cpu_env, t0); \
8104 t1 = tcg_temp_new(); \
8105 tcg_gen_extu_i32_tl(t1, t0); \
8106 tcg_temp_free_i32(t0); \
8107 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8108 0xFFFFFFFF00000000ULL); \
8109 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8110 tcg_temp_free(t1); \
8111 }
8112 #define GEN_SPEFPUOP_CONV_32_64(name) \
8113 static inline void gen_##name(DisasContext *ctx) \
8114 { \
8115 TCGv_i32 t0; \
8116 TCGv t1; \
8117 t0 = tcg_temp_new_i32(); \
8118 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8119 t1 = tcg_temp_new(); \
8120 tcg_gen_extu_i32_tl(t1, t0); \
8121 tcg_temp_free_i32(t0); \
8122 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8123 0xFFFFFFFF00000000ULL); \
8124 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8125 tcg_temp_free(t1); \
8126 }
8127 #define GEN_SPEFPUOP_CONV_64_32(name) \
8128 static inline void gen_##name(DisasContext *ctx) \
8129 { \
8130 TCGv_i32 t0 = tcg_temp_new_i32(); \
8131 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8132 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8133 tcg_temp_free_i32(t0); \
8134 }
8135 #define GEN_SPEFPUOP_CONV_64_64(name) \
8136 static inline void gen_##name(DisasContext *ctx) \
8137 { \
8138 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8139 cpu_gpr[rB(ctx->opcode)]); \
8140 }
8141 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8142 static inline void gen_##name(DisasContext *ctx) \
8143 { \
8144 TCGv_i32 t0, t1; \
8145 TCGv_i64 t2; \
8146 if (unlikely(!ctx->spe_enabled)) { \
8147 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8148 return; \
8149 } \
8150 t0 = tcg_temp_new_i32(); \
8151 t1 = tcg_temp_new_i32(); \
8152 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8153 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8154 gen_helper_##name(t0, cpu_env, t0, t1); \
8155 tcg_temp_free_i32(t1); \
8156 t2 = tcg_temp_new(); \
8157 tcg_gen_extu_i32_tl(t2, t0); \
8158 tcg_temp_free_i32(t0); \
8159 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8160 0xFFFFFFFF00000000ULL); \
8161 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8162 tcg_temp_free(t2); \
8163 }
8164 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8165 static inline void gen_##name(DisasContext *ctx) \
8166 { \
8167 if (unlikely(!ctx->spe_enabled)) { \
8168 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8169 return; \
8170 } \
8171 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8172 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8173 }
8174 #define GEN_SPEFPUOP_COMP_32(name) \
8175 static inline void gen_##name(DisasContext *ctx) \
8176 { \
8177 TCGv_i32 t0, t1; \
8178 if (unlikely(!ctx->spe_enabled)) { \
8179 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8180 return; \
8181 } \
8182 t0 = tcg_temp_new_i32(); \
8183 t1 = tcg_temp_new_i32(); \
8184 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8185 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8186 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8187 tcg_temp_free_i32(t0); \
8188 tcg_temp_free_i32(t1); \
8189 }
8190 #define GEN_SPEFPUOP_COMP_64(name) \
8191 static inline void gen_##name(DisasContext *ctx) \
8192 { \
8193 if (unlikely(!ctx->spe_enabled)) { \
8194 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8195 return; \
8196 } \
8197 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8198 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8199 }
8200 #else
8201 #define GEN_SPEFPUOP_CONV_32_32(name) \
8202 static inline void gen_##name(DisasContext *ctx) \
8203 { \
8204 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8205 cpu_gpr[rB(ctx->opcode)]); \
8206 }
8207 #define GEN_SPEFPUOP_CONV_32_64(name) \
8208 static inline void gen_##name(DisasContext *ctx) \
8209 { \
8210 TCGv_i64 t0 = tcg_temp_new_i64(); \
8211 gen_load_gpr64(t0, rB(ctx->opcode)); \
8212 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8213 tcg_temp_free_i64(t0); \
8214 }
8215 #define GEN_SPEFPUOP_CONV_64_32(name) \
8216 static inline void gen_##name(DisasContext *ctx) \
8217 { \
8218 TCGv_i64 t0 = tcg_temp_new_i64(); \
8219 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8220 gen_store_gpr64(rD(ctx->opcode), t0); \
8221 tcg_temp_free_i64(t0); \
8222 }
8223 #define GEN_SPEFPUOP_CONV_64_64(name) \
8224 static inline void gen_##name(DisasContext *ctx) \
8225 { \
8226 TCGv_i64 t0 = tcg_temp_new_i64(); \
8227 gen_load_gpr64(t0, rB(ctx->opcode)); \
8228 gen_helper_##name(t0, cpu_env, t0); \
8229 gen_store_gpr64(rD(ctx->opcode), t0); \
8230 tcg_temp_free_i64(t0); \
8231 }
8232 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8233 static inline void gen_##name(DisasContext *ctx) \
8234 { \
8235 if (unlikely(!ctx->spe_enabled)) { \
8236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8237 return; \
8238 } \
8239 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8240 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8241 }
8242 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8243 static inline void gen_##name(DisasContext *ctx) \
8244 { \
8245 TCGv_i64 t0, t1; \
8246 if (unlikely(!ctx->spe_enabled)) { \
8247 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8248 return; \
8249 } \
8250 t0 = tcg_temp_new_i64(); \
8251 t1 = tcg_temp_new_i64(); \
8252 gen_load_gpr64(t0, rA(ctx->opcode)); \
8253 gen_load_gpr64(t1, rB(ctx->opcode)); \
8254 gen_helper_##name(t0, cpu_env, t0, t1); \
8255 gen_store_gpr64(rD(ctx->opcode), t0); \
8256 tcg_temp_free_i64(t0); \
8257 tcg_temp_free_i64(t1); \
8258 }
8259 #define GEN_SPEFPUOP_COMP_32(name) \
8260 static inline void gen_##name(DisasContext *ctx) \
8261 { \
8262 if (unlikely(!ctx->spe_enabled)) { \
8263 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8264 return; \
8265 } \
8266 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8267 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8268 }
8269 #define GEN_SPEFPUOP_COMP_64(name) \
8270 static inline void gen_##name(DisasContext *ctx) \
8271 { \
8272 TCGv_i64 t0, t1; \
8273 if (unlikely(!ctx->spe_enabled)) { \
8274 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8275 return; \
8276 } \
8277 t0 = tcg_temp_new_i64(); \
8278 t1 = tcg_temp_new_i64(); \
8279 gen_load_gpr64(t0, rA(ctx->opcode)); \
8280 gen_load_gpr64(t1, rB(ctx->opcode)); \
8281 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8282 tcg_temp_free_i64(t0); \
8283 tcg_temp_free_i64(t1); \
8284 }
8285 #endif
8286
8287 /* Single precision floating-point vectors operations */
8288 /* Arithmetic */
8289 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8290 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8291 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8292 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8293 static inline void gen_evfsabs(DisasContext *ctx)
8294 {
8295 if (unlikely(!ctx->spe_enabled)) {
8296 gen_exception(ctx, POWERPC_EXCP_SPEU);
8297 return;
8298 }
8299 #if defined(TARGET_PPC64)
8300 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8301 #else
8302 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8303 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8304 #endif
8305 }
8306 static inline void gen_evfsnabs(DisasContext *ctx)
8307 {
8308 if (unlikely(!ctx->spe_enabled)) {
8309 gen_exception(ctx, POWERPC_EXCP_SPEU);
8310 return;
8311 }
8312 #if defined(TARGET_PPC64)
8313 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8314 #else
8315 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8316 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8317 #endif
8318 }
8319 static inline void gen_evfsneg(DisasContext *ctx)
8320 {
8321 if (unlikely(!ctx->spe_enabled)) {
8322 gen_exception(ctx, POWERPC_EXCP_SPEU);
8323 return;
8324 }
8325 #if defined(TARGET_PPC64)
8326 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8327 #else
8328 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8329 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8330 #endif
8331 }
8332
8333 /* Conversion */
8334 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8335 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8336 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8337 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8338 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8339 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8340 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8341 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8342 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8343 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8344
8345 /* Comparison */
8346 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8347 GEN_SPEFPUOP_COMP_64(evfscmplt);
8348 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8349 GEN_SPEFPUOP_COMP_64(evfststgt);
8350 GEN_SPEFPUOP_COMP_64(evfststlt);
8351 GEN_SPEFPUOP_COMP_64(evfststeq);
8352
8353 /* Opcodes definitions */
8354 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8355 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8356 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8357 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8358 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8359 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8360 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8361 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8362 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8363 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8364 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8365 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8366 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8367 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8368
8369 /* Single precision floating-point operations */
8370 /* Arithmetic */
8371 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8372 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8373 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8374 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8375 static inline void gen_efsabs(DisasContext *ctx)
8376 {
8377 if (unlikely(!ctx->spe_enabled)) {
8378 gen_exception(ctx, POWERPC_EXCP_SPEU);
8379 return;
8380 }
8381 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8382 }
8383 static inline void gen_efsnabs(DisasContext *ctx)
8384 {
8385 if (unlikely(!ctx->spe_enabled)) {
8386 gen_exception(ctx, POWERPC_EXCP_SPEU);
8387 return;
8388 }
8389 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8390 }
8391 static inline void gen_efsneg(DisasContext *ctx)
8392 {
8393 if (unlikely(!ctx->spe_enabled)) {
8394 gen_exception(ctx, POWERPC_EXCP_SPEU);
8395 return;
8396 }
8397 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8398 }
8399
8400 /* Conversion */
8401 GEN_SPEFPUOP_CONV_32_32(efscfui);
8402 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8403 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8404 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8405 GEN_SPEFPUOP_CONV_32_32(efsctui);
8406 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8407 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8408 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8409 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8410 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8411 GEN_SPEFPUOP_CONV_32_64(efscfd);
8412
8413 /* Comparison */
8414 GEN_SPEFPUOP_COMP_32(efscmpgt);
8415 GEN_SPEFPUOP_COMP_32(efscmplt);
8416 GEN_SPEFPUOP_COMP_32(efscmpeq);
8417 GEN_SPEFPUOP_COMP_32(efststgt);
8418 GEN_SPEFPUOP_COMP_32(efststlt);
8419 GEN_SPEFPUOP_COMP_32(efststeq);
8420
8421 /* Opcodes definitions */
8422 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8423 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8424 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8425 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8426 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8427 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8428 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8429 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8430 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8431 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8432 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8433 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8434 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8435 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8436
8437 /* Double precision floating-point operations */
8438 /* Arithmetic */
8439 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8440 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8441 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8442 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8443 static inline void gen_efdabs(DisasContext *ctx)
8444 {
8445 if (unlikely(!ctx->spe_enabled)) {
8446 gen_exception(ctx, POWERPC_EXCP_SPEU);
8447 return;
8448 }
8449 #if defined(TARGET_PPC64)
8450 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8451 #else
8452 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8453 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8454 #endif
8455 }
8456 static inline void gen_efdnabs(DisasContext *ctx)
8457 {
8458 if (unlikely(!ctx->spe_enabled)) {
8459 gen_exception(ctx, POWERPC_EXCP_SPEU);
8460 return;
8461 }
8462 #if defined(TARGET_PPC64)
8463 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8464 #else
8465 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8466 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8467 #endif
8468 }
8469 static inline void gen_efdneg(DisasContext *ctx)
8470 {
8471 if (unlikely(!ctx->spe_enabled)) {
8472 gen_exception(ctx, POWERPC_EXCP_SPEU);
8473 return;
8474 }
8475 #if defined(TARGET_PPC64)
8476 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8477 #else
8478 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8479 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8480 #endif
8481 }
8482
8483 /* Conversion */
8484 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8485 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8486 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8487 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8488 GEN_SPEFPUOP_CONV_32_64(efdctui);
8489 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8490 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8491 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8492 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8493 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8494 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8495 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8496 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8497 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8498 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8499
8500 /* Comparison */
8501 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8502 GEN_SPEFPUOP_COMP_64(efdcmplt);
8503 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8504 GEN_SPEFPUOP_COMP_64(efdtstgt);
8505 GEN_SPEFPUOP_COMP_64(efdtstlt);
8506 GEN_SPEFPUOP_COMP_64(efdtsteq);
8507
8508 /* Opcodes definitions */
8509 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8510 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8511 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8512 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8513 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8514 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8515 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8516 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8517 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8518 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8519 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8520 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8521 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8522 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8523 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8524 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8525
8526 static opcode_t opcodes[] = {
8527 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8528 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8529 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8530 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8531 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8532 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8533 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8534 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8535 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8536 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8537 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8538 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8539 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8540 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8541 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8542 #if defined(TARGET_PPC64)
8543 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8544 #endif
8545 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8546 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8547 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8548 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8549 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8550 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8551 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8552 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8553 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8554 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8555 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8556 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8557 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8558 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8559 #if defined(TARGET_PPC64)
8560 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8561 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8562 #endif
8563 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8564 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8565 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8566 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8567 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8568 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8569 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8570 #if defined(TARGET_PPC64)
8571 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8572 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8573 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8574 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8575 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8576 #endif
8577 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8578 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8579 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8580 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8581 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8582 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8583 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8584 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8585 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8586 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8587 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8588 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8589 #if defined(TARGET_PPC64)
8590 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8591 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8592 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8593 #endif
8594 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8595 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8596 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8597 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8598 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8599 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8600 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8601 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8602 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8603 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8604 #if defined(TARGET_PPC64)
8605 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8606 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8607 #endif
8608 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8609 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8610 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8611 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8612 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8613 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8614 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8615 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8616 #if defined(TARGET_PPC64)
8617 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8618 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8619 #endif
8620 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8621 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8622 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8623 #if defined(TARGET_PPC64)
8624 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8625 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8626 #endif
8627 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8628 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8629 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8630 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8631 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8632 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8633 #if defined(TARGET_PPC64)
8634 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8635 #endif
8636 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8637 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8638 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8639 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8640 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8641 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8642 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8643 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8644 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8645 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8646 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8647 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8648 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8649 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8650 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8651 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8652 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8653 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8654 #if defined(TARGET_PPC64)
8655 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8656 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8657 PPC_SEGMENT_64B),
8658 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8659 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8660 PPC_SEGMENT_64B),
8661 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8662 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8663 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8664 #endif
8665 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8666 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8667 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8668 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8669 #if defined(TARGET_PPC64)
8670 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8671 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8672 #endif
8673 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8674 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8675 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8676 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8677 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8678 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8679 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8680 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8681 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8682 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8683 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8684 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8685 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8686 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8687 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8688 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8689 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8690 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8691 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8692 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8693 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8694 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8695 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8696 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8697 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8698 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8699 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8700 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8701 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8702 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8703 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8704 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8705 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8706 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8707 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8708 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8709 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8710 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8711 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8712 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8713 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8714 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8715 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8716 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8717 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8718 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8719 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8720 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8721 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8722 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8723 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8724 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8725 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8726 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8727 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8728 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8729 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8730 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8731 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8732 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8733 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8734 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8735 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8736 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8737 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8738 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8739 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8740 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8741 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8742 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8743 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8744 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8745 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8746 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8747 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8748 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8749 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8750 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8751 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8752 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8753 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8754 PPC_NONE, PPC2_BOOKE206),
8755 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8756 PPC_NONE, PPC2_BOOKE206),
8757 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8758 PPC_NONE, PPC2_BOOKE206),
8759 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8760 PPC_NONE, PPC2_BOOKE206),
8761 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8762 PPC_NONE, PPC2_BOOKE206),
8763 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8764 PPC_NONE, PPC2_PRCNTL),
8765 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8766 PPC_NONE, PPC2_PRCNTL),
8767 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8768 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8769 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8770 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8771 PPC_BOOKE, PPC2_BOOKE206),
8772 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8773 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8774 PPC_BOOKE, PPC2_BOOKE206),
8775 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8776 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8777 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8778 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8779 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8780 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8781 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8782 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8783 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8784 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8785
8786 #undef GEN_INT_ARITH_ADD
8787 #undef GEN_INT_ARITH_ADD_CONST
8788 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8789 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8790 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8791 add_ca, compute_ca, compute_ov) \
8792 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8793 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8794 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8795 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8796 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8797 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8798 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8799 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8800 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8801 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8802 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8803
8804 #undef GEN_INT_ARITH_DIVW
8805 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8806 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8807 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8808 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8809 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8810 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8811
8812 #if defined(TARGET_PPC64)
8813 #undef GEN_INT_ARITH_DIVD
8814 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8815 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8816 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8817 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8818 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8819 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8820
8821 #undef GEN_INT_ARITH_MUL_HELPER
8822 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8823 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8824 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8825 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8826 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8827 #endif
8828
8829 #undef GEN_INT_ARITH_SUBF
8830 #undef GEN_INT_ARITH_SUBF_CONST
8831 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8832 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8833 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8834 add_ca, compute_ca, compute_ov) \
8835 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8836 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8837 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8838 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8839 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8840 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8841 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8842 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8843 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8844 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8845 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8846
8847 #undef GEN_LOGICAL1
8848 #undef GEN_LOGICAL2
8849 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8850 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8851 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8852 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8853 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8854 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8855 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8856 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8857 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8858 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8859 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8860 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8861 #if defined(TARGET_PPC64)
8862 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8863 #endif
8864
8865 #if defined(TARGET_PPC64)
8866 #undef GEN_PPC64_R2
8867 #undef GEN_PPC64_R4
8868 #define GEN_PPC64_R2(name, opc1, opc2) \
8869 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8870 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8871 PPC_64B)
8872 #define GEN_PPC64_R4(name, opc1, opc2) \
8873 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8874 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8875 PPC_64B), \
8876 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8877 PPC_64B), \
8878 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8879 PPC_64B)
8880 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8881 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8882 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8883 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8884 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8885 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8886 #endif
8887
8888 #undef _GEN_FLOAT_ACB
8889 #undef GEN_FLOAT_ACB
8890 #undef _GEN_FLOAT_AB
8891 #undef GEN_FLOAT_AB
8892 #undef _GEN_FLOAT_AC
8893 #undef GEN_FLOAT_AC
8894 #undef GEN_FLOAT_B
8895 #undef GEN_FLOAT_BS
8896 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8897 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8898 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8899 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8900 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8901 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8902 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8903 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8904 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8905 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8906 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8907 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8908 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8909 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8910 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8911 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8912 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8913 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8914 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8915
8916 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8917 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8918 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8919 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8920 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8921 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8922 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8923 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8924 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8925 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8926 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8927 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8928 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8929 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8930 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8931 #if defined(TARGET_PPC64)
8932 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8933 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8934 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8935 #endif
8936 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8937 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8938 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8939 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8940 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8941 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8942 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8943
8944 #undef GEN_LD
8945 #undef GEN_LDU
8946 #undef GEN_LDUX
8947 #undef GEN_LDX_E
8948 #undef GEN_LDS
8949 #define GEN_LD(name, ldop, opc, type) \
8950 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8951 #define GEN_LDU(name, ldop, opc, type) \
8952 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8953 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8954 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8955 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8956 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8957 #define GEN_LDS(name, ldop, op, type) \
8958 GEN_LD(name, ldop, op | 0x20, type) \
8959 GEN_LDU(name, ldop, op | 0x21, type) \
8960 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8961 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8962
8963 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8964 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8965 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8966 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8967 #if defined(TARGET_PPC64)
8968 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8969 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8970 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8971 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8972 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8973 #endif
8974 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8975 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8976
8977 #undef GEN_ST
8978 #undef GEN_STU
8979 #undef GEN_STUX
8980 #undef GEN_STX_E
8981 #undef GEN_STS
8982 #define GEN_ST(name, stop, opc, type) \
8983 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8984 #define GEN_STU(name, stop, opc, type) \
8985 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8986 #define GEN_STUX(name, stop, opc2, opc3, type) \
8987 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8988 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8989 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8990 #define GEN_STS(name, stop, op, type) \
8991 GEN_ST(name, stop, op | 0x20, type) \
8992 GEN_STU(name, stop, op | 0x21, type) \
8993 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8994 GEN_STX(name, stop, 0x17, op | 0x00, type)
8995
8996 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8997 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8998 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8999 #if defined(TARGET_PPC64)
9000 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9001 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9002 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9003 #endif
9004 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9005 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9006
9007 #undef GEN_LDF
9008 #undef GEN_LDUF
9009 #undef GEN_LDUXF
9010 #undef GEN_LDXF
9011 #undef GEN_LDFS
9012 #define GEN_LDF(name, ldop, opc, type) \
9013 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9014 #define GEN_LDUF(name, ldop, opc, type) \
9015 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9016 #define GEN_LDUXF(name, ldop, opc, type) \
9017 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9018 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9019 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9020 #define GEN_LDFS(name, ldop, op, type) \
9021 GEN_LDF(name, ldop, op | 0x20, type) \
9022 GEN_LDUF(name, ldop, op | 0x21, type) \
9023 GEN_LDUXF(name, ldop, op | 0x01, type) \
9024 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9025
9026 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9027 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9028
9029 #undef GEN_STF
9030 #undef GEN_STUF
9031 #undef GEN_STUXF
9032 #undef GEN_STXF
9033 #undef GEN_STFS
9034 #define GEN_STF(name, stop, opc, type) \
9035 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9036 #define GEN_STUF(name, stop, opc, type) \
9037 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9038 #define GEN_STUXF(name, stop, opc, type) \
9039 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9040 #define GEN_STXF(name, stop, opc2, opc3, type) \
9041 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9042 #define GEN_STFS(name, stop, op, type) \
9043 GEN_STF(name, stop, op | 0x20, type) \
9044 GEN_STUF(name, stop, op | 0x21, type) \
9045 GEN_STUXF(name, stop, op | 0x01, type) \
9046 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9047
9048 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9049 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9050 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9051
9052 #undef GEN_CRLOGIC
9053 #define GEN_CRLOGIC(name, tcg_op, opc) \
9054 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9055 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9056 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9057 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9058 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9059 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9060 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9061 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9062 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9063
9064 #undef GEN_MAC_HANDLER
9065 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9066 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9067 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9068 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9069 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9070 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9071 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9072 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9073 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9074 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9075 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9076 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9077 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9078 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9079 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9080 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9081 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9082 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9083 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9084 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9085 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9086 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9087 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9088 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9089 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9090 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9091 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9092 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9093 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9094 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9095 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9096 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9097 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9098 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9099 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9100 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9101 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9102 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9103 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9104 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9105 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9106 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9107 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9108 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9109
9110 #undef GEN_VR_LDX
9111 #undef GEN_VR_STX
9112 #undef GEN_VR_LVE
9113 #undef GEN_VR_STVE
9114 #define GEN_VR_LDX(name, opc2, opc3) \
9115 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9116 #define GEN_VR_STX(name, opc2, opc3) \
9117 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9118 #define GEN_VR_LVE(name, opc2, opc3) \
9119 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9120 #define GEN_VR_STVE(name, opc2, opc3) \
9121 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9122 GEN_VR_LDX(lvx, 0x07, 0x03),
9123 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9124 GEN_VR_LVE(bx, 0x07, 0x00),
9125 GEN_VR_LVE(hx, 0x07, 0x01),
9126 GEN_VR_LVE(wx, 0x07, 0x02),
9127 GEN_VR_STX(svx, 0x07, 0x07),
9128 GEN_VR_STX(svxl, 0x07, 0x0F),
9129 GEN_VR_STVE(bx, 0x07, 0x04),
9130 GEN_VR_STVE(hx, 0x07, 0x05),
9131 GEN_VR_STVE(wx, 0x07, 0x06),
9132
9133 #undef GEN_VX_LOGICAL
9134 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9135 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9136 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9137 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9138 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9139 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9140 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9141
9142 #undef GEN_VXFORM
9143 #define GEN_VXFORM(name, opc2, opc3) \
9144 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9145 GEN_VXFORM(vaddubm, 0, 0),
9146 GEN_VXFORM(vadduhm, 0, 1),
9147 GEN_VXFORM(vadduwm, 0, 2),
9148 GEN_VXFORM(vsububm, 0, 16),
9149 GEN_VXFORM(vsubuhm, 0, 17),
9150 GEN_VXFORM(vsubuwm, 0, 18),
9151 GEN_VXFORM(vmaxub, 1, 0),
9152 GEN_VXFORM(vmaxuh, 1, 1),
9153 GEN_VXFORM(vmaxuw, 1, 2),
9154 GEN_VXFORM(vmaxsb, 1, 4),
9155 GEN_VXFORM(vmaxsh, 1, 5),
9156 GEN_VXFORM(vmaxsw, 1, 6),
9157 GEN_VXFORM(vminub, 1, 8),
9158 GEN_VXFORM(vminuh, 1, 9),
9159 GEN_VXFORM(vminuw, 1, 10),
9160 GEN_VXFORM(vminsb, 1, 12),
9161 GEN_VXFORM(vminsh, 1, 13),
9162 GEN_VXFORM(vminsw, 1, 14),
9163 GEN_VXFORM(vavgub, 1, 16),
9164 GEN_VXFORM(vavguh, 1, 17),
9165 GEN_VXFORM(vavguw, 1, 18),
9166 GEN_VXFORM(vavgsb, 1, 20),
9167 GEN_VXFORM(vavgsh, 1, 21),
9168 GEN_VXFORM(vavgsw, 1, 22),
9169 GEN_VXFORM(vmrghb, 6, 0),
9170 GEN_VXFORM(vmrghh, 6, 1),
9171 GEN_VXFORM(vmrghw, 6, 2),
9172 GEN_VXFORM(vmrglb, 6, 4),
9173 GEN_VXFORM(vmrglh, 6, 5),
9174 GEN_VXFORM(vmrglw, 6, 6),
9175 GEN_VXFORM(vmuloub, 4, 0),
9176 GEN_VXFORM(vmulouh, 4, 1),
9177 GEN_VXFORM(vmulosb, 4, 4),
9178 GEN_VXFORM(vmulosh, 4, 5),
9179 GEN_VXFORM(vmuleub, 4, 8),
9180 GEN_VXFORM(vmuleuh, 4, 9),
9181 GEN_VXFORM(vmulesb, 4, 12),
9182 GEN_VXFORM(vmulesh, 4, 13),
9183 GEN_VXFORM(vslb, 2, 4),
9184 GEN_VXFORM(vslh, 2, 5),
9185 GEN_VXFORM(vslw, 2, 6),
9186 GEN_VXFORM(vsrb, 2, 8),
9187 GEN_VXFORM(vsrh, 2, 9),
9188 GEN_VXFORM(vsrw, 2, 10),
9189 GEN_VXFORM(vsrab, 2, 12),
9190 GEN_VXFORM(vsrah, 2, 13),
9191 GEN_VXFORM(vsraw, 2, 14),
9192 GEN_VXFORM(vslo, 6, 16),
9193 GEN_VXFORM(vsro, 6, 17),
9194 GEN_VXFORM(vaddcuw, 0, 6),
9195 GEN_VXFORM(vsubcuw, 0, 22),
9196 GEN_VXFORM(vaddubs, 0, 8),
9197 GEN_VXFORM(vadduhs, 0, 9),
9198 GEN_VXFORM(vadduws, 0, 10),
9199 GEN_VXFORM(vaddsbs, 0, 12),
9200 GEN_VXFORM(vaddshs, 0, 13),
9201 GEN_VXFORM(vaddsws, 0, 14),
9202 GEN_VXFORM(vsububs, 0, 24),
9203 GEN_VXFORM(vsubuhs, 0, 25),
9204 GEN_VXFORM(vsubuws, 0, 26),
9205 GEN_VXFORM(vsubsbs, 0, 28),
9206 GEN_VXFORM(vsubshs, 0, 29),
9207 GEN_VXFORM(vsubsws, 0, 30),
9208 GEN_VXFORM(vrlb, 2, 0),
9209 GEN_VXFORM(vrlh, 2, 1),
9210 GEN_VXFORM(vrlw, 2, 2),
9211 GEN_VXFORM(vsl, 2, 7),
9212 GEN_VXFORM(vsr, 2, 11),
9213 GEN_VXFORM(vpkuhum, 7, 0),
9214 GEN_VXFORM(vpkuwum, 7, 1),
9215 GEN_VXFORM(vpkuhus, 7, 2),
9216 GEN_VXFORM(vpkuwus, 7, 3),
9217 GEN_VXFORM(vpkshus, 7, 4),
9218 GEN_VXFORM(vpkswus, 7, 5),
9219 GEN_VXFORM(vpkshss, 7, 6),
9220 GEN_VXFORM(vpkswss, 7, 7),
9221 GEN_VXFORM(vpkpx, 7, 12),
9222 GEN_VXFORM(vsum4ubs, 4, 24),
9223 GEN_VXFORM(vsum4sbs, 4, 28),
9224 GEN_VXFORM(vsum4shs, 4, 25),
9225 GEN_VXFORM(vsum2sws, 4, 26),
9226 GEN_VXFORM(vsumsws, 4, 30),
9227 GEN_VXFORM(vaddfp, 5, 0),
9228 GEN_VXFORM(vsubfp, 5, 1),
9229 GEN_VXFORM(vmaxfp, 5, 16),
9230 GEN_VXFORM(vminfp, 5, 17),
9231
9232 #undef GEN_VXRFORM1
9233 #undef GEN_VXRFORM
9234 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9235 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9236 #define GEN_VXRFORM(name, opc2, opc3) \
9237 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9238 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9239 GEN_VXRFORM(vcmpequb, 3, 0)
9240 GEN_VXRFORM(vcmpequh, 3, 1)
9241 GEN_VXRFORM(vcmpequw, 3, 2)
9242 GEN_VXRFORM(vcmpgtsb, 3, 12)
9243 GEN_VXRFORM(vcmpgtsh, 3, 13)
9244 GEN_VXRFORM(vcmpgtsw, 3, 14)
9245 GEN_VXRFORM(vcmpgtub, 3, 8)
9246 GEN_VXRFORM(vcmpgtuh, 3, 9)
9247 GEN_VXRFORM(vcmpgtuw, 3, 10)
9248 GEN_VXRFORM(vcmpeqfp, 3, 3)
9249 GEN_VXRFORM(vcmpgefp, 3, 7)
9250 GEN_VXRFORM(vcmpgtfp, 3, 11)
9251 GEN_VXRFORM(vcmpbfp, 3, 15)
9252
9253 #undef GEN_VXFORM_SIMM
9254 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9255 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9256 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9257 GEN_VXFORM_SIMM(vspltish, 6, 13),
9258 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9259
9260 #undef GEN_VXFORM_NOA
9261 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9262 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9263 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9264 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9265 GEN_VXFORM_NOA(vupklsb, 7, 10),
9266 GEN_VXFORM_NOA(vupklsh, 7, 11),
9267 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9268 GEN_VXFORM_NOA(vupklpx, 7, 15),
9269 GEN_VXFORM_NOA(vrefp, 5, 4),
9270 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9271 GEN_VXFORM_NOA(vexptefp, 5, 6),
9272 GEN_VXFORM_NOA(vlogefp, 5, 7),
9273 GEN_VXFORM_NOA(vrfim, 5, 8),
9274 GEN_VXFORM_NOA(vrfin, 5, 9),
9275 GEN_VXFORM_NOA(vrfip, 5, 10),
9276 GEN_VXFORM_NOA(vrfiz, 5, 11),
9277
9278 #undef GEN_VXFORM_UIMM
9279 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9280 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9281 GEN_VXFORM_UIMM(vspltb, 6, 8),
9282 GEN_VXFORM_UIMM(vsplth, 6, 9),
9283 GEN_VXFORM_UIMM(vspltw, 6, 10),
9284 GEN_VXFORM_UIMM(vcfux, 5, 12),
9285 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9286 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9287 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9288
9289 #undef GEN_VAFORM_PAIRED
9290 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9291 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9292 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9293 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9294 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9295 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9296 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9297 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9298
9299 #undef GEN_SPE
9300 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9301 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9302 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9303 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9304 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9305 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9306 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9307 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9308 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9309 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9310 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9311 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9312 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9313 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9314 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9315 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9316 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9317 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9318 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9319 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9320 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9321 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9322 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9323 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9324 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9325 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9326 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9327 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9328 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9329 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9330 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9331
9332 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9333 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9334 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9335 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9336 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9337 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9338 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9339 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9340 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9341 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9342 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9343 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9344 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9345 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9346
9347 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9348 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9349 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9350 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9351 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9352 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9353 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9354 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9355 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9356 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9357 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9358 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9359 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9360 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9361
9362 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9363 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9364 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9365 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9366 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9367 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9368 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9369 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9370 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9371 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9372 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9373 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9374 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9375 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9376 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9377 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9378
9379 #undef GEN_SPEOP_LDST
9380 #define GEN_SPEOP_LDST(name, opc2, sh) \
9381 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9382 GEN_SPEOP_LDST(evldd, 0x00, 3),
9383 GEN_SPEOP_LDST(evldw, 0x01, 3),
9384 GEN_SPEOP_LDST(evldh, 0x02, 3),
9385 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9386 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9387 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9388 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9389 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9390 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9391 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9392 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9393
9394 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9395 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9396 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9397 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9398 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9399 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9400 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9401 };
9402
9403 #include "helper_regs.h"
9404 #include "translate_init.c"
9405
9406 /*****************************************************************************/
9407 /* Misc PowerPC helpers */
9408 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9409 int flags)
9410 {
9411 #define RGPL 4
9412 #define RFPL 4
9413
9414 int i;
9415
9416 cpu_synchronize_state(env);
9417
9418 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9419 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9420 env->nip, env->lr, env->ctr, env->xer);
9421 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9422 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9423 env->hflags, env->mmu_idx);
9424 #if !defined(NO_TIMER_DUMP)
9425 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9426 #if !defined(CONFIG_USER_ONLY)
9427 " DECR %08" PRIu32
9428 #endif
9429 "\n",
9430 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9431 #if !defined(CONFIG_USER_ONLY)
9432 , cpu_ppc_load_decr(env)
9433 #endif
9434 );
9435 #endif
9436 for (i = 0; i < 32; i++) {
9437 if ((i & (RGPL - 1)) == 0)
9438 cpu_fprintf(f, "GPR%02d", i);
9439 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9440 if ((i & (RGPL - 1)) == (RGPL - 1))
9441 cpu_fprintf(f, "\n");
9442 }
9443 cpu_fprintf(f, "CR ");
9444 for (i = 0; i < 8; i++)
9445 cpu_fprintf(f, "%01x", env->crf[i]);
9446 cpu_fprintf(f, " [");
9447 for (i = 0; i < 8; i++) {
9448 char a = '-';
9449 if (env->crf[i] & 0x08)
9450 a = 'L';
9451 else if (env->crf[i] & 0x04)
9452 a = 'G';
9453 else if (env->crf[i] & 0x02)
9454 a = 'E';
9455 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9456 }
9457 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9458 env->reserve_addr);
9459 for (i = 0; i < 32; i++) {
9460 if ((i & (RFPL - 1)) == 0)
9461 cpu_fprintf(f, "FPR%02d", i);
9462 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9463 if ((i & (RFPL - 1)) == (RFPL - 1))
9464 cpu_fprintf(f, "\n");
9465 }
9466 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
9467 #if !defined(CONFIG_USER_ONLY)
9468 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9469 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9470 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9471 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9472
9473 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9474 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9475 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9476 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9477
9478 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9479 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9480 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9481 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9482
9483 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9484 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9485 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9486 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9487 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9488
9489 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9490 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9491 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9492 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9493
9494 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9495 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9496 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9497 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9498
9499 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9500 " EPR " TARGET_FMT_lx "\n",
9501 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9502 env->spr[SPR_BOOKE_EPR]);
9503
9504 /* FSL-specific */
9505 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9506 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9507 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9508 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9509
9510 /*
9511 * IVORs are left out as they are large and do not change often --
9512 * they can be read with "p $ivor0", "p $ivor1", etc.
9513 */
9514 }
9515
9516 #if defined(TARGET_PPC64)
9517 if (env->flags & POWERPC_FLAG_CFAR) {
9518 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9519 }
9520 #endif
9521
9522 switch (env->mmu_model) {
9523 case POWERPC_MMU_32B:
9524 case POWERPC_MMU_601:
9525 case POWERPC_MMU_SOFT_6xx:
9526 case POWERPC_MMU_SOFT_74xx:
9527 #if defined(TARGET_PPC64)
9528 case POWERPC_MMU_620:
9529 case POWERPC_MMU_64B:
9530 #endif
9531 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9532 break;
9533 case POWERPC_MMU_BOOKE206:
9534 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9535 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9536 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9537 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9538
9539 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9540 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9541 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9542 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9543
9544 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9545 " TLB1CFG " TARGET_FMT_lx "\n",
9546 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9547 env->spr[SPR_BOOKE_TLB1CFG]);
9548 break;
9549 default:
9550 break;
9551 }
9552 #endif
9553
9554 #undef RGPL
9555 #undef RFPL
9556 }
9557
9558 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9559 int flags)
9560 {
9561 #if defined(DO_PPC_STATISTICS)
9562 opc_handler_t **t1, **t2, **t3, *handler;
9563 int op1, op2, op3;
9564
9565 t1 = env->opcodes;
9566 for (op1 = 0; op1 < 64; op1++) {
9567 handler = t1[op1];
9568 if (is_indirect_opcode(handler)) {
9569 t2 = ind_table(handler);
9570 for (op2 = 0; op2 < 32; op2++) {
9571 handler = t2[op2];
9572 if (is_indirect_opcode(handler)) {
9573 t3 = ind_table(handler);
9574 for (op3 = 0; op3 < 32; op3++) {
9575 handler = t3[op3];
9576 if (handler->count == 0)
9577 continue;
9578 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9579 "%016" PRIx64 " %" PRId64 "\n",
9580 op1, op2, op3, op1, (op3 << 5) | op2,
9581 handler->oname,
9582 handler->count, handler->count);
9583 }
9584 } else {
9585 if (handler->count == 0)
9586 continue;
9587 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9588 "%016" PRIx64 " %" PRId64 "\n",
9589 op1, op2, op1, op2, handler->oname,
9590 handler->count, handler->count);
9591 }
9592 }
9593 } else {
9594 if (handler->count == 0)
9595 continue;
9596 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9597 " %" PRId64 "\n",
9598 op1, op1, handler->oname,
9599 handler->count, handler->count);
9600 }
9601 }
9602 #endif
9603 }
9604
9605 /*****************************************************************************/
9606 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9607 TranslationBlock *tb,
9608 int search_pc)
9609 {
9610 DisasContext ctx, *ctxp = &ctx;
9611 opc_handler_t **table, *handler;
9612 target_ulong pc_start;
9613 uint16_t *gen_opc_end;
9614 CPUBreakpoint *bp;
9615 int j, lj = -1;
9616 int num_insns;
9617 int max_insns;
9618
9619 pc_start = tb->pc;
9620 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9621 ctx.nip = pc_start;
9622 ctx.tb = tb;
9623 ctx.exception = POWERPC_EXCP_NONE;
9624 ctx.spr_cb = env->spr_cb;
9625 ctx.mem_idx = env->mmu_idx;
9626 ctx.access_type = -1;
9627 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9628 #if defined(TARGET_PPC64)
9629 ctx.sf_mode = msr_is_64bit(env, env->msr);
9630 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9631 #endif
9632 ctx.fpu_enabled = msr_fp;
9633 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9634 ctx.spe_enabled = msr_spe;
9635 else
9636 ctx.spe_enabled = 0;
9637 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9638 ctx.altivec_enabled = msr_vr;
9639 else
9640 ctx.altivec_enabled = 0;
9641 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9642 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9643 else
9644 ctx.singlestep_enabled = 0;
9645 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9646 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9647 if (unlikely(env->singlestep_enabled))
9648 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9649 #if defined (DO_SINGLE_STEP) && 0
9650 /* Single step trace mode */
9651 msr_se = 1;
9652 #endif
9653 num_insns = 0;
9654 max_insns = tb->cflags & CF_COUNT_MASK;
9655 if (max_insns == 0)
9656 max_insns = CF_COUNT_MASK;
9657
9658 gen_icount_start();
9659 /* Set env in case of segfault during code fetch */
9660 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
9661 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9662 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9663 if (bp->pc == ctx.nip) {
9664 gen_debug_exception(ctxp);
9665 break;
9666 }
9667 }
9668 }
9669 if (unlikely(search_pc)) {
9670 j = gen_opc_ptr - gen_opc_buf;
9671 if (lj < j) {
9672 lj++;
9673 while (lj < j)
9674 gen_opc_instr_start[lj++] = 0;
9675 }
9676 gen_opc_pc[lj] = ctx.nip;
9677 gen_opc_instr_start[lj] = 1;
9678 gen_opc_icount[lj] = num_insns;
9679 }
9680 LOG_DISAS("----------------\n");
9681 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9682 ctx.nip, ctx.mem_idx, (int)msr_ir);
9683 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9684 gen_io_start();
9685 if (unlikely(ctx.le_mode)) {
9686 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9687 } else {
9688 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9689 }
9690 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9691 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9692 opc3(ctx.opcode), little_endian ? "little" : "big");
9693 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
9694 tcg_gen_debug_insn_start(ctx.nip);
9695 ctx.nip += 4;
9696 table = env->opcodes;
9697 num_insns++;
9698 handler = table[opc1(ctx.opcode)];
9699 if (is_indirect_opcode(handler)) {
9700 table = ind_table(handler);
9701 handler = table[opc2(ctx.opcode)];
9702 if (is_indirect_opcode(handler)) {
9703 table = ind_table(handler);
9704 handler = table[opc3(ctx.opcode)];
9705 }
9706 }
9707 /* Is opcode *REALLY* valid ? */
9708 if (unlikely(handler->handler == &gen_invalid)) {
9709 if (qemu_log_enabled()) {
9710 qemu_log("invalid/unsupported opcode: "
9711 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9712 opc1(ctx.opcode), opc2(ctx.opcode),
9713 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9714 }
9715 } else {
9716 uint32_t inval;
9717
9718 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9719 inval = handler->inval2;
9720 } else {
9721 inval = handler->inval1;
9722 }
9723
9724 if (unlikely((ctx.opcode & inval) != 0)) {
9725 if (qemu_log_enabled()) {
9726 qemu_log("invalid bits: %08x for opcode: "
9727 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9728 ctx.opcode & inval, opc1(ctx.opcode),
9729 opc2(ctx.opcode), opc3(ctx.opcode),
9730 ctx.opcode, ctx.nip - 4);
9731 }
9732 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9733 break;
9734 }
9735 }
9736 (*(handler->handler))(&ctx);
9737 #if defined(DO_PPC_STATISTICS)
9738 handler->count++;
9739 #endif
9740 /* Check trace mode exceptions */
9741 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9742 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9743 ctx.exception != POWERPC_SYSCALL &&
9744 ctx.exception != POWERPC_EXCP_TRAP &&
9745 ctx.exception != POWERPC_EXCP_BRANCH)) {
9746 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9747 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9748 (env->singlestep_enabled) ||
9749 singlestep ||
9750 num_insns >= max_insns)) {
9751 /* if we reach a page boundary or are single stepping, stop
9752 * generation
9753 */
9754 break;
9755 }
9756 }
9757 if (tb->cflags & CF_LAST_IO)
9758 gen_io_end();
9759 if (ctx.exception == POWERPC_EXCP_NONE) {
9760 gen_goto_tb(&ctx, 0, ctx.nip);
9761 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9762 if (unlikely(env->singlestep_enabled)) {
9763 gen_debug_exception(ctxp);
9764 }
9765 /* Generate the return instruction */
9766 tcg_gen_exit_tb(0);
9767 }
9768 gen_icount_end(tb, num_insns);
9769 *gen_opc_ptr = INDEX_op_end;
9770 if (unlikely(search_pc)) {
9771 j = gen_opc_ptr - gen_opc_buf;
9772 lj++;
9773 while (lj <= j)
9774 gen_opc_instr_start[lj++] = 0;
9775 } else {
9776 tb->size = ctx.nip - pc_start;
9777 tb->icount = num_insns;
9778 }
9779 #if defined(DEBUG_DISAS)
9780 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9781 int flags;
9782 flags = env->bfd_mach;
9783 flags |= ctx.le_mode << 16;
9784 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9785 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9786 qemu_log("\n");
9787 }
9788 #endif
9789 }
9790
9791 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9792 {
9793 gen_intermediate_code_internal(env, tb, 0);
9794 }
9795
9796 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9797 {
9798 gen_intermediate_code_internal(env, tb, 1);
9799 }
9800
9801 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9802 {
9803 env->nip = gen_opc_pc[pc_pos];
9804 }
Qemu with PowerPC KVM improvements