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target-ppc: Make host CPU a subclass of the host's CPU model
[qemu/agraf.git] / target-ppc / translate_init.c
blob521cdcca8ca2a1ae0e35adef4f613657a7649b24
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28
29 //#define PPC_DUMP_CPU
30 //#define PPC_DEBUG_SPR
31 //#define PPC_DUMP_SPR_ACCESSES
32
33 /* For user-mode emulation, we don't emulate any IRQ controller */
34 #if defined(CONFIG_USER_ONLY)
35 #define PPC_IRQ_INIT_FN(name) \
36 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
37 { \
38 }
39 #else
40 #define PPC_IRQ_INIT_FN(name) \
41 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
42 #endif
43
44 PPC_IRQ_INIT_FN(40x);
45 PPC_IRQ_INIT_FN(6xx);
46 PPC_IRQ_INIT_FN(970);
47 PPC_IRQ_INIT_FN(POWER7);
48 PPC_IRQ_INIT_FN(e500);
49
50 /* Generic callbacks:
51 * do nothing but store/retrieve spr value
52 */
53 static void spr_load_dump_spr(int sprn)
54 {
55 #ifdef PPC_DUMP_SPR_ACCESSES
56 TCGv_i32 t0 = tcg_const_i32(sprn);
57 gen_helper_load_dump_spr(cpu_env, t0);
58 tcg_temp_free_i32(t0);
59 #endif
60 }
61
62 static void spr_read_generic (void *opaque, int gprn, int sprn)
63 {
64 gen_load_spr(cpu_gpr[gprn], sprn);
65 spr_load_dump_spr(sprn);
66 }
67
68 static void spr_store_dump_spr(int sprn)
69 {
70 #ifdef PPC_DUMP_SPR_ACCESSES
71 TCGv_i32 t0 = tcg_const_i32(sprn);
72 gen_helper_store_dump_spr(cpu_env, t0);
73 tcg_temp_free_i32(t0);
74 #endif
75 }
76
77 static void spr_write_generic (void *opaque, int sprn, int gprn)
78 {
79 gen_store_spr(sprn, cpu_gpr[gprn]);
80 spr_store_dump_spr(sprn);
81 }
82
83 #if !defined(CONFIG_USER_ONLY)
84 static void spr_write_generic32(void *opaque, int sprn, int gprn)
85 {
86 #ifdef TARGET_PPC64
87 TCGv t0 = tcg_temp_new();
88 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
89 gen_store_spr(sprn, t0);
90 tcg_temp_free(t0);
91 spr_store_dump_spr(sprn);
92 #else
93 spr_write_generic(opaque, sprn, gprn);
94 #endif
95 }
96
97 static void spr_write_clear (void *opaque, int sprn, int gprn)
98 {
99 TCGv t0 = tcg_temp_new();
100 TCGv t1 = tcg_temp_new();
101 gen_load_spr(t0, sprn);
102 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
103 tcg_gen_and_tl(t0, t0, t1);
104 gen_store_spr(sprn, t0);
105 tcg_temp_free(t0);
106 tcg_temp_free(t1);
107 }
108 #endif
109
110 /* SPR common to all PowerPC */
111 /* XER */
112 static void spr_read_xer (void *opaque, int gprn, int sprn)
113 {
114 gen_read_xer(cpu_gpr[gprn]);
115 }
116
117 static void spr_write_xer (void *opaque, int sprn, int gprn)
118 {
119 gen_write_xer(cpu_gpr[gprn]);
120 }
121
122 /* LR */
123 static void spr_read_lr (void *opaque, int gprn, int sprn)
124 {
125 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
126 }
127
128 static void spr_write_lr (void *opaque, int sprn, int gprn)
129 {
130 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
131 }
132
133 /* CFAR */
134 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
135 static void spr_read_cfar (void *opaque, int gprn, int sprn)
136 {
137 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
138 }
139
140 static void spr_write_cfar (void *opaque, int sprn, int gprn)
141 {
142 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
143 }
144 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
145
146 /* CTR */
147 static void spr_read_ctr (void *opaque, int gprn, int sprn)
148 {
149 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
150 }
151
152 static void spr_write_ctr (void *opaque, int sprn, int gprn)
153 {
154 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
155 }
156
157 /* User read access to SPR */
158 /* USPRx */
159 /* UMMCRx */
160 /* UPMCx */
161 /* USIA */
162 /* UDECR */
163 static void spr_read_ureg (void *opaque, int gprn, int sprn)
164 {
165 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
166 }
167
168 /* SPR common to all non-embedded PowerPC */
169 /* DECR */
170 #if !defined(CONFIG_USER_ONLY)
171 static void spr_read_decr (void *opaque, int gprn, int sprn)
172 {
173 if (use_icount) {
174 gen_io_start();
175 }
176 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
177 if (use_icount) {
178 gen_io_end();
179 gen_stop_exception(opaque);
180 }
181 }
182
183 static void spr_write_decr (void *opaque, int sprn, int gprn)
184 {
185 if (use_icount) {
186 gen_io_start();
187 }
188 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
189 if (use_icount) {
190 gen_io_end();
191 gen_stop_exception(opaque);
192 }
193 }
194 #endif
195
196 /* SPR common to all non-embedded PowerPC, except 601 */
197 /* Time base */
198 static void spr_read_tbl (void *opaque, int gprn, int sprn)
199 {
200 if (use_icount) {
201 gen_io_start();
202 }
203 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
204 if (use_icount) {
205 gen_io_end();
206 gen_stop_exception(opaque);
207 }
208 }
209
210 static void spr_read_tbu (void *opaque, int gprn, int sprn)
211 {
212 if (use_icount) {
213 gen_io_start();
214 }
215 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
216 if (use_icount) {
217 gen_io_end();
218 gen_stop_exception(opaque);
219 }
220 }
221
222 __attribute__ (( unused ))
223 static void spr_read_atbl (void *opaque, int gprn, int sprn)
224 {
225 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
226 }
227
228 __attribute__ (( unused ))
229 static void spr_read_atbu (void *opaque, int gprn, int sprn)
230 {
231 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
232 }
233
234 #if !defined(CONFIG_USER_ONLY)
235 static void spr_write_tbl (void *opaque, int sprn, int gprn)
236 {
237 if (use_icount) {
238 gen_io_start();
239 }
240 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
241 if (use_icount) {
242 gen_io_end();
243 gen_stop_exception(opaque);
244 }
245 }
246
247 static void spr_write_tbu (void *opaque, int sprn, int gprn)
248 {
249 if (use_icount) {
250 gen_io_start();
251 }
252 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
253 if (use_icount) {
254 gen_io_end();
255 gen_stop_exception(opaque);
256 }
257 }
258
259 __attribute__ (( unused ))
260 static void spr_write_atbl (void *opaque, int sprn, int gprn)
261 {
262 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
263 }
264
265 __attribute__ (( unused ))
266 static void spr_write_atbu (void *opaque, int sprn, int gprn)
267 {
268 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
269 }
270
271 #if defined(TARGET_PPC64)
272 __attribute__ (( unused ))
273 static void spr_read_purr (void *opaque, int gprn, int sprn)
274 {
275 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
276 }
277 #endif
278 #endif
279
280 #if !defined(CONFIG_USER_ONLY)
281 /* IBAT0U...IBAT0U */
282 /* IBAT0L...IBAT7L */
283 static void spr_read_ibat (void *opaque, int gprn, int sprn)
284 {
285 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
286 }
287
288 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
289 {
290 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
291 }
292
293 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
296 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
303 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
308 {
309 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
310 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
311 tcg_temp_free_i32(t0);
312 }
313
314 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
315 {
316 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
317 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
318 tcg_temp_free_i32(t0);
319 }
320
321 /* DBAT0U...DBAT7U */
322 /* DBAT0L...DBAT7L */
323 static void spr_read_dbat (void *opaque, int gprn, int sprn)
324 {
325 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
326 }
327
328 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
329 {
330 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
331 }
332
333 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
336 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
343 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
348 {
349 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
350 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
351 tcg_temp_free_i32(t0);
352 }
353
354 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
355 {
356 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
357 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
358 tcg_temp_free_i32(t0);
359 }
360
361 /* SDR1 */
362 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
363 {
364 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
365 }
366
367 /* 64 bits PowerPC specific SPRs */
368 /* ASR */
369 #if defined(TARGET_PPC64)
370 static void spr_read_hior (void *opaque, int gprn, int sprn)
371 {
372 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
373 }
374
375 static void spr_write_hior (void *opaque, int sprn, int gprn)
376 {
377 TCGv t0 = tcg_temp_new();
378 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
379 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
380 tcg_temp_free(t0);
381 }
382
383 static void spr_read_asr (void *opaque, int gprn, int sprn)
384 {
385 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
386 }
387
388 static void spr_write_asr (void *opaque, int sprn, int gprn)
389 {
390 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
391 }
392 #endif
393 #endif
394
395 /* PowerPC 601 specific registers */
396 /* RTC */
397 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
398 {
399 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
400 }
401
402 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
403 {
404 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
405 }
406
407 #if !defined(CONFIG_USER_ONLY)
408 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
409 {
410 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
411 }
412
413 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
414 {
415 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
416 }
417
418 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
419 {
420 DisasContext *ctx = opaque;
421
422 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
423 /* Must stop the translation as endianness may have changed */
424 gen_stop_exception(ctx);
425 }
426 #endif
427
428 /* Unified bats */
429 #if !defined(CONFIG_USER_ONLY)
430 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
431 {
432 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
433 }
434
435 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
436 {
437 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
438 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
439 tcg_temp_free_i32(t0);
440 }
441
442 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
443 {
444 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
445 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
446 tcg_temp_free_i32(t0);
447 }
448 #endif
449
450 /* PowerPC 40x specific registers */
451 #if !defined(CONFIG_USER_ONLY)
452 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
453 {
454 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
455 }
456
457 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
460 }
461
462 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
463 {
464 DisasContext *ctx = opaque;
465
466 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
467 /* We must stop translation as we may have rebooted */
468 gen_stop_exception(ctx);
469 }
470
471 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
472 {
473 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
474 }
475
476 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
477 {
478 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
479 }
480
481 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
482 {
483 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
484 }
485 #endif
486
487 /* PowerPC 403 specific registers */
488 /* PBL1 / PBU1 / PBL2 / PBU2 */
489 #if !defined(CONFIG_USER_ONLY)
490 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
491 {
492 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
493 }
494
495 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
496 {
497 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
498 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
499 tcg_temp_free_i32(t0);
500 }
501
502 static void spr_write_pir (void *opaque, int sprn, int gprn)
503 {
504 TCGv t0 = tcg_temp_new();
505 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
506 gen_store_spr(SPR_PIR, t0);
507 tcg_temp_free(t0);
508 }
509 #endif
510
511 /* SPE specific registers */
512 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
513 {
514 TCGv_i32 t0 = tcg_temp_new_i32();
515 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
516 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
517 tcg_temp_free_i32(t0);
518 }
519
520 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
521 {
522 TCGv_i32 t0 = tcg_temp_new_i32();
523 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
524 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
525 tcg_temp_free_i32(t0);
526 }
527
528 #if !defined(CONFIG_USER_ONLY)
529 /* Callback used to write the exception vector base */
530 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
531 {
532 TCGv t0 = tcg_temp_new();
533 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
534 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
535 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
536 gen_store_spr(sprn, t0);
537 tcg_temp_free(t0);
538 }
539
540 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
541 {
542 DisasContext *ctx = opaque;
543 int sprn_offs;
544
545 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
546 sprn_offs = sprn - SPR_BOOKE_IVOR0;
547 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
548 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
549 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
550 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
551 } else {
552 printf("Trying to write an unknown exception vector %d %03x\n",
553 sprn, sprn);
554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
555 return;
556 }
557
558 TCGv t0 = tcg_temp_new();
559 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
560 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
561 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
562 gen_store_spr(sprn, t0);
563 tcg_temp_free(t0);
564 }
565 #endif
566
567 static inline void vscr_init (CPUPPCState *env, uint32_t val)
568 {
569 env->vscr = val;
570 /* Altivec always uses round-to-nearest */
571 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
572 set_flush_to_zero(vscr_nj, &env->vec_status);
573 }
574
575 #ifdef CONFIG_USER_ONLY
576 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, one_reg_id, initial_value) \
578 _spr_register(env, num, name, uea_read, uea_write, initial_value)
579 #else
580 #if !defined(CONFIG_KVM)
581 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
582 oea_read, oea_write, one_reg_id, initial_value) \
583 _spr_register(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, initial_value)
585 #else
586 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
587 oea_read, oea_write, one_reg_id, initial_value) \
588 _spr_register(env, num, name, uea_read, uea_write, \
589 oea_read, oea_write, one_reg_id, initial_value)
590 #endif
591 #endif
592
593 #define spr_register(env, num, name, uea_read, uea_write, \
594 oea_read, oea_write, initial_value) \
595 spr_register_kvm(env, num, name, uea_read, uea_write, \
596 oea_read, oea_write, 0, initial_value)
597
598 static inline void _spr_register(CPUPPCState *env, int num,
599 const char *name,
600 void (*uea_read)(void *opaque, int gprn, int sprn),
601 void (*uea_write)(void *opaque, int sprn, int gprn),
602 #if !defined(CONFIG_USER_ONLY)
603
604 void (*oea_read)(void *opaque, int gprn, int sprn),
605 void (*oea_write)(void *opaque, int sprn, int gprn),
606 #endif
607 #if defined(CONFIG_KVM)
608 uint64_t one_reg_id,
609 #endif
610 target_ulong initial_value)
611 {
612 ppc_spr_t *spr;
613
614 spr = &env->spr_cb[num];
615 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
616 #if !defined(CONFIG_USER_ONLY)
617 spr->oea_read != NULL || spr->oea_write != NULL ||
618 #endif
619 spr->uea_read != NULL || spr->uea_write != NULL) {
620 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
621 exit(1);
622 }
623 #if defined(PPC_DEBUG_SPR)
624 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
625 name, initial_value);
626 #endif
627 spr->name = name;
628 spr->uea_read = uea_read;
629 spr->uea_write = uea_write;
630 #if !defined(CONFIG_USER_ONLY)
631 spr->oea_read = oea_read;
632 spr->oea_write = oea_write;
633 #endif
634 env->spr[num] = initial_value;
635 }
636
637 /* Generic PowerPC SPRs */
638 static void gen_spr_generic (CPUPPCState *env)
639 {
640 /* Integer processing */
641 spr_register(env, SPR_XER, "XER",
642 &spr_read_xer, &spr_write_xer,
643 &spr_read_xer, &spr_write_xer,
644 0x00000000);
645 /* Branch contol */
646 spr_register(env, SPR_LR, "LR",
647 &spr_read_lr, &spr_write_lr,
648 &spr_read_lr, &spr_write_lr,
649 0x00000000);
650 spr_register(env, SPR_CTR, "CTR",
651 &spr_read_ctr, &spr_write_ctr,
652 &spr_read_ctr, &spr_write_ctr,
653 0x00000000);
654 /* Interrupt processing */
655 spr_register(env, SPR_SRR0, "SRR0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SRR1, "SRR1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Processor control */
664 spr_register(env, SPR_SPRG0, "SPRG0",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, &spr_write_generic,
667 0x00000000);
668 spr_register(env, SPR_SPRG1, "SPRG1",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_SPRG2, "SPRG2",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SPRG3, "SPRG3",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 }
681
682 /* SPR common to all non-embedded PowerPC, including 601 */
683 static void gen_spr_ne_601 (CPUPPCState *env)
684 {
685 /* Exception processing */
686 spr_register_kvm(env, SPR_DSISR, "DSISR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 KVM_REG_PPC_DSISR, 0x00000000);
690 spr_register_kvm(env, SPR_DAR, "DAR",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, &spr_write_generic,
693 KVM_REG_PPC_DAR, 0x00000000);
694 /* Timer */
695 spr_register(env, SPR_DECR, "DECR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_decr, &spr_write_decr,
698 0x00000000);
699 /* Memory management */
700 spr_register(env, SPR_SDR1, "SDR1",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_sdr1,
703 0x00000000);
704 }
705
706 /* BATs 0-3 */
707 static void gen_low_BATs (CPUPPCState *env)
708 {
709 #if !defined(CONFIG_USER_ONLY)
710 spr_register(env, SPR_IBAT0U, "IBAT0U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT0L, "IBAT0L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT1U, "IBAT1U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT1L, "IBAT1L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_IBAT2U, "IBAT2U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_ibat, &spr_write_ibatu,
729 0x00000000);
730 spr_register(env, SPR_IBAT2L, "IBAT2L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_ibat, &spr_write_ibatl,
733 0x00000000);
734 spr_register(env, SPR_IBAT3U, "IBAT3U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_ibat, &spr_write_ibatu,
737 0x00000000);
738 spr_register(env, SPR_IBAT3L, "IBAT3L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_ibat, &spr_write_ibatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT0U, "DBAT0U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT0L, "DBAT0L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT1U, "DBAT1U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT1L, "DBAT1L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 spr_register(env, SPR_DBAT2U, "DBAT2U",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_dbat, &spr_write_dbatu,
761 0x00000000);
762 spr_register(env, SPR_DBAT2L, "DBAT2L",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_dbat, &spr_write_dbatl,
765 0x00000000);
766 spr_register(env, SPR_DBAT3U, "DBAT3U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_dbat, &spr_write_dbatu,
769 0x00000000);
770 spr_register(env, SPR_DBAT3L, "DBAT3L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_dbat, &spr_write_dbatl,
773 0x00000000);
774 env->nb_BATs += 4;
775 #endif
776 }
777
778 /* BATs 4-7 */
779 static void gen_high_BATs (CPUPPCState *env)
780 {
781 #if !defined(CONFIG_USER_ONLY)
782 spr_register(env, SPR_IBAT4U, "IBAT4U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT4L, "IBAT4L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT5U, "IBAT5U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT5L, "IBAT5L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_IBAT6U, "IBAT6U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat_h, &spr_write_ibatu_h,
801 0x00000000);
802 spr_register(env, SPR_IBAT6L, "IBAT6L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat_h, &spr_write_ibatl_h,
805 0x00000000);
806 spr_register(env, SPR_IBAT7U, "IBAT7U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat_h, &spr_write_ibatu_h,
809 0x00000000);
810 spr_register(env, SPR_IBAT7L, "IBAT7L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_ibat_h, &spr_write_ibatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT4U, "DBAT4U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT4L, "DBAT4L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT5U, "DBAT5U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT5L, "DBAT5L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 spr_register(env, SPR_DBAT6U, "DBAT6U",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat_h, &spr_write_dbatu_h,
833 0x00000000);
834 spr_register(env, SPR_DBAT6L, "DBAT6L",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat_h, &spr_write_dbatl_h,
837 0x00000000);
838 spr_register(env, SPR_DBAT7U, "DBAT7U",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat_h, &spr_write_dbatu_h,
841 0x00000000);
842 spr_register(env, SPR_DBAT7L, "DBAT7L",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_dbat_h, &spr_write_dbatl_h,
845 0x00000000);
846 env->nb_BATs += 4;
847 #endif
848 }
849
850 /* Generic PowerPC time base */
851 static void gen_tbl (CPUPPCState *env)
852 {
853 spr_register(env, SPR_VTBL, "TBL",
854 &spr_read_tbl, SPR_NOACCESS,
855 &spr_read_tbl, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_TBL, "TBL",
858 &spr_read_tbl, SPR_NOACCESS,
859 &spr_read_tbl, &spr_write_tbl,
860 0x00000000);
861 spr_register(env, SPR_VTBU, "TBU",
862 &spr_read_tbu, SPR_NOACCESS,
863 &spr_read_tbu, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_TBU, "TBU",
866 &spr_read_tbu, SPR_NOACCESS,
867 &spr_read_tbu, &spr_write_tbu,
868 0x00000000);
869 }
870
871 /* Softare table search registers */
872 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
873 {
874 #if !defined(CONFIG_USER_ONLY)
875 env->nb_tlb = nb_tlbs;
876 env->nb_ways = nb_ways;
877 env->id_tlbs = 1;
878 env->tlb_type = TLB_6XX;
879 spr_register(env, SPR_DMISS, "DMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_DCMP, "DCMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_HASH1, "HASH1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 0x00000000);
891 spr_register(env, SPR_HASH2, "HASH2",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, SPR_NOACCESS,
894 0x00000000);
895 spr_register(env, SPR_IMISS, "IMISS",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 0x00000000);
899 spr_register(env, SPR_ICMP, "ICMP",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 0x00000000);
903 spr_register(env, SPR_RPA, "RPA",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 #endif
908 }
909
910 /* SPR common to MPC755 and G2 */
911 static void gen_spr_G2_755 (CPUPPCState *env)
912 {
913 /* SGPRs */
914 spr_register(env, SPR_SPRG4, "SPRG4",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 spr_register(env, SPR_SPRG5, "SPRG5",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 spr_register(env, SPR_SPRG6, "SPRG6",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 spr_register(env, SPR_SPRG7, "SPRG7",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 }
931
932 /* SPR common to all 7xx PowerPC implementations */
933 static void gen_spr_7xx (CPUPPCState *env)
934 {
935 /* Breakpoints */
936 /* XXX : not implemented */
937 spr_register_kvm(env, SPR_DABR, "DABR",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 KVM_REG_PPC_DABR, 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_IABR, "IABR",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* Cache management */
947 /* XXX : not implemented */
948 spr_register(env, SPR_ICTC, "ICTC",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* Performance monitors */
953 /* XXX : not implemented */
954 spr_register(env, SPR_MMCR0, "MMCR0",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_MMCR1, "MMCR1",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC1, "PMC1",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC2, "PMC2",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_PMC3, "PMC3",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_PMC4, "PMC4",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_SIAR, "SIAR",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, SPR_NOACCESS,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_UMMCR0, "UMMCR0",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_UMMCR1, "UMMCR1",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_UPMC1, "UPMC1",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_UPMC2, "UPMC2",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_UPMC3, "UPMC3",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_UPMC4, "UPMC4",
1015 &spr_read_ureg, SPR_NOACCESS,
1016 &spr_read_ureg, SPR_NOACCESS,
1017 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_USIAR, "USIAR",
1020 &spr_read_ureg, SPR_NOACCESS,
1021 &spr_read_ureg, SPR_NOACCESS,
1022 0x00000000);
1023 /* External access control */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_EAR, "EAR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 }
1030
1031 static void gen_spr_thrm (CPUPPCState *env)
1032 {
1033 /* Thermal management */
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_THRM1, "THRM1",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_THRM2, "THRM2",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_THRM3, "THRM3",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 }
1050
1051 /* SPR specific to PowerPC 604 implementation */
1052 static void gen_spr_604 (CPUPPCState *env)
1053 {
1054 /* Processor identification */
1055 spr_register(env, SPR_PIR, "PIR",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_pir,
1058 0x00000000);
1059 /* Breakpoints */
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_IABR, "IABR",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
1065 /* XXX : not implemented */
1066 spr_register_kvm(env, SPR_DABR, "DABR",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 KVM_REG_PPC_DABR, 0x00000000);
1070 /* Performance counters */
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_MMCR0, "MMCR0",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_PMC1, "PMC1",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_PMC2, "PMC2",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
1086 /* XXX : not implemented */
1087 spr_register(env, SPR_SIAR, "SIAR",
1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_generic, SPR_NOACCESS,
1090 0x00000000);
1091 /* XXX : not implemented */
1092 spr_register(env, SPR_SDA, "SDA",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, SPR_NOACCESS,
1095 0x00000000);
1096 /* External access control */
1097 /* XXX : not implemented */
1098 spr_register(env, SPR_EAR, "EAR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 }
1103
1104 /* SPR specific to PowerPC 603 implementation */
1105 static void gen_spr_603 (CPUPPCState *env)
1106 {
1107 /* External access control */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_EAR, "EAR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 }
1114
1115 /* SPR specific to PowerPC G2 implementation */
1116 static void gen_spr_G2 (CPUPPCState *env)
1117 {
1118 /* Memory base address */
1119 /* MBAR */
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_MBAR, "MBAR",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* Exception processing */
1126 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* Breakpoints */
1135 /* XXX : not implemented */
1136 spr_register(env, SPR_DABR, "DABR",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_generic, &spr_write_generic,
1139 0x00000000);
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_DABR2, "DABR2",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_IABR, "IABR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_IABR2, "IABR2",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_IBCR, "IBCR",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_DBCR, "DBCR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 }
1166
1167 /* SPR specific to PowerPC 602 implementation */
1168 static void gen_spr_602 (CPUPPCState *env)
1169 {
1170 /* ESA registers */
1171 /* XXX : not implemented */
1172 spr_register(env, SPR_SER, "SER",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_SEBR, "SEBR",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 /* XXX : not implemented */
1182 spr_register(env, SPR_ESASRR, "ESASRR",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* Floating point status */
1187 /* XXX : not implemented */
1188 spr_register(env, SPR_SP, "SP",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_LT, "LT",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 /* Watchdog timer */
1198 /* XXX : not implemented */
1199 spr_register(env, SPR_TCR, "TCR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203 /* Interrupt base */
1204 spr_register(env, SPR_IBR, "IBR",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 /* XXX : not implemented */
1209 spr_register(env, SPR_IABR, "IABR",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_generic,
1212 0x00000000);
1213 }
1214
1215 /* SPR specific to PowerPC 601 implementation */
1216 static void gen_spr_601 (CPUPPCState *env)
1217 {
1218 /* Multiplication/division register */
1219 /* MQ */
1220 spr_register(env, SPR_MQ, "MQ",
1221 &spr_read_generic, &spr_write_generic,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* RTC registers */
1225 spr_register(env, SPR_601_RTCU, "RTCU",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 SPR_NOACCESS, &spr_write_601_rtcu,
1228 0x00000000);
1229 spr_register(env, SPR_601_VRTCU, "RTCU",
1230 &spr_read_601_rtcu, SPR_NOACCESS,
1231 &spr_read_601_rtcu, SPR_NOACCESS,
1232 0x00000000);
1233 spr_register(env, SPR_601_RTCL, "RTCL",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 SPR_NOACCESS, &spr_write_601_rtcl,
1236 0x00000000);
1237 spr_register(env, SPR_601_VRTCL, "RTCL",
1238 &spr_read_601_rtcl, SPR_NOACCESS,
1239 &spr_read_601_rtcl, SPR_NOACCESS,
1240 0x00000000);
1241 /* Timer */
1242 #if 0 /* ? */
1243 spr_register(env, SPR_601_UDECR, "UDECR",
1244 &spr_read_decr, SPR_NOACCESS,
1245 &spr_read_decr, SPR_NOACCESS,
1246 0x00000000);
1247 #endif
1248 /* External access control */
1249 /* XXX : not implemented */
1250 spr_register(env, SPR_EAR, "EAR",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 /* Memory management */
1255 #if !defined(CONFIG_USER_ONLY)
1256 spr_register(env, SPR_IBAT0U, "IBAT0U",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_601_ubat, &spr_write_601_ubatu,
1259 0x00000000);
1260 spr_register(env, SPR_IBAT0L, "IBAT0L",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_601_ubat, &spr_write_601_ubatl,
1263 0x00000000);
1264 spr_register(env, SPR_IBAT1U, "IBAT1U",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_601_ubat, &spr_write_601_ubatu,
1267 0x00000000);
1268 spr_register(env, SPR_IBAT1L, "IBAT1L",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_601_ubat, &spr_write_601_ubatl,
1271 0x00000000);
1272 spr_register(env, SPR_IBAT2U, "IBAT2U",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 &spr_read_601_ubat, &spr_write_601_ubatu,
1275 0x00000000);
1276 spr_register(env, SPR_IBAT2L, "IBAT2L",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_601_ubat, &spr_write_601_ubatl,
1279 0x00000000);
1280 spr_register(env, SPR_IBAT3U, "IBAT3U",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_601_ubat, &spr_write_601_ubatu,
1283 0x00000000);
1284 spr_register(env, SPR_IBAT3L, "IBAT3L",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_601_ubat, &spr_write_601_ubatl,
1287 0x00000000);
1288 env->nb_BATs = 4;
1289 #endif
1290 }
1291
1292 static void gen_spr_74xx (CPUPPCState *env)
1293 {
1294 /* Processor identification */
1295 spr_register(env, SPR_PIR, "PIR",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_pir,
1298 0x00000000);
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_MMCR2, "MMCR2",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_UMMCR2, "UMMCR2",
1306 &spr_read_ureg, SPR_NOACCESS,
1307 &spr_read_ureg, SPR_NOACCESS,
1308 0x00000000);
1309 /* XXX: not implemented */
1310 spr_register(env, SPR_BAMR, "BAMR",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_MSSCR0, "MSSCR0",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* Hardware implementation registers */
1320 /* XXX : not implemented */
1321 spr_register(env, SPR_HID0, "HID0",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_HID1, "HID1",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
1330 /* Altivec */
1331 spr_register(env, SPR_VRSAVE, "VRSAVE",
1332 &spr_read_generic, &spr_write_generic,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_L2CR, "L2CR",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 /* Not strictly an SPR */
1341 vscr_init(env, 0x00010000);
1342 }
1343
1344 static void gen_l3_ctrl (CPUPPCState *env)
1345 {
1346 /* L3CR */
1347 /* XXX : not implemented */
1348 spr_register(env, SPR_L3CR, "L3CR",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 /* L3ITCR0 */
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 /* L3PM */
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_L3PM, "L3PM",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 }
1365
1366 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1367 {
1368 #if !defined(CONFIG_USER_ONLY)
1369 env->nb_tlb = nb_tlbs;
1370 env->nb_ways = nb_ways;
1371 env->id_tlbs = 1;
1372 env->tlb_type = TLB_6XX;
1373 /* XXX : not implemented */
1374 spr_register(env, SPR_PTEHI, "PTEHI",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378 /* XXX : not implemented */
1379 spr_register(env, SPR_PTELO, "PTELO",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383 /* XXX : not implemented */
1384 spr_register(env, SPR_TLBMISS, "TLBMISS",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388 #endif
1389 }
1390
1391 #if !defined(CONFIG_USER_ONLY)
1392 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1393 {
1394 TCGv t0 = tcg_temp_new();
1395
1396 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1397 gen_store_spr(sprn, t0);
1398 tcg_temp_free(t0);
1399 }
1400
1401 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1402 {
1403 TCGv_i32 t0 = tcg_const_i32(sprn);
1404 gen_helper_booke206_tlbflush(cpu_env, t0);
1405 tcg_temp_free_i32(t0);
1406 }
1407
1408 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1409 {
1410 TCGv_i32 t0 = tcg_const_i32(sprn);
1411 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1412 tcg_temp_free_i32(t0);
1413 }
1414 #endif
1415
1416 static void gen_spr_usprgh (CPUPPCState *env)
1417 {
1418 spr_register(env, SPR_USPRG4, "USPRG4",
1419 &spr_read_ureg, SPR_NOACCESS,
1420 &spr_read_ureg, SPR_NOACCESS,
1421 0x00000000);
1422 spr_register(env, SPR_USPRG5, "USPRG5",
1423 &spr_read_ureg, SPR_NOACCESS,
1424 &spr_read_ureg, SPR_NOACCESS,
1425 0x00000000);
1426 spr_register(env, SPR_USPRG6, "USPRG6",
1427 &spr_read_ureg, SPR_NOACCESS,
1428 &spr_read_ureg, SPR_NOACCESS,
1429 0x00000000);
1430 spr_register(env, SPR_USPRG7, "USPRG7",
1431 &spr_read_ureg, SPR_NOACCESS,
1432 &spr_read_ureg, SPR_NOACCESS,
1433 0x00000000);
1434 }
1435
1436 /* PowerPC BookE SPR */
1437 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1438 {
1439 const char *ivor_names[64] = {
1440 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1441 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1442 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1443 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1444 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1445 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1446 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1447 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1448 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1449 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1450 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1451 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1452 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1453 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1454 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1455 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1456 };
1457 #define SPR_BOOKE_IVORxx (-1)
1458 int ivor_sprn[64] = {
1459 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1460 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1461 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1462 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1463 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1464 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1465 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1466 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1467 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1468 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1469 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1470 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1471 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1472 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1473 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1474 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1475 };
1476 int i;
1477
1478 /* Interrupt processing */
1479 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 /* Debug */
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* XXX : not implemented */
1499 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 /* XXX : not implemented */
1504 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 /* XXX : not implemented */
1509 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, &spr_write_40x_dbcr0,
1512 0x00000000);
1513 /* XXX : not implemented */
1514 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518 /* XXX : not implemented */
1519 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523 /* XXX : not implemented */
1524 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_clear,
1527 0x00000000);
1528 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 spr_register(env, SPR_BOOKE_ESR, "ESR",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
1536 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_excp_prefix,
1539 0x00000000);
1540 /* Exception vectors */
1541 for (i = 0; i < 64; i++) {
1542 if (ivor_mask & (1ULL << i)) {
1543 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1544 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1545 exit(1);
1546 }
1547 spr_register(env, ivor_sprn[i], ivor_names[i],
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_excp_vector,
1550 0x00000000);
1551 }
1552 }
1553 spr_register(env, SPR_BOOKE_PID, "PID",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_booke_pid,
1556 0x00000000);
1557 spr_register(env, SPR_BOOKE_TCR, "TCR",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_booke_tcr,
1560 0x00000000);
1561 spr_register(env, SPR_BOOKE_TSR, "TSR",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_booke_tsr,
1564 0x00000000);
1565 /* Timer */
1566 spr_register(env, SPR_DECR, "DECR",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_decr, &spr_write_decr,
1569 0x00000000);
1570 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 SPR_NOACCESS, &spr_write_generic,
1573 0x00000000);
1574 /* SPRGs */
1575 spr_register(env, SPR_USPRG0, "USPRG0",
1576 &spr_read_generic, &spr_write_generic,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579 spr_register(env, SPR_SPRG4, "SPRG4",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 spr_register(env, SPR_SPRG5, "SPRG5",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 spr_register(env, SPR_SPRG6, "SPRG6",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
1591 spr_register(env, SPR_SPRG7, "SPRG7",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595 }
1596
1597 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1598 uint32_t maxsize, uint32_t flags,
1599 uint32_t nentries)
1600 {
1601 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1602 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1603 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1604 flags | nentries;
1605 }
1606
1607 /* BookE 2.06 storage control registers */
1608 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1609 uint32_t *tlbncfg)
1610 {
1611 #if !defined(CONFIG_USER_ONLY)
1612 const char *mas_names[8] = {
1613 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1614 };
1615 int mas_sprn[8] = {
1616 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1617 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1618 };
1619 int i;
1620
1621 /* TLB assist registers */
1622 /* XXX : not implemented */
1623 for (i = 0; i < 8; i++) {
1624 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1625 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1626 uea_write = &spr_write_generic;
1627 }
1628 if (mas_mask & (1 << i)) {
1629 spr_register(env, mas_sprn[i], mas_names[i],
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, uea_write,
1632 0x00000000);
1633 }
1634 }
1635 if (env->nb_pids > 1) {
1636 /* XXX : not implemented */
1637 spr_register(env, SPR_BOOKE_PID1, "PID1",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, &spr_write_booke_pid,
1640 0x00000000);
1641 }
1642 if (env->nb_pids > 2) {
1643 /* XXX : not implemented */
1644 spr_register(env, SPR_BOOKE_PID2, "PID2",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_booke_pid,
1647 0x00000000);
1648 }
1649 /* XXX : not implemented */
1650 spr_register(env, SPR_MMUCFG, "MMUCFG",
1651 SPR_NOACCESS, SPR_NOACCESS,
1652 &spr_read_generic, SPR_NOACCESS,
1653 0x00000000); /* TOFIX */
1654 switch (env->nb_ways) {
1655 case 4:
1656 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, SPR_NOACCESS,
1659 tlbncfg[3]);
1660 /* Fallthru */
1661 case 3:
1662 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, SPR_NOACCESS,
1665 tlbncfg[2]);
1666 /* Fallthru */
1667 case 2:
1668 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, SPR_NOACCESS,
1671 tlbncfg[1]);
1672 /* Fallthru */
1673 case 1:
1674 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, SPR_NOACCESS,
1677 tlbncfg[0]);
1678 /* Fallthru */
1679 case 0:
1680 default:
1681 break;
1682 }
1683 #endif
1684
1685 gen_spr_usprgh(env);
1686 }
1687
1688 /* SPR specific to PowerPC 440 implementation */
1689 static void gen_spr_440 (CPUPPCState *env)
1690 {
1691 /* Cache control */
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DNV0, "DNV0",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DNV1, "DNV1",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_DNV2, "DNV2",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_DNV3, "DNV3",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_DTV0, "DTV0",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_440_DTV1, "DTV1",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_440_DTV2, "DTV2",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_440_DTV3, "DTV3",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_DVLIM, "DVLIM",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_INV0, "INV0",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_INV1, "INV1",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_440_INV2, "INV2",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_INV3, "INV3",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_440_ITV0, "ITV0",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_440_ITV1, "ITV1",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_440_ITV2, "ITV2",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_440_ITV3, "ITV3",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_440_IVLIM, "IVLIM",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* Cache debug */
1783 /* XXX : not implemented */
1784 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* XXX : not implemented */
1789 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, SPR_NOACCESS,
1792 0x00000000);
1793 /* XXX : not implemented */
1794 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, SPR_NOACCESS,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, SPR_NOACCESS,
1802 0x00000000);
1803 /* XXX : not implemented */
1804 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, SPR_NOACCESS,
1807 0x00000000);
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_440_DBDR, "DBDR",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 /* Processor control */
1814 spr_register(env, SPR_4xx_CCR0, "CCR0",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, SPR_NOACCESS,
1821 0x00000000);
1822 /* Storage control */
1823 spr_register(env, SPR_440_MMUCR, "MMUCR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 }
1828
1829 /* SPR shared between PowerPC 40x implementations */
1830 static void gen_spr_40x (CPUPPCState *env)
1831 {
1832 /* Cache */
1833 /* not emulated, as QEMU do not emulate caches */
1834 spr_register(env, SPR_40x_DCCR, "DCCR",
1835 SPR_NOACCESS, SPR_NOACCESS,
1836 &spr_read_generic, &spr_write_generic,
1837 0x00000000);
1838 /* not emulated, as QEMU do not emulate caches */
1839 spr_register(env, SPR_40x_ICCR, "ICCR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
1843 /* not emulated, as QEMU do not emulate caches */
1844 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, SPR_NOACCESS,
1847 0x00000000);
1848 /* Exception */
1849 spr_register(env, SPR_40x_DEAR, "DEAR",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 spr_register(env, SPR_40x_ESR, "ESR",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_40x_EVPR, "EVPR",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_excp_prefix,
1860 0x00000000);
1861 spr_register(env, SPR_40x_SRR2, "SRR2",
1862 &spr_read_generic, &spr_write_generic,
1863 &spr_read_generic, &spr_write_generic,
1864 0x00000000);
1865 spr_register(env, SPR_40x_SRR3, "SRR3",
1866 &spr_read_generic, &spr_write_generic,
1867 &spr_read_generic, &spr_write_generic,
1868 0x00000000);
1869 /* Timers */
1870 spr_register(env, SPR_40x_PIT, "PIT",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_40x_pit, &spr_write_40x_pit,
1873 0x00000000);
1874 spr_register(env, SPR_40x_TCR, "TCR",
1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, &spr_write_booke_tcr,
1877 0x00000000);
1878 spr_register(env, SPR_40x_TSR, "TSR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_booke_tsr,
1881 0x00000000);
1882 }
1883
1884 /* SPR specific to PowerPC 405 implementation */
1885 static void gen_spr_405 (CPUPPCState *env)
1886 {
1887 /* MMU */
1888 spr_register(env, SPR_40x_PID, "PID",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 spr_register(env, SPR_4xx_CCR0, "CCR0",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00700000);
1896 /* Debug interface */
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_40x_dbcr0,
1901 0x00000000);
1902 /* XXX : not implemented */
1903 spr_register(env, SPR_405_DBCR1, "DBCR1",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_40x_DBSR, "DBSR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_clear,
1911 /* Last reset was system reset */
1912 0x00000300);
1913 /* XXX : not implemented */
1914 spr_register(env, SPR_40x_DAC1, "DAC1",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
1917 0x00000000);
1918 spr_register(env, SPR_40x_DAC2, "DAC2",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
1922 /* XXX : not implemented */
1923 spr_register(env, SPR_405_DVC1, "DVC1",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_405_DVC2, "DVC2",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_40x_IAC1, "IAC1",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 spr_register(env, SPR_40x_IAC2, "IAC2",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 /* XXX : not implemented */
1942 spr_register(env, SPR_405_IAC3, "IAC3",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_405_IAC4, "IAC4",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
1951 /* Storage control */
1952 /* XXX: TODO: not implemented */
1953 spr_register(env, SPR_405_SLER, "SLER",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_40x_sler,
1956 0x00000000);
1957 spr_register(env, SPR_40x_ZPR, "ZPR",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_generic,
1960 0x00000000);
1961 /* XXX : not implemented */
1962 spr_register(env, SPR_405_SU0R, "SU0R",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 /* SPRG */
1967 spr_register(env, SPR_USPRG0, "USPRG0",
1968 &spr_read_ureg, SPR_NOACCESS,
1969 &spr_read_ureg, SPR_NOACCESS,
1970 0x00000000);
1971 spr_register(env, SPR_SPRG4, "SPRG4",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_generic,
1974 0x00000000);
1975 spr_register(env, SPR_SPRG5, "SPRG5",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 spr_register(env, SPR_SPRG6, "SPRG6",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 spr_read_generic, &spr_write_generic,
1982 0x00000000);
1983 spr_register(env, SPR_SPRG7, "SPRG7",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 gen_spr_usprgh(env);
1988 }
1989
1990 /* SPR shared between PowerPC 401 & 403 implementations */
1991 static void gen_spr_401_403 (CPUPPCState *env)
1992 {
1993 /* Time base */
1994 spr_register(env, SPR_403_VTBL, "TBL",
1995 &spr_read_tbl, SPR_NOACCESS,
1996 &spr_read_tbl, SPR_NOACCESS,
1997 0x00000000);
1998 spr_register(env, SPR_403_TBL, "TBL",
1999 SPR_NOACCESS, SPR_NOACCESS,
2000 SPR_NOACCESS, &spr_write_tbl,
2001 0x00000000);
2002 spr_register(env, SPR_403_VTBU, "TBU",
2003 &spr_read_tbu, SPR_NOACCESS,
2004 &spr_read_tbu, SPR_NOACCESS,
2005 0x00000000);
2006 spr_register(env, SPR_403_TBU, "TBU",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 SPR_NOACCESS, &spr_write_tbu,
2009 0x00000000);
2010 /* Debug */
2011 /* not emulated, as QEMU do not emulate caches */
2012 spr_register(env, SPR_403_CDBCR, "CDBCR",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 }
2017
2018 /* SPR specific to PowerPC 401 implementation */
2019 static void gen_spr_401 (CPUPPCState *env)
2020 {
2021 /* Debug interface */
2022 /* XXX : not implemented */
2023 spr_register(env, SPR_40x_DBCR0, "DBCR",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_40x_dbcr0,
2026 0x00000000);
2027 /* XXX : not implemented */
2028 spr_register(env, SPR_40x_DBSR, "DBSR",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_clear,
2031 /* Last reset was system reset */
2032 0x00000300);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_40x_DAC1, "DAC",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_40x_IAC1, "IAC",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* Storage control */
2044 /* XXX: TODO: not implemented */
2045 spr_register(env, SPR_405_SLER, "SLER",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_40x_sler,
2048 0x00000000);
2049 /* not emulated, as QEMU never does speculative access */
2050 spr_register(env, SPR_40x_SGR, "SGR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0xFFFFFFFF);
2054 /* not emulated, as QEMU do not emulate caches */
2055 spr_register(env, SPR_40x_DCWR, "DCWR",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 }
2060
2061 static void gen_spr_401x2 (CPUPPCState *env)
2062 {
2063 gen_spr_401(env);
2064 spr_register(env, SPR_40x_PID, "PID",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068 spr_register(env, SPR_40x_ZPR, "ZPR",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 }
2073
2074 /* SPR specific to PowerPC 403 implementation */
2075 static void gen_spr_403 (CPUPPCState *env)
2076 {
2077 /* Debug interface */
2078 /* XXX : not implemented */
2079 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, &spr_write_40x_dbcr0,
2082 0x00000000);
2083 /* XXX : not implemented */
2084 spr_register(env, SPR_40x_DBSR, "DBSR",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_clear,
2087 /* Last reset was system reset */
2088 0x00000300);
2089 /* XXX : not implemented */
2090 spr_register(env, SPR_40x_DAC1, "DAC1",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
2094 /* XXX : not implemented */
2095 spr_register(env, SPR_40x_DAC2, "DAC2",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
2099 /* XXX : not implemented */
2100 spr_register(env, SPR_40x_IAC1, "IAC1",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
2104 /* XXX : not implemented */
2105 spr_register(env, SPR_40x_IAC2, "IAC2",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0x00000000);
2109 }
2110
2111 static void gen_spr_403_real (CPUPPCState *env)
2112 {
2113 spr_register(env, SPR_403_PBL1, "PBL1",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_403_pbr, &spr_write_403_pbr,
2116 0x00000000);
2117 spr_register(env, SPR_403_PBU1, "PBU1",
2118 SPR_NOACCESS, SPR_NOACCESS,
2119 &spr_read_403_pbr, &spr_write_403_pbr,
2120 0x00000000);
2121 spr_register(env, SPR_403_PBL2, "PBL2",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_403_pbr, &spr_write_403_pbr,
2124 0x00000000);
2125 spr_register(env, SPR_403_PBU2, "PBU2",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_403_pbr, &spr_write_403_pbr,
2128 0x00000000);
2129 }
2130
2131 static void gen_spr_403_mmu (CPUPPCState *env)
2132 {
2133 /* MMU */
2134 spr_register(env, SPR_40x_PID, "PID",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 spr_register(env, SPR_40x_ZPR, "ZPR",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 }
2143
2144 /* SPR specific to PowerPC compression coprocessor extension */
2145 static void gen_spr_compress (CPUPPCState *env)
2146 {
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_401_SKR, "SKR",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152 }
2153
2154 #if defined (TARGET_PPC64)
2155 /* SPR specific to PowerPC 620 */
2156 static void gen_spr_620 (CPUPPCState *env)
2157 {
2158 /* Processor identification */
2159 spr_register(env, SPR_PIR, "PIR",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_pir,
2162 0x00000000);
2163 spr_register(env, SPR_ASR, "ASR",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_asr, &spr_write_asr,
2166 0x00000000);
2167 /* Breakpoints */
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_IABR, "IABR",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_DABR, "DABR",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_SIAR, "SIAR",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, SPR_NOACCESS,
2182 0x00000000);
2183 /* XXX : not implemented */
2184 spr_register(env, SPR_SDA, "SDA",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, SPR_NOACCESS,
2187 0x00000000);
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_PMC1R, "PMC1",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, SPR_NOACCESS,
2192 0x00000000);
2193 spr_register(env, SPR_620_PMC1W, "PMC1",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 SPR_NOACCESS, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_PMC2R, "PMC2",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, SPR_NOACCESS,
2201 0x00000000);
2202 spr_register(env, SPR_620_PMC2W, "PMC2",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 SPR_NOACCESS, &spr_write_generic,
2205 0x00000000);
2206 /* XXX : not implemented */
2207 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2208 SPR_NOACCESS, SPR_NOACCESS,
2209 &spr_read_generic, SPR_NOACCESS,
2210 0x00000000);
2211 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 SPR_NOACCESS, &spr_write_generic,
2214 0x00000000);
2215 /* External access control */
2216 /* XXX : not implemented */
2217 spr_register(env, SPR_EAR, "EAR",
2218 SPR_NOACCESS, SPR_NOACCESS,
2219 &spr_read_generic, &spr_write_generic,
2220 0x00000000);
2221 #if 0 // XXX: check this
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_620_PMR0, "PMR0",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_620_PMR1, "PMR1",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_620_PMR2, "PMR2",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_620_PMR3, "PMR3",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_620_PMR4, "PMR4",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_620_PMR5, "PMR5",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_620_PMR6, "PMR6",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_620_PMR7, "PMR7",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_620_PMR8, "PMR8",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 /* XXX : not implemented */
2268 spr_register(env, SPR_620_PMR9, "PMR9",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 /* XXX : not implemented */
2273 spr_register(env, SPR_620_PMRA, "PMR10",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_620_PMRB, "PMR11",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_620_PMRC, "PMR12",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_620_PMRD, "PMR13",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* XXX : not implemented */
2293 spr_register(env, SPR_620_PMRE, "PMR14",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* XXX : not implemented */
2298 spr_register(env, SPR_620_PMRF, "PMR15",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
2302 #endif
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 /* XXX : not implemented */
2309 spr_register(env, SPR_620_L2CR, "L2CR",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_620_L2SR, "L2SR",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 }
2319 #endif /* defined (TARGET_PPC64) */
2320
2321 static void gen_spr_5xx_8xx (CPUPPCState *env)
2322 {
2323 /* Exception processing */
2324 spr_register_kvm(env, SPR_DSISR, "DSISR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 KVM_REG_PPC_DSISR, 0x00000000);
2328 spr_register_kvm(env, SPR_DAR, "DAR",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 KVM_REG_PPC_DAR, 0x00000000);
2332 /* Timer */
2333 spr_register(env, SPR_DECR, "DECR",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_decr, &spr_write_decr,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_EIE, "EIE",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_EID, "EID",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_NRI, "NRI",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_CMPA, "CMPA",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPB, "CMPB",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_CMPC, "CMPC",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_CMPD, "CMPD",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_ECR, "ECR",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_DER, "DER",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_CMPE, "CMPE",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_CMPF, "CMPF",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_MPC_CMPG, "CMPG",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_CMPH, "CMPH",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_BAR, "BAR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_DPDR, "DPDR",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_IMMR, "IMMR",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 }
2438
2439 static void gen_spr_5xx (CPUPPCState *env)
2440 {
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 }
2547
2548 static void gen_spr_8xx (CPUPPCState *env)
2549 {
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 /* XXX : not implemented */
2641 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645 /* XXX : not implemented */
2646 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* XXX : not implemented */
2651 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655 /* XXX : not implemented */
2656 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 /* XXX : not implemented */
2661 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665 /* XXX : not implemented */
2666 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
2670 /* XXX : not implemented */
2671 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
2675 }
2676
2677 // XXX: TODO
2678 /*
2679 * AMR => SPR 29 (Power 2.04)
2680 * CTRL => SPR 136 (Power 2.04)
2681 * CTRL => SPR 152 (Power 2.04)
2682 * SCOMC => SPR 276 (64 bits ?)
2683 * SCOMD => SPR 277 (64 bits ?)
2684 * TBU40 => SPR 286 (Power 2.04 hypv)
2685 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2686 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2687 * HDSISR => SPR 306 (Power 2.04 hypv)
2688 * HDAR => SPR 307 (Power 2.04 hypv)
2689 * PURR => SPR 309 (Power 2.04 hypv)
2690 * HDEC => SPR 310 (Power 2.04 hypv)
2691 * HIOR => SPR 311 (hypv)
2692 * RMOR => SPR 312 (970)
2693 * HRMOR => SPR 313 (Power 2.04 hypv)
2694 * HSRR0 => SPR 314 (Power 2.04 hypv)
2695 * HSRR1 => SPR 315 (Power 2.04 hypv)
2696 * LPCR => SPR 316 (970)
2697 * LPIDR => SPR 317 (970)
2698 * EPR => SPR 702 (Power 2.04 emb)
2699 * perf => 768-783 (Power 2.04)
2700 * perf => 784-799 (Power 2.04)
2701 * PPR => SPR 896 (Power 2.04)
2702 * EPLC => SPR 947 (Power 2.04 emb)
2703 * EPSC => SPR 948 (Power 2.04 emb)
2704 * DABRX => 1015 (Power 2.04 hypv)
2705 * FPECR => SPR 1022 (?)
2706 * ... and more (thermal management, performance counters, ...)
2707 */
2708
2709 /*****************************************************************************/
2710 /* Exception vectors models */
2711 static void init_excp_4xx_real (CPUPPCState *env)
2712 {
2713 #if !defined(CONFIG_USER_ONLY)
2714 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2715 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2716 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2717 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2718 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2719 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2720 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2721 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2722 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2723 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2724 env->hreset_excp_prefix = 0x00000000UL;
2725 env->ivor_mask = 0x0000FFF0UL;
2726 env->ivpr_mask = 0xFFFF0000UL;
2727 /* Hardware reset vector */
2728 env->hreset_vector = 0xFFFFFFFCUL;
2729 #endif
2730 }
2731
2732 static void init_excp_4xx_softmmu (CPUPPCState *env)
2733 {
2734 #if !defined(CONFIG_USER_ONLY)
2735 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2736 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2737 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2738 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2739 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2740 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2741 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2742 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2743 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2744 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2745 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2746 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2747 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2748 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2749 env->hreset_excp_prefix = 0x00000000UL;
2750 env->ivor_mask = 0x0000FFF0UL;
2751 env->ivpr_mask = 0xFFFF0000UL;
2752 /* Hardware reset vector */
2753 env->hreset_vector = 0xFFFFFFFCUL;
2754 #endif
2755 }
2756
2757 static void init_excp_MPC5xx (CPUPPCState *env)
2758 {
2759 #if !defined(CONFIG_USER_ONLY)
2760 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2761 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2762 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2763 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2764 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2765 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2767 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2768 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2769 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2770 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2771 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2772 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2773 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2774 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2775 env->hreset_excp_prefix = 0x00000000UL;
2776 env->ivor_mask = 0x0000FFF0UL;
2777 env->ivpr_mask = 0xFFFF0000UL;
2778 /* Hardware reset vector */
2779 env->hreset_vector = 0xFFFFFFFCUL;
2780 #endif
2781 }
2782
2783 static void init_excp_MPC8xx (CPUPPCState *env)
2784 {
2785 #if !defined(CONFIG_USER_ONLY)
2786 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2787 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2788 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2789 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2790 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2791 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2792 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2793 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2794 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2795 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2796 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2797 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2798 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2799 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2800 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2801 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2802 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2803 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2804 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2805 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2806 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2807 env->hreset_excp_prefix = 0x00000000UL;
2808 env->ivor_mask = 0x0000FFF0UL;
2809 env->ivpr_mask = 0xFFFF0000UL;
2810 /* Hardware reset vector */
2811 env->hreset_vector = 0xFFFFFFFCUL;
2812 #endif
2813 }
2814
2815 static void init_excp_G2 (CPUPPCState *env)
2816 {
2817 #if !defined(CONFIG_USER_ONLY)
2818 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2819 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2820 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2821 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2822 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2823 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2824 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2825 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2826 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2827 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2828 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2829 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2830 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2831 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2832 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2833 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2834 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2835 env->hreset_excp_prefix = 0x00000000UL;
2836 /* Hardware reset vector */
2837 env->hreset_vector = 0xFFFFFFFCUL;
2838 #endif
2839 }
2840
2841 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2842 {
2843 #if !defined(CONFIG_USER_ONLY)
2844 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2845 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2864 env->hreset_excp_prefix = 0x00000000UL;
2865 env->ivor_mask = 0x0000FFF7UL;
2866 env->ivpr_mask = ivpr_mask;
2867 /* Hardware reset vector */
2868 env->hreset_vector = 0xFFFFFFFCUL;
2869 #endif
2870 }
2871
2872 static void init_excp_BookE (CPUPPCState *env)
2873 {
2874 #if !defined(CONFIG_USER_ONLY)
2875 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2883 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2884 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2885 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2886 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2887 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2888 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2889 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2890 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2891 env->hreset_excp_prefix = 0x00000000UL;
2892 env->ivor_mask = 0x0000FFE0UL;
2893 env->ivpr_mask = 0xFFFF0000UL;
2894 /* Hardware reset vector */
2895 env->hreset_vector = 0xFFFFFFFCUL;
2896 #endif
2897 }
2898
2899 static void init_excp_601 (CPUPPCState *env)
2900 {
2901 #if !defined(CONFIG_USER_ONLY)
2902 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2910 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2911 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2912 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2913 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2914 env->hreset_excp_prefix = 0xFFF00000UL;
2915 /* Hardware reset vector */
2916 env->hreset_vector = 0x00000100UL;
2917 #endif
2918 }
2919
2920 static void init_excp_602 (CPUPPCState *env)
2921 {
2922 #if !defined(CONFIG_USER_ONLY)
2923 /* XXX: exception prefix has a special behavior on 602 */
2924 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2925 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2926 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2927 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2928 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2929 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2930 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2931 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2932 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2933 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2934 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2935 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2936 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2937 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2938 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2939 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2940 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2941 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2942 env->hreset_excp_prefix = 0xFFF00000UL;
2943 /* Hardware reset vector */
2944 env->hreset_vector = 0xFFFFFFFCUL;
2945 #endif
2946 }
2947
2948 static void init_excp_603 (CPUPPCState *env)
2949 {
2950 #if !defined(CONFIG_USER_ONLY)
2951 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2952 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2953 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2954 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2955 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2956 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2957 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2958 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2959 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2960 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2961 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2962 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2963 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2964 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2965 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2966 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2967 env->hreset_excp_prefix = 0x00000000UL;
2968 /* Hardware reset vector */
2969 env->hreset_vector = 0xFFFFFFFCUL;
2970 #endif
2971 }
2972
2973 static void init_excp_604 (CPUPPCState *env)
2974 {
2975 #if !defined(CONFIG_USER_ONLY)
2976 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2977 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2978 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2979 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2980 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2981 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2982 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2983 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2984 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2985 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2986 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2987 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2988 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2989 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2990 env->hreset_excp_prefix = 0xFFF00000UL;
2991 /* Hardware reset vector */
2992 env->hreset_vector = 0x00000100UL;
2993 #endif
2994 }
2995
2996 #if defined(TARGET_PPC64)
2997 static void init_excp_620 (CPUPPCState *env)
2998 {
2999 #if !defined(CONFIG_USER_ONLY)
3000 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3001 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3002 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3003 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3004 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3005 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3006 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3007 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3008 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3009 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3010 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3011 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3012 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3013 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3014 env->hreset_excp_prefix = 0xFFF00000UL;
3015 /* Hardware reset vector */
3016 env->hreset_vector = 0x0000000000000100ULL;
3017 #endif
3018 }
3019 #endif /* defined(TARGET_PPC64) */
3020
3021 static void init_excp_7x0 (CPUPPCState *env)
3022 {
3023 #if !defined(CONFIG_USER_ONLY)
3024 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3025 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3026 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3027 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3033 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3034 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3035 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3036 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3037 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3038 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3039 env->hreset_excp_prefix = 0x00000000UL;
3040 /* Hardware reset vector */
3041 env->hreset_vector = 0xFFFFFFFCUL;
3042 #endif
3043 }
3044
3045 static void init_excp_750cl (CPUPPCState *env)
3046 {
3047 #if !defined(CONFIG_USER_ONLY)
3048 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3049 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3050 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3051 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3052 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3053 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3054 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3055 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3056 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3057 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3058 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3059 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3060 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3061 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3062 env->hreset_excp_prefix = 0x00000000UL;
3063 /* Hardware reset vector */
3064 env->hreset_vector = 0xFFFFFFFCUL;
3065 #endif
3066 }
3067
3068 static void init_excp_750cx (CPUPPCState *env)
3069 {
3070 #if !defined(CONFIG_USER_ONLY)
3071 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3072 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3073 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3074 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3075 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3076 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3077 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3078 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3079 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3080 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3081 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3082 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3083 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3084 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3085 env->hreset_excp_prefix = 0x00000000UL;
3086 /* Hardware reset vector */
3087 env->hreset_vector = 0xFFFFFFFCUL;
3088 #endif
3089 }
3090
3091 /* XXX: Check if this is correct */
3092 static void init_excp_7x5 (CPUPPCState *env)
3093 {
3094 #if !defined(CONFIG_USER_ONLY)
3095 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3096 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3097 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3098 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3099 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3100 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3101 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3102 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3103 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3104 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3105 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3106 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3107 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3108 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3109 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3110 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3111 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3112 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3113 env->hreset_excp_prefix = 0x00000000UL;
3114 /* Hardware reset vector */
3115 env->hreset_vector = 0xFFFFFFFCUL;
3116 #endif
3117 }
3118
3119 static void init_excp_7400 (CPUPPCState *env)
3120 {
3121 #if !defined(CONFIG_USER_ONLY)
3122 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3123 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3124 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3125 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3126 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3127 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3128 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3129 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3130 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3131 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3132 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3133 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3134 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3135 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3136 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3137 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3138 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3139 env->hreset_excp_prefix = 0x00000000UL;
3140 /* Hardware reset vector */
3141 env->hreset_vector = 0xFFFFFFFCUL;
3142 #endif
3143 }
3144
3145 static void init_excp_7450 (CPUPPCState *env)
3146 {
3147 #if !defined(CONFIG_USER_ONLY)
3148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3149 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3150 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3151 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3152 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3153 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3154 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3155 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3156 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3158 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3159 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3160 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3161 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3162 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3163 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3164 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3165 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3166 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3167 env->hreset_excp_prefix = 0x00000000UL;
3168 /* Hardware reset vector */
3169 env->hreset_vector = 0xFFFFFFFCUL;
3170 #endif
3171 }
3172
3173 #if defined (TARGET_PPC64)
3174 static void init_excp_970 (CPUPPCState *env)
3175 {
3176 #if !defined(CONFIG_USER_ONLY)
3177 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3178 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3179 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3180 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3181 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3182 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3183 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3184 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3185 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3186 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3187 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3188 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3189 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3190 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3191 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3192 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3193 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3194 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3195 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3196 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3197 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3198 /* Hardware reset vector */
3199 env->hreset_vector = 0x0000000000000100ULL;
3200 #endif
3201 }
3202
3203 static void init_excp_POWER7 (CPUPPCState *env)
3204 {
3205 #if !defined(CONFIG_USER_ONLY)
3206 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3207 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3208 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3209 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3210 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3211 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3212 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3213 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3214 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3215 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3216 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3217 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3218 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3219 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3220 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3221 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3222 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3223 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3224 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3225 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3226 env->hreset_excp_prefix = 0;
3227 /* Hardware reset vector */
3228 env->hreset_vector = 0x0000000000000100ULL;
3229 #endif
3230 }
3231 #endif
3232
3233 /*****************************************************************************/
3234 /* Power management enable checks */
3235 static int check_pow_none (CPUPPCState *env)
3236 {
3237 return 0;
3238 }
3239
3240 static int check_pow_nocheck (CPUPPCState *env)
3241 {
3242 return 1;
3243 }
3244
3245 static int check_pow_hid0 (CPUPPCState *env)
3246 {
3247 if (env->spr[SPR_HID0] & 0x00E00000)
3248 return 1;
3249
3250 return 0;
3251 }
3252
3253 static int check_pow_hid0_74xx (CPUPPCState *env)
3254 {
3255 if (env->spr[SPR_HID0] & 0x00600000)
3256 return 1;
3257
3258 return 0;
3259 }
3260
3261 /*****************************************************************************/
3262 /* PowerPC implementations definitions */
3263
3264 #define POWERPC_FAMILY(_name) \
3265 static void \
3266 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3267 \
3268 static const TypeInfo \
3269 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3270 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3271 .parent = TYPE_POWERPC_CPU, \
3272 .abstract = true, \
3273 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3274 }; \
3275 \
3276 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3277 { \
3278 type_register_static( \
3279 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3280 } \
3281 \
3282 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3283 \
3284 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3285
3286 static void init_proc_401 (CPUPPCState *env)
3287 {
3288 gen_spr_40x(env);
3289 gen_spr_401_403(env);
3290 gen_spr_401(env);
3291 init_excp_4xx_real(env);
3292 env->dcache_line_size = 32;
3293 env->icache_line_size = 32;
3294 /* Allocate hardware IRQ controller */
3295 ppc40x_irq_init(env);
3296
3297 SET_FIT_PERIOD(12, 16, 20, 24);
3298 SET_WDT_PERIOD(16, 20, 24, 28);
3299 }
3300
3301 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3302 {
3303 DeviceClass *dc = DEVICE_CLASS(oc);
3304 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3305
3306 dc->desc = "PowerPC 401";
3307 pcc->init_proc = init_proc_401;
3308 pcc->check_pow = check_pow_nocheck;
3309 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3310 PPC_WRTEE | PPC_DCR |
3311 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3312 PPC_CACHE_DCBZ |
3313 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3314 PPC_4xx_COMMON | PPC_40x_EXCP;
3315 pcc->insns_flags2 = PPC_NONE;
3316 pcc->msr_mask = 0x00000000000FD201ULL;
3317 pcc->mmu_model = POWERPC_MMU_REAL;
3318 pcc->excp_model = POWERPC_EXCP_40x;
3319 pcc->bus_model = PPC_FLAGS_INPUT_401;
3320 pcc->bfd_mach = bfd_mach_ppc_403;
3321 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3322 POWERPC_FLAG_BUS_CLK;
3323 }
3324
3325 static void init_proc_401x2 (CPUPPCState *env)
3326 {
3327 gen_spr_40x(env);
3328 gen_spr_401_403(env);
3329 gen_spr_401x2(env);
3330 gen_spr_compress(env);
3331 /* Memory management */
3332 #if !defined(CONFIG_USER_ONLY)
3333 env->nb_tlb = 64;
3334 env->nb_ways = 1;
3335 env->id_tlbs = 0;
3336 env->tlb_type = TLB_EMB;
3337 #endif
3338 init_excp_4xx_softmmu(env);
3339 env->dcache_line_size = 32;
3340 env->icache_line_size = 32;
3341 /* Allocate hardware IRQ controller */
3342 ppc40x_irq_init(env);
3343
3344 SET_FIT_PERIOD(12, 16, 20, 24);
3345 SET_WDT_PERIOD(16, 20, 24, 28);
3346 }
3347
3348 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3349 {
3350 DeviceClass *dc = DEVICE_CLASS(oc);
3351 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3352
3353 dc->desc = "PowerPC 401x2";
3354 pcc->init_proc = init_proc_401x2;
3355 pcc->check_pow = check_pow_nocheck;
3356 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3357 PPC_DCR | PPC_WRTEE |
3358 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3359 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3360 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3361 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3362 PPC_4xx_COMMON | PPC_40x_EXCP;
3363 pcc->insns_flags2 = PPC_NONE;
3364 pcc->msr_mask = 0x00000000001FD231ULL;
3365 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3366 pcc->excp_model = POWERPC_EXCP_40x;
3367 pcc->bus_model = PPC_FLAGS_INPUT_401;
3368 pcc->bfd_mach = bfd_mach_ppc_403;
3369 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3370 POWERPC_FLAG_BUS_CLK;
3371 }
3372
3373 static void init_proc_401x3 (CPUPPCState *env)
3374 {
3375 gen_spr_40x(env);
3376 gen_spr_401_403(env);
3377 gen_spr_401(env);
3378 gen_spr_401x2(env);
3379 gen_spr_compress(env);
3380 init_excp_4xx_softmmu(env);
3381 env->dcache_line_size = 32;
3382 env->icache_line_size = 32;
3383 /* Allocate hardware IRQ controller */
3384 ppc40x_irq_init(env);
3385
3386 SET_FIT_PERIOD(12, 16, 20, 24);
3387 SET_WDT_PERIOD(16, 20, 24, 28);
3388 }
3389
3390 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3391 {
3392 DeviceClass *dc = DEVICE_CLASS(oc);
3393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3394
3395 dc->desc = "PowerPC 401x3";
3396 pcc->init_proc = init_proc_401x3;
3397 pcc->check_pow = check_pow_nocheck;
3398 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3399 PPC_DCR | PPC_WRTEE |
3400 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3401 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3402 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3403 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3404 PPC_4xx_COMMON | PPC_40x_EXCP;
3405 pcc->insns_flags2 = PPC_NONE;
3406 pcc->msr_mask = 0x00000000001FD631ULL;
3407 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3408 pcc->excp_model = POWERPC_EXCP_40x;
3409 pcc->bus_model = PPC_FLAGS_INPUT_401;
3410 pcc->bfd_mach = bfd_mach_ppc_403;
3411 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3412 POWERPC_FLAG_BUS_CLK;
3413 }
3414
3415 static void init_proc_IOP480 (CPUPPCState *env)
3416 {
3417 gen_spr_40x(env);
3418 gen_spr_401_403(env);
3419 gen_spr_401x2(env);
3420 gen_spr_compress(env);
3421 /* Memory management */
3422 #if !defined(CONFIG_USER_ONLY)
3423 env->nb_tlb = 64;
3424 env->nb_ways = 1;
3425 env->id_tlbs = 0;
3426 env->tlb_type = TLB_EMB;
3427 #endif
3428 init_excp_4xx_softmmu(env);
3429 env->dcache_line_size = 32;
3430 env->icache_line_size = 32;
3431 /* Allocate hardware IRQ controller */
3432 ppc40x_irq_init(env);
3433
3434 SET_FIT_PERIOD(8, 12, 16, 20);
3435 SET_WDT_PERIOD(16, 20, 24, 28);
3436 }
3437
3438 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3439 {
3440 DeviceClass *dc = DEVICE_CLASS(oc);
3441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3442
3443 dc->desc = "IOP480";
3444 pcc->init_proc = init_proc_IOP480;
3445 pcc->check_pow = check_pow_nocheck;
3446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3447 PPC_DCR | PPC_WRTEE |
3448 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3449 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3450 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3451 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3452 PPC_4xx_COMMON | PPC_40x_EXCP;
3453 pcc->insns_flags2 = PPC_NONE;
3454 pcc->msr_mask = 0x00000000001FD231ULL;
3455 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3456 pcc->excp_model = POWERPC_EXCP_40x;
3457 pcc->bus_model = PPC_FLAGS_INPUT_401;
3458 pcc->bfd_mach = bfd_mach_ppc_403;
3459 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3460 POWERPC_FLAG_BUS_CLK;
3461 }
3462
3463 static void init_proc_403 (CPUPPCState *env)
3464 {
3465 gen_spr_40x(env);
3466 gen_spr_401_403(env);
3467 gen_spr_403(env);
3468 gen_spr_403_real(env);
3469 init_excp_4xx_real(env);
3470 env->dcache_line_size = 32;
3471 env->icache_line_size = 32;
3472 /* Allocate hardware IRQ controller */
3473 ppc40x_irq_init(env);
3474
3475 SET_FIT_PERIOD(8, 12, 16, 20);
3476 SET_WDT_PERIOD(16, 20, 24, 28);
3477 }
3478
3479 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3480 {
3481 DeviceClass *dc = DEVICE_CLASS(oc);
3482 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3483
3484 dc->desc = "PowerPC 403";
3485 pcc->init_proc = init_proc_403;
3486 pcc->check_pow = check_pow_nocheck;
3487 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3488 PPC_DCR | PPC_WRTEE |
3489 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3490 PPC_CACHE_DCBZ |
3491 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3492 PPC_4xx_COMMON | PPC_40x_EXCP;
3493 pcc->insns_flags2 = PPC_NONE;
3494 pcc->msr_mask = 0x000000000007D00DULL;
3495 pcc->mmu_model = POWERPC_MMU_REAL;
3496 pcc->excp_model = POWERPC_EXCP_40x;
3497 pcc->bus_model = PPC_FLAGS_INPUT_401;
3498 pcc->bfd_mach = bfd_mach_ppc_403;
3499 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3500 POWERPC_FLAG_BUS_CLK;
3501 }
3502
3503 static void init_proc_403GCX (CPUPPCState *env)
3504 {
3505 gen_spr_40x(env);
3506 gen_spr_401_403(env);
3507 gen_spr_403(env);
3508 gen_spr_403_real(env);
3509 gen_spr_403_mmu(env);
3510 /* Bus access control */
3511 /* not emulated, as QEMU never does speculative access */
3512 spr_register(env, SPR_40x_SGR, "SGR",
3513 SPR_NOACCESS, SPR_NOACCESS,
3514 &spr_read_generic, &spr_write_generic,
3515 0xFFFFFFFF);
3516 /* not emulated, as QEMU do not emulate caches */
3517 spr_register(env, SPR_40x_DCWR, "DCWR",
3518 SPR_NOACCESS, SPR_NOACCESS,
3519 &spr_read_generic, &spr_write_generic,
3520 0x00000000);
3521 /* Memory management */
3522 #if !defined(CONFIG_USER_ONLY)
3523 env->nb_tlb = 64;
3524 env->nb_ways = 1;
3525 env->id_tlbs = 0;
3526 env->tlb_type = TLB_EMB;
3527 #endif
3528 init_excp_4xx_softmmu(env);
3529 env->dcache_line_size = 32;
3530 env->icache_line_size = 32;
3531 /* Allocate hardware IRQ controller */
3532 ppc40x_irq_init(env);
3533
3534 SET_FIT_PERIOD(8, 12, 16, 20);
3535 SET_WDT_PERIOD(16, 20, 24, 28);
3536 }
3537
3538 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3539 {
3540 DeviceClass *dc = DEVICE_CLASS(oc);
3541 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3542
3543 dc->desc = "PowerPC 403 GCX";
3544 pcc->init_proc = init_proc_403GCX;
3545 pcc->check_pow = check_pow_nocheck;
3546 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3547 PPC_DCR | PPC_WRTEE |
3548 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3549 PPC_CACHE_DCBZ |
3550 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3551 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3552 PPC_4xx_COMMON | PPC_40x_EXCP;
3553 pcc->insns_flags2 = PPC_NONE;
3554 pcc->msr_mask = 0x000000000007D00DULL;
3555 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3556 pcc->excp_model = POWERPC_EXCP_40x;
3557 pcc->bus_model = PPC_FLAGS_INPUT_401;
3558 pcc->bfd_mach = bfd_mach_ppc_403;
3559 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3560 POWERPC_FLAG_BUS_CLK;
3561 }
3562
3563 static void init_proc_405 (CPUPPCState *env)
3564 {
3565 /* Time base */
3566 gen_tbl(env);
3567 gen_spr_40x(env);
3568 gen_spr_405(env);
3569 /* Bus access control */
3570 /* not emulated, as QEMU never does speculative access */
3571 spr_register(env, SPR_40x_SGR, "SGR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_generic,
3574 0xFFFFFFFF);
3575 /* not emulated, as QEMU do not emulate caches */
3576 spr_register(env, SPR_40x_DCWR, "DCWR",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* Memory management */
3581 #if !defined(CONFIG_USER_ONLY)
3582 env->nb_tlb = 64;
3583 env->nb_ways = 1;
3584 env->id_tlbs = 0;
3585 env->tlb_type = TLB_EMB;
3586 #endif
3587 init_excp_4xx_softmmu(env);
3588 env->dcache_line_size = 32;
3589 env->icache_line_size = 32;
3590 /* Allocate hardware IRQ controller */
3591 ppc40x_irq_init(env);
3592
3593 SET_FIT_PERIOD(8, 12, 16, 20);
3594 SET_WDT_PERIOD(16, 20, 24, 28);
3595 }
3596
3597 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3598 {
3599 DeviceClass *dc = DEVICE_CLASS(oc);
3600 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3601
3602 dc->desc = "PowerPC 405";
3603 pcc->init_proc = init_proc_405;
3604 pcc->check_pow = check_pow_nocheck;
3605 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3606 PPC_DCR | PPC_WRTEE |
3607 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3608 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3609 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3610 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3611 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3612 pcc->insns_flags2 = PPC_NONE;
3613 pcc->msr_mask = 0x000000000006E630ULL;
3614 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3615 pcc->excp_model = POWERPC_EXCP_40x;
3616 pcc->bus_model = PPC_FLAGS_INPUT_405;
3617 pcc->bfd_mach = bfd_mach_ppc_403;
3618 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3619 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3620 }
3621
3622 static void init_proc_440EP (CPUPPCState *env)
3623 {
3624 /* Time base */
3625 gen_tbl(env);
3626 gen_spr_BookE(env, 0x000000000000FFFFULL);
3627 gen_spr_440(env);
3628 gen_spr_usprgh(env);
3629 /* Processor identification */
3630 spr_register(env, SPR_BOOKE_PIR, "PIR",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_pir,
3633 0x00000000);
3634 /* XXX : not implemented */
3635 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 /* XXX : not implemented */
3645 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 /* XXX : not implemented */
3650 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 /* XXX : not implemented */
3655 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3656 SPR_NOACCESS, SPR_NOACCESS,
3657 &spr_read_generic, &spr_write_generic,
3658 0x00000000);
3659 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_generic,
3666 0x00000000);
3667 /* XXX : not implemented */
3668 spr_register(env, SPR_440_CCR1, "CCR1",
3669 SPR_NOACCESS, SPR_NOACCESS,
3670 &spr_read_generic, &spr_write_generic,
3671 0x00000000);
3672 /* Memory management */
3673 #if !defined(CONFIG_USER_ONLY)
3674 env->nb_tlb = 64;
3675 env->nb_ways = 1;
3676 env->id_tlbs = 0;
3677 env->tlb_type = TLB_EMB;
3678 #endif
3679 init_excp_BookE(env);
3680 env->dcache_line_size = 32;
3681 env->icache_line_size = 32;
3682 ppc40x_irq_init(env);
3683
3684 SET_FIT_PERIOD(12, 16, 20, 24);
3685 SET_WDT_PERIOD(20, 24, 28, 32);
3686 }
3687
3688 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3689 {
3690 DeviceClass *dc = DEVICE_CLASS(oc);
3691 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3692
3693 dc->desc = "PowerPC 440 EP";
3694 pcc->init_proc = init_proc_440EP;
3695 pcc->check_pow = check_pow_nocheck;
3696 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3697 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3698 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3699 PPC_FLOAT_STFIWX |
3700 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3701 PPC_CACHE | PPC_CACHE_ICBI |
3702 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3703 PPC_MEM_TLBSYNC | PPC_MFTB |
3704 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3705 PPC_440_SPEC;
3706 pcc->insns_flags2 = PPC_NONE;
3707 pcc->msr_mask = 0x000000000006FF30ULL;
3708 pcc->mmu_model = POWERPC_MMU_BOOKE;
3709 pcc->excp_model = POWERPC_EXCP_BOOKE;
3710 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3711 pcc->bfd_mach = bfd_mach_ppc_403;
3712 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3713 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3714 }
3715
3716 static void init_proc_440GP (CPUPPCState *env)
3717 {
3718 /* Time base */
3719 gen_tbl(env);
3720 gen_spr_BookE(env, 0x000000000000FFFFULL);
3721 gen_spr_440(env);
3722 gen_spr_usprgh(env);
3723 /* Processor identification */
3724 spr_register(env, SPR_BOOKE_PIR, "PIR",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_pir,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* XXX : not implemented */
3734 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3735 SPR_NOACCESS, SPR_NOACCESS,
3736 &spr_read_generic, &spr_write_generic,
3737 0x00000000);
3738 /* XXX : not implemented */
3739 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_generic,
3742 0x00000000);
3743 /* XXX : not implemented */
3744 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3745 SPR_NOACCESS, SPR_NOACCESS,
3746 &spr_read_generic, &spr_write_generic,
3747 0x00000000);
3748 /* Memory management */
3749 #if !defined(CONFIG_USER_ONLY)
3750 env->nb_tlb = 64;
3751 env->nb_ways = 1;
3752 env->id_tlbs = 0;
3753 env->tlb_type = TLB_EMB;
3754 #endif
3755 init_excp_BookE(env);
3756 env->dcache_line_size = 32;
3757 env->icache_line_size = 32;
3758 /* XXX: TODO: allocate internal IRQ controller */
3759
3760 SET_FIT_PERIOD(12, 16, 20, 24);
3761 SET_WDT_PERIOD(20, 24, 28, 32);
3762 }
3763
3764 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3765 {
3766 DeviceClass *dc = DEVICE_CLASS(oc);
3767 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3768
3769 dc->desc = "PowerPC 440 GP";
3770 pcc->init_proc = init_proc_440GP;
3771 pcc->check_pow = check_pow_nocheck;
3772 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3773 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3774 PPC_CACHE | PPC_CACHE_ICBI |
3775 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3776 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3777 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3778 PPC_440_SPEC;
3779 pcc->insns_flags2 = PPC_NONE;
3780 pcc->msr_mask = 0x000000000006FF30ULL;
3781 pcc->mmu_model = POWERPC_MMU_BOOKE;
3782 pcc->excp_model = POWERPC_EXCP_BOOKE;
3783 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3784 pcc->bfd_mach = bfd_mach_ppc_403;
3785 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3786 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3787 }
3788
3789 static void init_proc_440x4 (CPUPPCState *env)
3790 {
3791 /* Time base */
3792 gen_tbl(env);
3793 gen_spr_BookE(env, 0x000000000000FFFFULL);
3794 gen_spr_440(env);
3795 gen_spr_usprgh(env);
3796 /* Processor identification */
3797 spr_register(env, SPR_BOOKE_PIR, "PIR",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_pir,
3800 0x00000000);
3801 /* XXX : not implemented */
3802 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3803 SPR_NOACCESS, SPR_NOACCESS,
3804 &spr_read_generic, &spr_write_generic,
3805 0x00000000);
3806 /* XXX : not implemented */
3807 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3808 SPR_NOACCESS, SPR_NOACCESS,
3809 &spr_read_generic, &spr_write_generic,
3810 0x00000000);
3811 /* XXX : not implemented */
3812 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3813 SPR_NOACCESS, SPR_NOACCESS,
3814 &spr_read_generic, &spr_write_generic,
3815 0x00000000);
3816 /* XXX : not implemented */
3817 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3818 SPR_NOACCESS, SPR_NOACCESS,
3819 &spr_read_generic, &spr_write_generic,
3820 0x00000000);
3821 /* Memory management */
3822 #if !defined(CONFIG_USER_ONLY)
3823 env->nb_tlb = 64;
3824 env->nb_ways = 1;
3825 env->id_tlbs = 0;
3826 env->tlb_type = TLB_EMB;
3827 #endif
3828 init_excp_BookE(env);
3829 env->dcache_line_size = 32;
3830 env->icache_line_size = 32;
3831 /* XXX: TODO: allocate internal IRQ controller */
3832
3833 SET_FIT_PERIOD(12, 16, 20, 24);
3834 SET_WDT_PERIOD(20, 24, 28, 32);
3835 }
3836
3837 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3838 {
3839 DeviceClass *dc = DEVICE_CLASS(oc);
3840 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3841
3842 dc->desc = "PowerPC 440x4";
3843 pcc->init_proc = init_proc_440x4;
3844 pcc->check_pow = check_pow_nocheck;
3845 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3846 PPC_DCR | PPC_WRTEE |
3847 PPC_CACHE | PPC_CACHE_ICBI |
3848 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3849 PPC_MEM_TLBSYNC | PPC_MFTB |
3850 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3851 PPC_440_SPEC;
3852 pcc->insns_flags2 = PPC_NONE;
3853 pcc->msr_mask = 0x000000000006FF30ULL;
3854 pcc->mmu_model = POWERPC_MMU_BOOKE;
3855 pcc->excp_model = POWERPC_EXCP_BOOKE;
3856 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3857 pcc->bfd_mach = bfd_mach_ppc_403;
3858 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3859 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3860 }
3861
3862 static void init_proc_440x5 (CPUPPCState *env)
3863 {
3864 /* Time base */
3865 gen_tbl(env);
3866 gen_spr_BookE(env, 0x000000000000FFFFULL);
3867 gen_spr_440(env);
3868 gen_spr_usprgh(env);
3869 /* Processor identification */
3870 spr_register(env, SPR_BOOKE_PIR, "PIR",
3871 SPR_NOACCESS, SPR_NOACCESS,
3872 &spr_read_generic, &spr_write_pir,
3873 0x00000000);
3874 /* XXX : not implemented */
3875 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
3878 0x00000000);
3879 /* XXX : not implemented */
3880 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 /* XXX : not implemented */
3885 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 /* XXX : not implemented */
3890 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3904 SPR_NOACCESS, SPR_NOACCESS,
3905 &spr_read_generic, &spr_write_generic,
3906 0x00000000);
3907 /* XXX : not implemented */
3908 spr_register(env, SPR_440_CCR1, "CCR1",
3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
3912 /* Memory management */
3913 #if !defined(CONFIG_USER_ONLY)
3914 env->nb_tlb = 64;
3915 env->nb_ways = 1;
3916 env->id_tlbs = 0;
3917 env->tlb_type = TLB_EMB;
3918 #endif
3919 init_excp_BookE(env);
3920 env->dcache_line_size = 32;
3921 env->icache_line_size = 32;
3922 ppc40x_irq_init(env);
3923
3924 SET_FIT_PERIOD(12, 16, 20, 24);
3925 SET_WDT_PERIOD(20, 24, 28, 32);
3926 }
3927
3928 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3929 {
3930 DeviceClass *dc = DEVICE_CLASS(oc);
3931 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3932
3933 dc->desc = "PowerPC 440x5";
3934 pcc->init_proc = init_proc_440x5;
3935 pcc->check_pow = check_pow_nocheck;
3936 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3937 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3938 PPC_CACHE | PPC_CACHE_ICBI |
3939 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3940 PPC_MEM_TLBSYNC | PPC_MFTB |
3941 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3942 PPC_440_SPEC;
3943 pcc->insns_flags2 = PPC_NONE;
3944 pcc->msr_mask = 0x000000000006FF30ULL;
3945 pcc->mmu_model = POWERPC_MMU_BOOKE;
3946 pcc->excp_model = POWERPC_EXCP_BOOKE;
3947 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3948 pcc->bfd_mach = bfd_mach_ppc_403;
3949 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3950 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3951 }
3952
3953 static void init_proc_460 (CPUPPCState *env)
3954 {
3955 /* Time base */
3956 gen_tbl(env);
3957 gen_spr_BookE(env, 0x000000000000FFFFULL);
3958 gen_spr_440(env);
3959 gen_spr_usprgh(env);
3960 /* Processor identification */
3961 spr_register(env, SPR_BOOKE_PIR, "PIR",
3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_pir,
3964 0x00000000);
3965 /* XXX : not implemented */
3966 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, &spr_write_generic,
3969 0x00000000);
3970 /* XXX : not implemented */
3971 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 /* XXX : not implemented */
3981 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
3985 /* XXX : not implemented */
3986 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3991 SPR_NOACCESS, SPR_NOACCESS,
3992 &spr_read_generic, &spr_write_generic,
3993 0x00000000);
3994 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3995 SPR_NOACCESS, SPR_NOACCESS,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
3998 /* XXX : not implemented */
3999 spr_register(env, SPR_440_CCR1, "CCR1",
4000 SPR_NOACCESS, SPR_NOACCESS,
4001 &spr_read_generic, &spr_write_generic,
4002 0x00000000);
4003 /* XXX : not implemented */
4004 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4005 &spr_read_generic, &spr_write_generic,
4006 &spr_read_generic, &spr_write_generic,
4007 0x00000000);
4008 /* Memory management */
4009 #if !defined(CONFIG_USER_ONLY)
4010 env->nb_tlb = 64;
4011 env->nb_ways = 1;
4012 env->id_tlbs = 0;
4013 env->tlb_type = TLB_EMB;
4014 #endif
4015 init_excp_BookE(env);
4016 env->dcache_line_size = 32;
4017 env->icache_line_size = 32;
4018 /* XXX: TODO: allocate internal IRQ controller */
4019
4020 SET_FIT_PERIOD(12, 16, 20, 24);
4021 SET_WDT_PERIOD(20, 24, 28, 32);
4022 }
4023
4024 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4025 {
4026 DeviceClass *dc = DEVICE_CLASS(oc);
4027 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4028
4029 dc->desc = "PowerPC 460 (guessed)";
4030 pcc->init_proc = init_proc_460;
4031 pcc->check_pow = check_pow_nocheck;
4032 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4033 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4034 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4035 PPC_CACHE | PPC_CACHE_ICBI |
4036 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4037 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4038 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4039 PPC_440_SPEC;
4040 pcc->insns_flags2 = PPC_NONE;
4041 pcc->msr_mask = 0x000000000006FF30ULL;
4042 pcc->mmu_model = POWERPC_MMU_BOOKE;
4043 pcc->excp_model = POWERPC_EXCP_BOOKE;
4044 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4045 pcc->bfd_mach = bfd_mach_ppc_403;
4046 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4047 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4048 }
4049
4050 static void init_proc_460F (CPUPPCState *env)
4051 {
4052 /* Time base */
4053 gen_tbl(env);
4054 gen_spr_BookE(env, 0x000000000000FFFFULL);
4055 gen_spr_440(env);
4056 gen_spr_usprgh(env);
4057 /* Processor identification */
4058 spr_register(env, SPR_BOOKE_PIR, "PIR",
4059 SPR_NOACCESS, SPR_NOACCESS,
4060 &spr_read_generic, &spr_write_pir,
4061 0x00000000);
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* XXX : not implemented */
4078 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 /* XXX : not implemented */
4083 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4084 SPR_NOACCESS, SPR_NOACCESS,
4085 &spr_read_generic, &spr_write_generic,
4086 0x00000000);
4087 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4088 SPR_NOACCESS, SPR_NOACCESS,
4089 &spr_read_generic, &spr_write_generic,
4090 0x00000000);
4091 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* XXX : not implemented */
4096 spr_register(env, SPR_440_CCR1, "CCR1",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 /* XXX : not implemented */
4101 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4102 &spr_read_generic, &spr_write_generic,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
4105 /* Memory management */
4106 #if !defined(CONFIG_USER_ONLY)
4107 env->nb_tlb = 64;
4108 env->nb_ways = 1;
4109 env->id_tlbs = 0;
4110 env->tlb_type = TLB_EMB;
4111 #endif
4112 init_excp_BookE(env);
4113 env->dcache_line_size = 32;
4114 env->icache_line_size = 32;
4115 /* XXX: TODO: allocate internal IRQ controller */
4116
4117 SET_FIT_PERIOD(12, 16, 20, 24);
4118 SET_WDT_PERIOD(20, 24, 28, 32);
4119 }
4120
4121 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4122 {
4123 DeviceClass *dc = DEVICE_CLASS(oc);
4124 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4125
4126 dc->desc = "PowerPC 460F (guessed)";
4127 pcc->init_proc = init_proc_460F;
4128 pcc->check_pow = check_pow_nocheck;
4129 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4130 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4131 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4132 PPC_FLOAT_STFIWX | PPC_MFTB |
4133 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4134 PPC_WRTEE | PPC_MFAPIDI |
4135 PPC_CACHE | PPC_CACHE_ICBI |
4136 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4137 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4138 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4139 PPC_440_SPEC;
4140 pcc->insns_flags2 = PPC_NONE;
4141 pcc->msr_mask = 0x000000000006FF30ULL;
4142 pcc->mmu_model = POWERPC_MMU_BOOKE;
4143 pcc->excp_model = POWERPC_EXCP_BOOKE;
4144 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4145 pcc->bfd_mach = bfd_mach_ppc_403;
4146 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4147 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4148 }
4149
4150 static void init_proc_MPC5xx (CPUPPCState *env)
4151 {
4152 /* Time base */
4153 gen_tbl(env);
4154 gen_spr_5xx_8xx(env);
4155 gen_spr_5xx(env);
4156 init_excp_MPC5xx(env);
4157 env->dcache_line_size = 32;
4158 env->icache_line_size = 32;
4159 /* XXX: TODO: allocate internal IRQ controller */
4160 }
4161
4162 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4163 {
4164 DeviceClass *dc = DEVICE_CLASS(oc);
4165 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4166
4167 dc->desc = "Freescale 5xx cores (aka RCPU)";
4168 pcc->init_proc = init_proc_MPC5xx;
4169 pcc->check_pow = check_pow_none;
4170 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4171 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4172 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4173 PPC_MFTB;
4174 pcc->insns_flags2 = PPC_NONE;
4175 pcc->msr_mask = 0x000000000001FF43ULL;
4176 pcc->mmu_model = POWERPC_MMU_REAL;
4177 pcc->excp_model = POWERPC_EXCP_603;
4178 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4179 pcc->bfd_mach = bfd_mach_ppc_505;
4180 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4181 POWERPC_FLAG_BUS_CLK;
4182 }
4183
4184 static void init_proc_MPC8xx (CPUPPCState *env)
4185 {
4186 /* Time base */
4187 gen_tbl(env);
4188 gen_spr_5xx_8xx(env);
4189 gen_spr_8xx(env);
4190 init_excp_MPC8xx(env);
4191 env->dcache_line_size = 32;
4192 env->icache_line_size = 32;
4193 /* XXX: TODO: allocate internal IRQ controller */
4194 }
4195
4196 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4197 {
4198 DeviceClass *dc = DEVICE_CLASS(oc);
4199 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4200
4201 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4202 pcc->init_proc = init_proc_MPC8xx;
4203 pcc->check_pow = check_pow_none;
4204 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4205 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4206 PPC_CACHE_ICBI | PPC_MFTB;
4207 pcc->insns_flags2 = PPC_NONE;
4208 pcc->msr_mask = 0x000000000001F673ULL;
4209 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4210 pcc->excp_model = POWERPC_EXCP_603;
4211 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4212 pcc->bfd_mach = bfd_mach_ppc_860;
4213 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4214 POWERPC_FLAG_BUS_CLK;
4215 }
4216
4217 /* Freescale 82xx cores (aka PowerQUICC-II) */
4218
4219 static void init_proc_G2 (CPUPPCState *env)
4220 {
4221 gen_spr_ne_601(env);
4222 gen_spr_G2_755(env);
4223 gen_spr_G2(env);
4224 /* Time base */
4225 gen_tbl(env);
4226 /* External access control */
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_EAR, "EAR",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
4232 /* Hardware implementation register */
4233 /* XXX : not implemented */
4234 spr_register(env, SPR_HID0, "HID0",
4235 SPR_NOACCESS, SPR_NOACCESS,
4236 &spr_read_generic, &spr_write_generic,
4237 0x00000000);
4238 /* XXX : not implemented */
4239 spr_register(env, SPR_HID1, "HID1",
4240 SPR_NOACCESS, SPR_NOACCESS,
4241 &spr_read_generic, &spr_write_generic,
4242 0x00000000);
4243 /* XXX : not implemented */
4244 spr_register(env, SPR_HID2, "HID2",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_generic,
4247 0x00000000);
4248 /* Memory management */
4249 gen_low_BATs(env);
4250 gen_high_BATs(env);
4251 gen_6xx_7xx_soft_tlb(env, 64, 2);
4252 init_excp_G2(env);
4253 env->dcache_line_size = 32;
4254 env->icache_line_size = 32;
4255 /* Allocate hardware IRQ controller */
4256 ppc6xx_irq_init(env);
4257 }
4258
4259 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4260 {
4261 DeviceClass *dc = DEVICE_CLASS(oc);
4262 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4263
4264 dc->desc = "PowerPC G2";
4265 pcc->init_proc = init_proc_G2;
4266 pcc->check_pow = check_pow_hid0;
4267 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4268 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4269 PPC_FLOAT_STFIWX |
4270 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4271 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4272 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4273 PPC_SEGMENT | PPC_EXTERN;
4274 pcc->insns_flags2 = PPC_NONE;
4275 pcc->msr_mask = 0x000000000006FFF2ULL;
4276 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4277 pcc->excp_model = POWERPC_EXCP_G2;
4278 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4279 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4280 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4281 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4282 }
4283
4284 static void init_proc_G2LE (CPUPPCState *env)
4285 {
4286 gen_spr_ne_601(env);
4287 gen_spr_G2_755(env);
4288 gen_spr_G2(env);
4289 /* Time base */
4290 gen_tbl(env);
4291 /* External access control */
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_EAR, "EAR",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
4297 /* Hardware implementation register */
4298 /* XXX : not implemented */
4299 spr_register(env, SPR_HID0, "HID0",
4300 SPR_NOACCESS, SPR_NOACCESS,
4301 &spr_read_generic, &spr_write_generic,
4302 0x00000000);
4303 /* XXX : not implemented */
4304 spr_register(env, SPR_HID1, "HID1",
4305 SPR_NOACCESS, SPR_NOACCESS,
4306 &spr_read_generic, &spr_write_generic,
4307 0x00000000);
4308 /* XXX : not implemented */
4309 spr_register(env, SPR_HID2, "HID2",
4310 SPR_NOACCESS, SPR_NOACCESS,
4311 &spr_read_generic, &spr_write_generic,
4312 0x00000000);
4313 /* Memory management */
4314 gen_low_BATs(env);
4315 gen_high_BATs(env);
4316 gen_6xx_7xx_soft_tlb(env, 64, 2);
4317 init_excp_G2(env);
4318 env->dcache_line_size = 32;
4319 env->icache_line_size = 32;
4320 /* Allocate hardware IRQ controller */
4321 ppc6xx_irq_init(env);
4322 }
4323
4324 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4325 {
4326 DeviceClass *dc = DEVICE_CLASS(oc);
4327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4328
4329 dc->desc = "PowerPC G2LE";
4330 pcc->init_proc = init_proc_G2LE;
4331 pcc->check_pow = check_pow_hid0;
4332 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4333 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4334 PPC_FLOAT_STFIWX |
4335 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4336 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4337 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4338 PPC_SEGMENT | PPC_EXTERN;
4339 pcc->insns_flags2 = PPC_NONE;
4340 pcc->msr_mask = 0x000000000007FFF3ULL;
4341 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4342 pcc->excp_model = POWERPC_EXCP_G2;
4343 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4344 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4345 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4346 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4347 }
4348
4349 static void init_proc_e200 (CPUPPCState *env)
4350 {
4351 /* Time base */
4352 gen_tbl(env);
4353 gen_spr_BookE(env, 0x000000070000FFFFULL);
4354 /* XXX : not implemented */
4355 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4356 &spr_read_spefscr, &spr_write_spefscr,
4357 &spr_read_spefscr, &spr_write_spefscr,
4358 0x00000000);
4359 /* Memory management */
4360 gen_spr_BookE206(env, 0x0000005D, NULL);
4361 /* XXX : not implemented */
4362 spr_register(env, SPR_HID0, "HID0",
4363 SPR_NOACCESS, SPR_NOACCESS,
4364 &spr_read_generic, &spr_write_generic,
4365 0x00000000);
4366 /* XXX : not implemented */
4367 spr_register(env, SPR_HID1, "HID1",
4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_generic,
4370 0x00000000);
4371 /* XXX : not implemented */
4372 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
4376 /* XXX : not implemented */
4377 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4378 SPR_NOACCESS, SPR_NOACCESS,
4379 &spr_read_generic, &spr_write_generic,
4380 0x00000000);
4381 /* XXX : not implemented */
4382 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4383 SPR_NOACCESS, SPR_NOACCESS,
4384 &spr_read_generic, &spr_write_generic,
4385 0x00000000);
4386 /* XXX : not implemented */
4387 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4388 SPR_NOACCESS, SPR_NOACCESS,
4389 &spr_read_generic, &spr_write_generic,
4390 0x00000000);
4391 /* XXX : not implemented */
4392 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4393 SPR_NOACCESS, SPR_NOACCESS,
4394 &spr_read_generic, &spr_write_generic,
4395 0x00000000);
4396 /* XXX : not implemented */
4397 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4398 SPR_NOACCESS, SPR_NOACCESS,
4399 &spr_read_generic, &spr_write_generic,
4400 0x00000000);
4401 /* XXX : not implemented */
4402 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4403 SPR_NOACCESS, SPR_NOACCESS,
4404 &spr_read_generic, &spr_write_generic,
4405 0x00000000);
4406 /* XXX : not implemented */
4407 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, &spr_write_generic,
4410 0x00000000);
4411 /* XXX : not implemented */
4412 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000);
4416 /* XXX : not implemented */
4417 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4418 SPR_NOACCESS, SPR_NOACCESS,
4419 &spr_read_generic, &spr_write_generic,
4420 0x00000000);
4421 /* XXX : not implemented */
4422 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4423 SPR_NOACCESS, SPR_NOACCESS,
4424 &spr_read_generic, &spr_write_generic,
4425 0x00000000);
4426 /* XXX : not implemented */
4427 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4428 SPR_NOACCESS, SPR_NOACCESS,
4429 &spr_read_generic, &spr_write_generic,
4430 0x00000000);
4431 /* XXX : not implemented */
4432 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4433 SPR_NOACCESS, SPR_NOACCESS,
4434 &spr_read_generic, &spr_write_generic,
4435 0x00000000); /* TOFIX */
4436 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4437 SPR_NOACCESS, SPR_NOACCESS,
4438 &spr_read_generic, &spr_write_generic,
4439 0x00000000);
4440 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4441 SPR_NOACCESS, SPR_NOACCESS,
4442 &spr_read_generic, &spr_write_generic,
4443 0x00000000);
4444 #if !defined(CONFIG_USER_ONLY)
4445 env->nb_tlb = 64;
4446 env->nb_ways = 1;
4447 env->id_tlbs = 0;
4448 env->tlb_type = TLB_EMB;
4449 #endif
4450 init_excp_e200(env, 0xFFFF0000UL);
4451 env->dcache_line_size = 32;
4452 env->icache_line_size = 32;
4453 /* XXX: TODO: allocate internal IRQ controller */
4454 }
4455
4456 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4457 {
4458 DeviceClass *dc = DEVICE_CLASS(oc);
4459 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4460
4461 dc->desc = "e200 core";
4462 pcc->init_proc = init_proc_e200;
4463 pcc->check_pow = check_pow_hid0;
4464 /* XXX: unimplemented instructions:
4465 * dcblc
4466 * dcbtlst
4467 * dcbtstls
4468 * icblc
4469 * icbtls
4470 * tlbivax
4471 * all SPE multiply-accumulate instructions
4472 */
4473 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4474 PPC_SPE | PPC_SPE_SINGLE |
4475 PPC_WRTEE | PPC_RFDI |
4476 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4477 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4478 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4479 PPC_BOOKE;
4480 pcc->insns_flags2 = PPC_NONE;
4481 pcc->msr_mask = 0x000000000606FF30ULL;
4482 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4483 pcc->excp_model = POWERPC_EXCP_BOOKE;
4484 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4485 pcc->bfd_mach = bfd_mach_ppc_860;
4486 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4487 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4488 POWERPC_FLAG_BUS_CLK;
4489 }
4490
4491 static void init_proc_e300 (CPUPPCState *env)
4492 {
4493 gen_spr_ne_601(env);
4494 gen_spr_603(env);
4495 /* Time base */
4496 gen_tbl(env);
4497 /* hardware implementation registers */
4498 /* XXX : not implemented */
4499 spr_register(env, SPR_HID0, "HID0",
4500 SPR_NOACCESS, SPR_NOACCESS,
4501 &spr_read_generic, &spr_write_generic,
4502 0x00000000);
4503 /* XXX : not implemented */
4504 spr_register(env, SPR_HID1, "HID1",
4505 SPR_NOACCESS, SPR_NOACCESS,
4506 &spr_read_generic, &spr_write_generic,
4507 0x00000000);
4508 /* XXX : not implemented */
4509 spr_register(env, SPR_HID2, "HID2",
4510 SPR_NOACCESS, SPR_NOACCESS,
4511 &spr_read_generic, &spr_write_generic,
4512 0x00000000);
4513 /* Memory management */
4514 gen_low_BATs(env);
4515 gen_high_BATs(env);
4516 gen_6xx_7xx_soft_tlb(env, 64, 2);
4517 init_excp_603(env);
4518 env->dcache_line_size = 32;
4519 env->icache_line_size = 32;
4520 /* Allocate hardware IRQ controller */
4521 ppc6xx_irq_init(env);
4522 }
4523
4524 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4525 {
4526 DeviceClass *dc = DEVICE_CLASS(oc);
4527 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4528
4529 dc->desc = "e300 core";
4530 pcc->init_proc = init_proc_e300;
4531 pcc->check_pow = check_pow_hid0;
4532 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4533 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4534 PPC_FLOAT_STFIWX |
4535 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4536 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4537 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4538 PPC_SEGMENT | PPC_EXTERN;
4539 pcc->insns_flags2 = PPC_NONE;
4540 pcc->msr_mask = 0x000000000007FFF3ULL;
4541 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4542 pcc->excp_model = POWERPC_EXCP_603;
4543 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4544 pcc->bfd_mach = bfd_mach_ppc_603;
4545 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4546 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4547 }
4548
4549 #if !defined(CONFIG_USER_ONLY)
4550 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4551 {
4552 TCGv val = tcg_temp_new();
4553 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4554 gen_store_spr(SPR_BOOKE_MAS3, val);
4555 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4556 gen_store_spr(SPR_BOOKE_MAS7, val);
4557 tcg_temp_free(val);
4558 }
4559
4560 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4561 {
4562 TCGv mas7 = tcg_temp_new();
4563 TCGv mas3 = tcg_temp_new();
4564 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4565 tcg_gen_shli_tl(mas7, mas7, 32);
4566 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4567 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4568 tcg_temp_free(mas3);
4569 tcg_temp_free(mas7);
4570 }
4571
4572 #endif
4573
4574 enum fsl_e500_version {
4575 fsl_e500v1,
4576 fsl_e500v2,
4577 fsl_e500mc,
4578 fsl_e5500,
4579 };
4580
4581 static void init_proc_e500 (CPUPPCState *env, int version)
4582 {
4583 uint32_t tlbncfg[2];
4584 uint64_t ivor_mask;
4585 uint64_t ivpr_mask = 0xFFFF0000ULL;
4586 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4587 | 0x0020; /* 32 kb */
4588 #if !defined(CONFIG_USER_ONLY)
4589 int i;
4590 #endif
4591
4592 /* Time base */
4593 gen_tbl(env);
4594 /*
4595 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4596 * complain when accessing them.
4597 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4598 */
4599 switch (version) {
4600 case fsl_e500v1:
4601 case fsl_e500v2:
4602 default:
4603 ivor_mask = 0x0000000F0000FFFFULL;
4604 break;
4605 case fsl_e500mc:
4606 case fsl_e5500:
4607 ivor_mask = 0x000003FE0000FFFFULL;
4608 break;
4609 }
4610 gen_spr_BookE(env, ivor_mask);
4611 /* Processor identification */
4612 spr_register(env, SPR_BOOKE_PIR, "PIR",
4613 SPR_NOACCESS, SPR_NOACCESS,
4614 &spr_read_generic, &spr_write_pir,
4615 0x00000000);
4616 /* XXX : not implemented */
4617 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4618 &spr_read_spefscr, &spr_write_spefscr,
4619 &spr_read_spefscr, &spr_write_spefscr,
4620 0x00000000);
4621 #if !defined(CONFIG_USER_ONLY)
4622 /* Memory management */
4623 env->nb_pids = 3;
4624 env->nb_ways = 2;
4625 env->id_tlbs = 0;
4626 switch (version) {
4627 case fsl_e500v1:
4628 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4629 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4630 break;
4631 case fsl_e500v2:
4632 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4633 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4634 break;
4635 case fsl_e500mc:
4636 case fsl_e5500:
4637 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4638 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4639 break;
4640 default:
4641 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4642 }
4643 #endif
4644 /* Cache sizes */
4645 switch (version) {
4646 case fsl_e500v1:
4647 case fsl_e500v2:
4648 env->dcache_line_size = 32;
4649 env->icache_line_size = 32;
4650 break;
4651 case fsl_e500mc:
4652 case fsl_e5500:
4653 env->dcache_line_size = 64;
4654 env->icache_line_size = 64;
4655 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4656 break;
4657 default:
4658 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4659 }
4660 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4661 /* XXX : not implemented */
4662 spr_register(env, SPR_HID0, "HID0",
4663 SPR_NOACCESS, SPR_NOACCESS,
4664 &spr_read_generic, &spr_write_generic,
4665 0x00000000);
4666 /* XXX : not implemented */
4667 spr_register(env, SPR_HID1, "HID1",
4668 SPR_NOACCESS, SPR_NOACCESS,
4669 &spr_read_generic, &spr_write_generic,
4670 0x00000000);
4671 /* XXX : not implemented */
4672 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4673 SPR_NOACCESS, SPR_NOACCESS,
4674 &spr_read_generic, &spr_write_generic,
4675 0x00000000);
4676 /* XXX : not implemented */
4677 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4678 SPR_NOACCESS, SPR_NOACCESS,
4679 &spr_read_generic, &spr_write_generic,
4680 0x00000000);
4681 /* XXX : not implemented */
4682 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4683 SPR_NOACCESS, SPR_NOACCESS,
4684 &spr_read_generic, &spr_write_generic,
4685 0x00000000);
4686 /* XXX : not implemented */
4687 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4688 SPR_NOACCESS, SPR_NOACCESS,
4689 &spr_read_generic, &spr_write_generic,
4690 0x00000000);
4691 /* XXX : not implemented */
4692 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4693 SPR_NOACCESS, SPR_NOACCESS,
4694 &spr_read_generic, &spr_write_generic,
4695 0x00000000);
4696 /* XXX : not implemented */
4697 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4698 SPR_NOACCESS, SPR_NOACCESS,
4699 &spr_read_generic, &spr_write_generic,
4700 0x00000000);
4701 /* XXX : not implemented */
4702 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4703 SPR_NOACCESS, SPR_NOACCESS,
4704 &spr_read_generic, &spr_write_generic,
4705 l1cfg0);
4706 /* XXX : not implemented */
4707 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4708 SPR_NOACCESS, SPR_NOACCESS,
4709 &spr_read_generic, &spr_write_e500_l1csr0,
4710 0x00000000);
4711 /* XXX : not implemented */
4712 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4713 SPR_NOACCESS, SPR_NOACCESS,
4714 &spr_read_generic, &spr_write_generic,
4715 0x00000000);
4716 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4717 SPR_NOACCESS, SPR_NOACCESS,
4718 &spr_read_generic, &spr_write_generic,
4719 0x00000000);
4720 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4721 SPR_NOACCESS, SPR_NOACCESS,
4722 &spr_read_generic, &spr_write_generic,
4723 0x00000000);
4724 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4725 SPR_NOACCESS, SPR_NOACCESS,
4726 &spr_read_generic, &spr_write_booke206_mmucsr0,
4727 0x00000000);
4728 spr_register(env, SPR_BOOKE_EPR, "EPR",
4729 SPR_NOACCESS, SPR_NOACCESS,
4730 &spr_read_generic, SPR_NOACCESS,
4731 0x00000000);
4732 /* XXX better abstract into Emb.xxx features */
4733 if (version == fsl_e5500) {
4734 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4735 SPR_NOACCESS, SPR_NOACCESS,
4736 &spr_read_generic, &spr_write_generic,
4737 0x00000000);
4738 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4739 SPR_NOACCESS, SPR_NOACCESS,
4740 &spr_read_mas73, &spr_write_mas73,
4741 0x00000000);
4742 ivpr_mask = (target_ulong)~0xFFFFULL;
4743 }
4744
4745 #if !defined(CONFIG_USER_ONLY)
4746 env->nb_tlb = 0;
4747 env->tlb_type = TLB_MAS;
4748 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4749 env->nb_tlb += booke206_tlb_size(env, i);
4750 }
4751 #endif
4752
4753 init_excp_e200(env, ivpr_mask);
4754 /* Allocate hardware IRQ controller */
4755 ppce500_irq_init(env);
4756 }
4757
4758 static void init_proc_e500v1(CPUPPCState *env)
4759 {
4760 init_proc_e500(env, fsl_e500v1);
4761 }
4762
4763 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4764 {
4765 DeviceClass *dc = DEVICE_CLASS(oc);
4766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4767
4768 dc->desc = "e500v1 core";
4769 pcc->init_proc = init_proc_e500v1;
4770 pcc->check_pow = check_pow_hid0;
4771 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4772 PPC_SPE | PPC_SPE_SINGLE |
4773 PPC_WRTEE | PPC_RFDI |
4774 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4775 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4776 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4777 pcc->insns_flags2 = PPC2_BOOKE206;
4778 pcc->msr_mask = 0x000000000606FF30ULL;
4779 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4780 pcc->excp_model = POWERPC_EXCP_BOOKE;
4781 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4782 pcc->bfd_mach = bfd_mach_ppc_860;
4783 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4784 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4785 POWERPC_FLAG_BUS_CLK;
4786 }
4787
4788 static void init_proc_e500v2(CPUPPCState *env)
4789 {
4790 init_proc_e500(env, fsl_e500v2);
4791 }
4792
4793 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4794 {
4795 DeviceClass *dc = DEVICE_CLASS(oc);
4796 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4797
4798 dc->desc = "e500v2 core";
4799 pcc->init_proc = init_proc_e500v2;
4800 pcc->check_pow = check_pow_hid0;
4801 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4802 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4803 PPC_WRTEE | PPC_RFDI |
4804 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4805 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4806 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4807 pcc->insns_flags2 = PPC2_BOOKE206;
4808 pcc->msr_mask = 0x000000000606FF30ULL;
4809 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4810 pcc->excp_model = POWERPC_EXCP_BOOKE;
4811 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4812 pcc->bfd_mach = bfd_mach_ppc_860;
4813 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4814 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4815 POWERPC_FLAG_BUS_CLK;
4816 }
4817
4818 static void init_proc_e500mc(CPUPPCState *env)
4819 {
4820 init_proc_e500(env, fsl_e500mc);
4821 }
4822
4823 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4824 {
4825 DeviceClass *dc = DEVICE_CLASS(oc);
4826 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4827
4828 dc->desc = "e500mc core";
4829 pcc->init_proc = init_proc_e500mc;
4830 pcc->check_pow = check_pow_none;
4831 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4832 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4833 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4834 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4835 PPC_FLOAT | PPC_FLOAT_FRES |
4836 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4837 PPC_FLOAT_STFIWX | PPC_WAIT |
4838 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4839 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4840 pcc->msr_mask = 0x000000001402FB36ULL;
4841 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4842 pcc->excp_model = POWERPC_EXCP_BOOKE;
4843 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4844 /* FIXME: figure out the correct flag for e500mc */
4845 pcc->bfd_mach = bfd_mach_ppc_e500;
4846 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4847 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4848 }
4849
4850 #ifdef TARGET_PPC64
4851 static void init_proc_e5500(CPUPPCState *env)
4852 {
4853 init_proc_e500(env, fsl_e5500);
4854 }
4855
4856 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4857 {
4858 DeviceClass *dc = DEVICE_CLASS(oc);
4859 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4860
4861 dc->desc = "e5500 core";
4862 pcc->init_proc = init_proc_e5500;
4863 pcc->check_pow = check_pow_none;
4864 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4865 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4866 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4867 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4868 PPC_FLOAT | PPC_FLOAT_FRES |
4869 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4870 PPC_FLOAT_STFIWX | PPC_WAIT |
4871 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4872 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4873 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4874 pcc->msr_mask = 0x000000009402FB36ULL;
4875 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4876 pcc->excp_model = POWERPC_EXCP_BOOKE;
4877 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4878 /* FIXME: figure out the correct flag for e5500 */
4879 pcc->bfd_mach = bfd_mach_ppc_e500;
4880 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4881 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4882 }
4883 #endif
4884
4885 /* Non-embedded PowerPC */
4886
4887 /* POWER : same as 601, without mfmsr, mfsr */
4888 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4889 {
4890 DeviceClass *dc = DEVICE_CLASS(oc);
4891 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4892
4893 dc->desc = "POWER";
4894 /* pcc->insns_flags = XXX_TODO; */
4895 /* POWER RSC (from RAD6000) */
4896 pcc->msr_mask = 0x00000000FEF0ULL;
4897 }
4898
4899 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4900
4901 static void init_proc_601 (CPUPPCState *env)
4902 {
4903 gen_spr_ne_601(env);
4904 gen_spr_601(env);
4905 /* Hardware implementation registers */
4906 /* XXX : not implemented */
4907 spr_register(env, SPR_HID0, "HID0",
4908 SPR_NOACCESS, SPR_NOACCESS,
4909 &spr_read_generic, &spr_write_hid0_601,
4910 0x80010080);
4911 /* XXX : not implemented */
4912 spr_register(env, SPR_HID1, "HID1",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* XXX : not implemented */
4917 spr_register(env, SPR_601_HID2, "HID2",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921 /* XXX : not implemented */
4922 spr_register(env, SPR_601_HID5, "HID5",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926 /* Memory management */
4927 init_excp_601(env);
4928 /* XXX: beware that dcache line size is 64
4929 * but dcbz uses 32 bytes "sectors"
4930 * XXX: this breaks clcs instruction !
4931 */
4932 env->dcache_line_size = 32;
4933 env->icache_line_size = 64;
4934 /* Allocate hardware IRQ controller */
4935 ppc6xx_irq_init(env);
4936 }
4937
4938 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4939 {
4940 DeviceClass *dc = DEVICE_CLASS(oc);
4941 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4942
4943 dc->desc = "PowerPC 601";
4944 pcc->init_proc = init_proc_601;
4945 pcc->check_pow = check_pow_none;
4946 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4947 PPC_FLOAT |
4948 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4949 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4950 PPC_SEGMENT | PPC_EXTERN;
4951 pcc->insns_flags2 = PPC_NONE;
4952 pcc->msr_mask = 0x000000000000FD70ULL;
4953 pcc->mmu_model = POWERPC_MMU_601;
4954 pcc->excp_model = POWERPC_EXCP_601;
4955 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4956 pcc->bfd_mach = bfd_mach_ppc_601;
4957 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4958 }
4959
4960 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4961
4962 static void init_proc_601v (CPUPPCState *env)
4963 {
4964 init_proc_601(env);
4965 /* XXX : not implemented */
4966 spr_register(env, SPR_601_HID15, "HID15",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970 }
4971
4972 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4973 {
4974 DeviceClass *dc = DEVICE_CLASS(oc);
4975 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4976
4977 dc->desc = "PowerPC 601v";
4978 pcc->init_proc = init_proc_601v;
4979 pcc->check_pow = check_pow_none;
4980 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4981 PPC_FLOAT |
4982 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4983 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4984 PPC_SEGMENT | PPC_EXTERN;
4985 pcc->insns_flags2 = PPC_NONE;
4986 pcc->msr_mask = 0x000000000000FD70ULL;
4987 pcc->mmu_model = POWERPC_MMU_601;
4988 pcc->excp_model = POWERPC_EXCP_601;
4989 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4990 pcc->bfd_mach = bfd_mach_ppc_601;
4991 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4992 }
4993
4994 static void init_proc_602 (CPUPPCState *env)
4995 {
4996 gen_spr_ne_601(env);
4997 gen_spr_602(env);
4998 /* Time base */
4999 gen_tbl(env);
5000 /* hardware implementation registers */
5001 /* XXX : not implemented */
5002 spr_register(env, SPR_HID0, "HID0",
5003 SPR_NOACCESS, SPR_NOACCESS,
5004 &spr_read_generic, &spr_write_generic,
5005 0x00000000);
5006 /* XXX : not implemented */
5007 spr_register(env, SPR_HID1, "HID1",
5008 SPR_NOACCESS, SPR_NOACCESS,
5009 &spr_read_generic, &spr_write_generic,
5010 0x00000000);
5011 /* Memory management */
5012 gen_low_BATs(env);
5013 gen_6xx_7xx_soft_tlb(env, 64, 2);
5014 init_excp_602(env);
5015 env->dcache_line_size = 32;
5016 env->icache_line_size = 32;
5017 /* Allocate hardware IRQ controller */
5018 ppc6xx_irq_init(env);
5019 }
5020
5021 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5022 {
5023 DeviceClass *dc = DEVICE_CLASS(oc);
5024 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5025
5026 dc->desc = "PowerPC 602";
5027 pcc->init_proc = init_proc_602;
5028 pcc->check_pow = check_pow_hid0;
5029 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5030 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5031 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5032 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5033 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5034 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5035 PPC_SEGMENT | PPC_602_SPEC;
5036 pcc->insns_flags2 = PPC_NONE;
5037 pcc->msr_mask = 0x0000000000C7FF73ULL;
5038 /* XXX: 602 MMU is quite specific. Should add a special case */
5039 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5040 pcc->excp_model = POWERPC_EXCP_602;
5041 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5042 pcc->bfd_mach = bfd_mach_ppc_602;
5043 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5044 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5045 }
5046
5047 static void init_proc_603 (CPUPPCState *env)
5048 {
5049 gen_spr_ne_601(env);
5050 gen_spr_603(env);
5051 /* Time base */
5052 gen_tbl(env);
5053 /* hardware implementation registers */
5054 /* XXX : not implemented */
5055 spr_register(env, SPR_HID0, "HID0",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 0x00000000);
5059 /* XXX : not implemented */
5060 spr_register(env, SPR_HID1, "HID1",
5061 SPR_NOACCESS, SPR_NOACCESS,
5062 &spr_read_generic, &spr_write_generic,
5063 0x00000000);
5064 /* Memory management */
5065 gen_low_BATs(env);
5066 gen_6xx_7xx_soft_tlb(env, 64, 2);
5067 init_excp_603(env);
5068 env->dcache_line_size = 32;
5069 env->icache_line_size = 32;
5070 /* Allocate hardware IRQ controller */
5071 ppc6xx_irq_init(env);
5072 }
5073
5074 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5075 {
5076 DeviceClass *dc = DEVICE_CLASS(oc);
5077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5078
5079 dc->desc = "PowerPC 603";
5080 pcc->init_proc = init_proc_603;
5081 pcc->check_pow = check_pow_hid0;
5082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5084 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5085 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5086 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5087 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5088 PPC_SEGMENT | PPC_EXTERN;
5089 pcc->insns_flags2 = PPC_NONE;
5090 pcc->msr_mask = 0x000000000007FF73ULL;
5091 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5092 pcc->excp_model = POWERPC_EXCP_603;
5093 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5094 pcc->bfd_mach = bfd_mach_ppc_603;
5095 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5096 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5097 }
5098
5099 static void init_proc_603E (CPUPPCState *env)
5100 {
5101 gen_spr_ne_601(env);
5102 gen_spr_603(env);
5103 /* Time base */
5104 gen_tbl(env);
5105 /* hardware implementation registers */
5106 /* XXX : not implemented */
5107 spr_register(env, SPR_HID0, "HID0",
5108 SPR_NOACCESS, SPR_NOACCESS,
5109 &spr_read_generic, &spr_write_generic,
5110 0x00000000);
5111 /* XXX : not implemented */
5112 spr_register(env, SPR_HID1, "HID1",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, &spr_write_generic,
5115 0x00000000);
5116 /* XXX : not implemented */
5117 spr_register(env, SPR_IABR, "IABR",
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 0x00000000);
5121 /* Memory management */
5122 gen_low_BATs(env);
5123 gen_6xx_7xx_soft_tlb(env, 64, 2);
5124 init_excp_603(env);
5125 env->dcache_line_size = 32;
5126 env->icache_line_size = 32;
5127 /* Allocate hardware IRQ controller */
5128 ppc6xx_irq_init(env);
5129 }
5130
5131 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5132 {
5133 DeviceClass *dc = DEVICE_CLASS(oc);
5134 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5135
5136 dc->desc = "PowerPC 603e";
5137 pcc->init_proc = init_proc_603E;
5138 pcc->check_pow = check_pow_hid0;
5139 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5140 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5141 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5142 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5143 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5144 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5145 PPC_SEGMENT | PPC_EXTERN;
5146 pcc->insns_flags2 = PPC_NONE;
5147 pcc->msr_mask = 0x000000000007FF73ULL;
5148 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5149 pcc->excp_model = POWERPC_EXCP_603E;
5150 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5151 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5152 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5153 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5154 }
5155
5156 static void init_proc_604 (CPUPPCState *env)
5157 {
5158 gen_spr_ne_601(env);
5159 gen_spr_604(env);
5160 /* Time base */
5161 gen_tbl(env);
5162 /* Hardware implementation registers */
5163 /* XXX : not implemented */
5164 spr_register(env, SPR_HID0, "HID0",
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_generic, &spr_write_generic,
5167 0x00000000);
5168 /* Memory management */
5169 gen_low_BATs(env);
5170 init_excp_604(env);
5171 env->dcache_line_size = 32;
5172 env->icache_line_size = 32;
5173 /* Allocate hardware IRQ controller */
5174 ppc6xx_irq_init(env);
5175 }
5176
5177 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5178 {
5179 DeviceClass *dc = DEVICE_CLASS(oc);
5180 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5181
5182 dc->desc = "PowerPC 604";
5183 pcc->init_proc = init_proc_604;
5184 pcc->check_pow = check_pow_nocheck;
5185 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5186 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5187 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5188 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5189 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5190 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5191 PPC_SEGMENT | PPC_EXTERN;
5192 pcc->insns_flags2 = PPC_NONE;
5193 pcc->msr_mask = 0x000000000005FF77ULL;
5194 pcc->mmu_model = POWERPC_MMU_32B;
5195 pcc->excp_model = POWERPC_EXCP_604;
5196 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5197 pcc->bfd_mach = bfd_mach_ppc_604;
5198 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5199 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5200 }
5201
5202 static void init_proc_604E (CPUPPCState *env)
5203 {
5204 gen_spr_ne_601(env);
5205 gen_spr_604(env);
5206 /* XXX : not implemented */
5207 spr_register(env, SPR_MMCR1, "MMCR1",
5208 SPR_NOACCESS, SPR_NOACCESS,
5209 &spr_read_generic, &spr_write_generic,
5210 0x00000000);
5211 /* XXX : not implemented */
5212 spr_register(env, SPR_PMC3, "PMC3",
5213 SPR_NOACCESS, SPR_NOACCESS,
5214 &spr_read_generic, &spr_write_generic,
5215 0x00000000);
5216 /* XXX : not implemented */
5217 spr_register(env, SPR_PMC4, "PMC4",
5218 SPR_NOACCESS, SPR_NOACCESS,
5219 &spr_read_generic, &spr_write_generic,
5220 0x00000000);
5221 /* Time base */
5222 gen_tbl(env);
5223 /* Hardware implementation registers */
5224 /* XXX : not implemented */
5225 spr_register(env, SPR_HID0, "HID0",
5226 SPR_NOACCESS, SPR_NOACCESS,
5227 &spr_read_generic, &spr_write_generic,
5228 0x00000000);
5229 /* XXX : not implemented */
5230 spr_register(env, SPR_HID1, "HID1",
5231 SPR_NOACCESS, SPR_NOACCESS,
5232 &spr_read_generic, &spr_write_generic,
5233 0x00000000);
5234 /* Memory management */
5235 gen_low_BATs(env);
5236 init_excp_604(env);
5237 env->dcache_line_size = 32;
5238 env->icache_line_size = 32;
5239 /* Allocate hardware IRQ controller */
5240 ppc6xx_irq_init(env);
5241 }
5242
5243 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5244 {
5245 DeviceClass *dc = DEVICE_CLASS(oc);
5246 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5247
5248 dc->desc = "PowerPC 604E";
5249 pcc->init_proc = init_proc_604E;
5250 pcc->check_pow = check_pow_nocheck;
5251 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5252 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5253 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5254 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5255 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5256 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5257 PPC_SEGMENT | PPC_EXTERN;
5258 pcc->insns_flags2 = PPC_NONE;
5259 pcc->msr_mask = 0x000000000005FF77ULL;
5260 pcc->mmu_model = POWERPC_MMU_32B;
5261 pcc->excp_model = POWERPC_EXCP_604;
5262 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5263 pcc->bfd_mach = bfd_mach_ppc_604;
5264 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5265 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5266 }
5267
5268 static void init_proc_740 (CPUPPCState *env)
5269 {
5270 gen_spr_ne_601(env);
5271 gen_spr_7xx(env);
5272 /* Time base */
5273 gen_tbl(env);
5274 /* Thermal management */
5275 gen_spr_thrm(env);
5276 /* Hardware implementation registers */
5277 /* XXX : not implemented */
5278 spr_register(env, SPR_HID0, "HID0",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 /* XXX : not implemented */
5283 spr_register(env, SPR_HID1, "HID1",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287 /* Memory management */
5288 gen_low_BATs(env);
5289 init_excp_7x0(env);
5290 env->dcache_line_size = 32;
5291 env->icache_line_size = 32;
5292 /* Allocate hardware IRQ controller */
5293 ppc6xx_irq_init(env);
5294 }
5295
5296 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5297 {
5298 DeviceClass *dc = DEVICE_CLASS(oc);
5299 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5300
5301 dc->desc = "PowerPC 740";
5302 pcc->init_proc = init_proc_740;
5303 pcc->check_pow = check_pow_hid0;
5304 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5305 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5306 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5307 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5308 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5309 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5310 PPC_SEGMENT | PPC_EXTERN;
5311 pcc->insns_flags2 = PPC_NONE;
5312 pcc->msr_mask = 0x000000000005FF77ULL;
5313 pcc->mmu_model = POWERPC_MMU_32B;
5314 pcc->excp_model = POWERPC_EXCP_7x0;
5315 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5316 pcc->bfd_mach = bfd_mach_ppc_750;
5317 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5318 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5319 }
5320
5321 static void init_proc_750 (CPUPPCState *env)
5322 {
5323 gen_spr_ne_601(env);
5324 gen_spr_7xx(env);
5325 /* XXX : not implemented */
5326 spr_register(env, SPR_L2CR, "L2CR",
5327 SPR_NOACCESS, SPR_NOACCESS,
5328 &spr_read_generic, &spr_write_generic,
5329 0x00000000);
5330 /* Time base */
5331 gen_tbl(env);
5332 /* Thermal management */
5333 gen_spr_thrm(env);
5334 /* Hardware implementation registers */
5335 /* XXX : not implemented */
5336 spr_register(env, SPR_HID0, "HID0",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 0x00000000);
5340 /* XXX : not implemented */
5341 spr_register(env, SPR_HID1, "HID1",
5342 SPR_NOACCESS, SPR_NOACCESS,
5343 &spr_read_generic, &spr_write_generic,
5344 0x00000000);
5345 /* Memory management */
5346 gen_low_BATs(env);
5347 /* XXX: high BATs are also present but are known to be bugged on
5348 * die version 1.x
5349 */
5350 init_excp_7x0(env);
5351 env->dcache_line_size = 32;
5352 env->icache_line_size = 32;
5353 /* Allocate hardware IRQ controller */
5354 ppc6xx_irq_init(env);
5355 }
5356
5357 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5358 {
5359 DeviceClass *dc = DEVICE_CLASS(oc);
5360 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5361
5362 dc->desc = "PowerPC 750";
5363 pcc->init_proc = init_proc_750;
5364 pcc->check_pow = check_pow_hid0;
5365 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5366 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5367 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5368 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5369 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5370 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5371 PPC_SEGMENT | PPC_EXTERN;
5372 pcc->insns_flags2 = PPC_NONE;
5373 pcc->msr_mask = 0x000000000005FF77ULL;
5374 pcc->mmu_model = POWERPC_MMU_32B;
5375 pcc->excp_model = POWERPC_EXCP_7x0;
5376 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5377 pcc->bfd_mach = bfd_mach_ppc_750;
5378 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5379 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5380 }
5381
5382 static void init_proc_750cl (CPUPPCState *env)
5383 {
5384 gen_spr_ne_601(env);
5385 gen_spr_7xx(env);
5386 /* XXX : not implemented */
5387 spr_register(env, SPR_L2CR, "L2CR",
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 &spr_read_generic, &spr_write_generic,
5390 0x00000000);
5391 /* Time base */
5392 gen_tbl(env);
5393 /* Thermal management */
5394 /* Those registers are fake on 750CL */
5395 spr_register(env, SPR_THRM1, "THRM1",
5396 SPR_NOACCESS, SPR_NOACCESS,
5397 &spr_read_generic, &spr_write_generic,
5398 0x00000000);
5399 spr_register(env, SPR_THRM2, "THRM2",
5400 SPR_NOACCESS, SPR_NOACCESS,
5401 &spr_read_generic, &spr_write_generic,
5402 0x00000000);
5403 spr_register(env, SPR_THRM3, "THRM3",
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 /* XXX: not implemented */
5408 spr_register(env, SPR_750_TDCL, "TDCL",
5409 SPR_NOACCESS, SPR_NOACCESS,
5410 &spr_read_generic, &spr_write_generic,
5411 0x00000000);
5412 spr_register(env, SPR_750_TDCH, "TDCH",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 &spr_read_generic, &spr_write_generic,
5415 0x00000000);
5416 /* DMA */
5417 /* XXX : not implemented */
5418 spr_register(env, SPR_750_WPAR, "WPAR",
5419 SPR_NOACCESS, SPR_NOACCESS,
5420 &spr_read_generic, &spr_write_generic,
5421 0x00000000);
5422 spr_register(env, SPR_750_DMAL, "DMAL",
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 &spr_read_generic, &spr_write_generic,
5425 0x00000000);
5426 spr_register(env, SPR_750_DMAU, "DMAU",
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 &spr_read_generic, &spr_write_generic,
5429 0x00000000);
5430 /* Hardware implementation registers */
5431 /* XXX : not implemented */
5432 spr_register(env, SPR_HID0, "HID0",
5433 SPR_NOACCESS, SPR_NOACCESS,
5434 &spr_read_generic, &spr_write_generic,
5435 0x00000000);
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_HID1, "HID1",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* XXX : not implemented */
5442 spr_register(env, SPR_750CL_HID2, "HID2",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 &spr_read_generic, &spr_write_generic,
5445 0x00000000);
5446 /* XXX : not implemented */
5447 spr_register(env, SPR_750CL_HID4, "HID4",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* Quantization registers */
5452 /* XXX : not implemented */
5453 spr_register(env, SPR_750_GQR0, "GQR0",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 &spr_read_generic, &spr_write_generic,
5456 0x00000000);
5457 /* XXX : not implemented */
5458 spr_register(env, SPR_750_GQR1, "GQR1",
5459 SPR_NOACCESS, SPR_NOACCESS,
5460 &spr_read_generic, &spr_write_generic,
5461 0x00000000);
5462 /* XXX : not implemented */
5463 spr_register(env, SPR_750_GQR2, "GQR2",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 &spr_read_generic, &spr_write_generic,
5466 0x00000000);
5467 /* XXX : not implemented */
5468 spr_register(env, SPR_750_GQR3, "GQR3",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_generic,
5471 0x00000000);
5472 /* XXX : not implemented */
5473 spr_register(env, SPR_750_GQR4, "GQR4",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 /* XXX : not implemented */
5478 spr_register(env, SPR_750_GQR5, "GQR5",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 /* XXX : not implemented */
5483 spr_register(env, SPR_750_GQR6, "GQR6",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 &spr_read_generic, &spr_write_generic,
5486 0x00000000);
5487 /* XXX : not implemented */
5488 spr_register(env, SPR_750_GQR7, "GQR7",
5489 SPR_NOACCESS, SPR_NOACCESS,
5490 &spr_read_generic, &spr_write_generic,
5491 0x00000000);
5492 /* Memory management */
5493 gen_low_BATs(env);
5494 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5495 gen_high_BATs(env);
5496 init_excp_750cl(env);
5497 env->dcache_line_size = 32;
5498 env->icache_line_size = 32;
5499 /* Allocate hardware IRQ controller */
5500 ppc6xx_irq_init(env);
5501 }
5502
5503 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5504 {
5505 DeviceClass *dc = DEVICE_CLASS(oc);
5506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5507
5508 dc->desc = "PowerPC 750 CL";
5509 pcc->init_proc = init_proc_750cl;
5510 pcc->check_pow = check_pow_hid0;
5511 /* XXX: not implemented:
5512 * cache lock instructions:
5513 * dcbz_l
5514 * floating point paired instructions
5515 * psq_lux
5516 * psq_lx
5517 * psq_stux
5518 * psq_stx
5519 * ps_abs
5520 * ps_add
5521 * ps_cmpo0
5522 * ps_cmpo1
5523 * ps_cmpu0
5524 * ps_cmpu1
5525 * ps_div
5526 * ps_madd
5527 * ps_madds0
5528 * ps_madds1
5529 * ps_merge00
5530 * ps_merge01
5531 * ps_merge10
5532 * ps_merge11
5533 * ps_mr
5534 * ps_msub
5535 * ps_mul
5536 * ps_muls0
5537 * ps_muls1
5538 * ps_nabs
5539 * ps_neg
5540 * ps_nmadd
5541 * ps_nmsub
5542 * ps_res
5543 * ps_rsqrte
5544 * ps_sel
5545 * ps_sub
5546 * ps_sum0
5547 * ps_sum1
5548 */
5549 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5550 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5551 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5552 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5553 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5554 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5555 PPC_SEGMENT | PPC_EXTERN;
5556 pcc->insns_flags2 = PPC_NONE;
5557 pcc->msr_mask = 0x000000000005FF77ULL;
5558 pcc->mmu_model = POWERPC_MMU_32B;
5559 pcc->excp_model = POWERPC_EXCP_7x0;
5560 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5561 pcc->bfd_mach = bfd_mach_ppc_750;
5562 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5563 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5564 }
5565
5566 static void init_proc_750cx (CPUPPCState *env)
5567 {
5568 gen_spr_ne_601(env);
5569 gen_spr_7xx(env);
5570 /* XXX : not implemented */
5571 spr_register(env, SPR_L2CR, "L2CR",
5572 SPR_NOACCESS, SPR_NOACCESS,
5573 &spr_read_generic, &spr_write_generic,
5574 0x00000000);
5575 /* Time base */
5576 gen_tbl(env);
5577 /* Thermal management */
5578 gen_spr_thrm(env);
5579 /* This register is not implemented but is present for compatibility */
5580 spr_register(env, SPR_SDA, "SDA",
5581 SPR_NOACCESS, SPR_NOACCESS,
5582 &spr_read_generic, &spr_write_generic,
5583 0x00000000);
5584 /* Hardware implementation registers */
5585 /* XXX : not implemented */
5586 spr_register(env, SPR_HID0, "HID0",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 &spr_read_generic, &spr_write_generic,
5589 0x00000000);
5590 /* XXX : not implemented */
5591 spr_register(env, SPR_HID1, "HID1",
5592 SPR_NOACCESS, SPR_NOACCESS,
5593 &spr_read_generic, &spr_write_generic,
5594 0x00000000);
5595 /* Memory management */
5596 gen_low_BATs(env);
5597 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5598 gen_high_BATs(env);
5599 init_excp_750cx(env);
5600 env->dcache_line_size = 32;
5601 env->icache_line_size = 32;
5602 /* Allocate hardware IRQ controller */
5603 ppc6xx_irq_init(env);
5604 }
5605
5606 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5607 {
5608 DeviceClass *dc = DEVICE_CLASS(oc);
5609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5610
5611 dc->desc = "PowerPC 750CX";
5612 pcc->init_proc = init_proc_750cx;
5613 pcc->check_pow = check_pow_hid0;
5614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5616 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5617 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5618 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5620 PPC_SEGMENT | PPC_EXTERN;
5621 pcc->insns_flags2 = PPC_NONE;
5622 pcc->msr_mask = 0x000000000005FF77ULL;
5623 pcc->mmu_model = POWERPC_MMU_32B;
5624 pcc->excp_model = POWERPC_EXCP_7x0;
5625 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5626 pcc->bfd_mach = bfd_mach_ppc_750;
5627 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5628 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5629 }
5630
5631 static void init_proc_750fx (CPUPPCState *env)
5632 {
5633 gen_spr_ne_601(env);
5634 gen_spr_7xx(env);
5635 /* XXX : not implemented */
5636 spr_register(env, SPR_L2CR, "L2CR",
5637 SPR_NOACCESS, SPR_NOACCESS,
5638 &spr_read_generic, &spr_write_generic,
5639 0x00000000);
5640 /* Time base */
5641 gen_tbl(env);
5642 /* Thermal management */
5643 gen_spr_thrm(env);
5644 /* XXX : not implemented */
5645 spr_register(env, SPR_750_THRM4, "THRM4",
5646 SPR_NOACCESS, SPR_NOACCESS,
5647 &spr_read_generic, &spr_write_generic,
5648 0x00000000);
5649 /* Hardware implementation registers */
5650 /* XXX : not implemented */
5651 spr_register(env, SPR_HID0, "HID0",
5652 SPR_NOACCESS, SPR_NOACCESS,
5653 &spr_read_generic, &spr_write_generic,
5654 0x00000000);
5655 /* XXX : not implemented */
5656 spr_register(env, SPR_HID1, "HID1",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_generic, &spr_write_generic,
5659 0x00000000);
5660 /* XXX : not implemented */
5661 spr_register(env, SPR_750FX_HID2, "HID2",
5662 SPR_NOACCESS, SPR_NOACCESS,
5663 &spr_read_generic, &spr_write_generic,
5664 0x00000000);
5665 /* Memory management */
5666 gen_low_BATs(env);
5667 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5668 gen_high_BATs(env);
5669 init_excp_7x0(env);
5670 env->dcache_line_size = 32;
5671 env->icache_line_size = 32;
5672 /* Allocate hardware IRQ controller */
5673 ppc6xx_irq_init(env);
5674 }
5675
5676 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5677 {
5678 DeviceClass *dc = DEVICE_CLASS(oc);
5679 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5680
5681 dc->desc = "PowerPC 750FX";
5682 pcc->init_proc = init_proc_750fx;
5683 pcc->check_pow = check_pow_hid0;
5684 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5685 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5686 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5687 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5688 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5689 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5690 PPC_SEGMENT | PPC_EXTERN;
5691 pcc->insns_flags2 = PPC_NONE;
5692 pcc->msr_mask = 0x000000000005FF77ULL;
5693 pcc->mmu_model = POWERPC_MMU_32B;
5694 pcc->excp_model = POWERPC_EXCP_7x0;
5695 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5696 pcc->bfd_mach = bfd_mach_ppc_750;
5697 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5698 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5699 }
5700
5701 static void init_proc_750gx (CPUPPCState *env)
5702 {
5703 gen_spr_ne_601(env);
5704 gen_spr_7xx(env);
5705 /* XXX : not implemented (XXX: different from 750fx) */
5706 spr_register(env, SPR_L2CR, "L2CR",
5707 SPR_NOACCESS, SPR_NOACCESS,
5708 &spr_read_generic, &spr_write_generic,
5709 0x00000000);
5710 /* Time base */
5711 gen_tbl(env);
5712 /* Thermal management */
5713 gen_spr_thrm(env);
5714 /* XXX : not implemented */
5715 spr_register(env, SPR_750_THRM4, "THRM4",
5716 SPR_NOACCESS, SPR_NOACCESS,
5717 &spr_read_generic, &spr_write_generic,
5718 0x00000000);
5719 /* Hardware implementation registers */
5720 /* XXX : not implemented (XXX: different from 750fx) */
5721 spr_register(env, SPR_HID0, "HID0",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 &spr_read_generic, &spr_write_generic,
5724 0x00000000);
5725 /* XXX : not implemented */
5726 spr_register(env, SPR_HID1, "HID1",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 &spr_read_generic, &spr_write_generic,
5729 0x00000000);
5730 /* XXX : not implemented (XXX: different from 750fx) */
5731 spr_register(env, SPR_750FX_HID2, "HID2",
5732 SPR_NOACCESS, SPR_NOACCESS,
5733 &spr_read_generic, &spr_write_generic,
5734 0x00000000);
5735 /* Memory management */
5736 gen_low_BATs(env);
5737 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5738 gen_high_BATs(env);
5739 init_excp_7x0(env);
5740 env->dcache_line_size = 32;
5741 env->icache_line_size = 32;
5742 /* Allocate hardware IRQ controller */
5743 ppc6xx_irq_init(env);
5744 }
5745
5746 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5747 {
5748 DeviceClass *dc = DEVICE_CLASS(oc);
5749 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5750
5751 dc->desc = "PowerPC 750GX";
5752 pcc->init_proc = init_proc_750gx;
5753 pcc->check_pow = check_pow_hid0;
5754 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5755 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5756 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5757 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5758 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5759 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5760 PPC_SEGMENT | PPC_EXTERN;
5761 pcc->insns_flags2 = PPC_NONE;
5762 pcc->msr_mask = 0x000000000005FF77ULL;
5763 pcc->mmu_model = POWERPC_MMU_32B;
5764 pcc->excp_model = POWERPC_EXCP_7x0;
5765 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5766 pcc->bfd_mach = bfd_mach_ppc_750;
5767 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5768 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5769 }
5770
5771 static void init_proc_745 (CPUPPCState *env)
5772 {
5773 gen_spr_ne_601(env);
5774 gen_spr_7xx(env);
5775 gen_spr_G2_755(env);
5776 /* Time base */
5777 gen_tbl(env);
5778 /* Thermal management */
5779 gen_spr_thrm(env);
5780 /* Hardware implementation registers */
5781 /* XXX : not implemented */
5782 spr_register(env, SPR_HID0, "HID0",
5783 SPR_NOACCESS, SPR_NOACCESS,
5784 &spr_read_generic, &spr_write_generic,
5785 0x00000000);
5786 /* XXX : not implemented */
5787 spr_register(env, SPR_HID1, "HID1",
5788 SPR_NOACCESS, SPR_NOACCESS,
5789 &spr_read_generic, &spr_write_generic,
5790 0x00000000);
5791 /* XXX : not implemented */
5792 spr_register(env, SPR_HID2, "HID2",
5793 SPR_NOACCESS, SPR_NOACCESS,
5794 &spr_read_generic, &spr_write_generic,
5795 0x00000000);
5796 /* Memory management */
5797 gen_low_BATs(env);
5798 gen_high_BATs(env);
5799 gen_6xx_7xx_soft_tlb(env, 64, 2);
5800 init_excp_7x5(env);
5801 env->dcache_line_size = 32;
5802 env->icache_line_size = 32;
5803 /* Allocate hardware IRQ controller */
5804 ppc6xx_irq_init(env);
5805 }
5806
5807 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5808 {
5809 DeviceClass *dc = DEVICE_CLASS(oc);
5810 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5811
5812 dc->desc = "PowerPC 745";
5813 pcc->init_proc = init_proc_745;
5814 pcc->check_pow = check_pow_hid0;
5815 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5816 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5817 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5818 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5819 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5820 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5821 PPC_SEGMENT | PPC_EXTERN;
5822 pcc->insns_flags2 = PPC_NONE;
5823 pcc->msr_mask = 0x000000000005FF77ULL;
5824 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5825 pcc->excp_model = POWERPC_EXCP_7x5;
5826 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5827 pcc->bfd_mach = bfd_mach_ppc_750;
5828 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5829 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5830 }
5831
5832 static void init_proc_755 (CPUPPCState *env)
5833 {
5834 gen_spr_ne_601(env);
5835 gen_spr_7xx(env);
5836 gen_spr_G2_755(env);
5837 /* Time base */
5838 gen_tbl(env);
5839 /* L2 cache control */
5840 /* XXX : not implemented */
5841 spr_register(env, SPR_L2CR, "L2CR",
5842 SPR_NOACCESS, SPR_NOACCESS,
5843 &spr_read_generic, &spr_write_generic,
5844 0x00000000);
5845 /* XXX : not implemented */
5846 spr_register(env, SPR_L2PMCR, "L2PMCR",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 &spr_read_generic, &spr_write_generic,
5849 0x00000000);
5850 /* Thermal management */
5851 gen_spr_thrm(env);
5852 /* Hardware implementation registers */
5853 /* XXX : not implemented */
5854 spr_register(env, SPR_HID0, "HID0",
5855 SPR_NOACCESS, SPR_NOACCESS,
5856 &spr_read_generic, &spr_write_generic,
5857 0x00000000);
5858 /* XXX : not implemented */
5859 spr_register(env, SPR_HID1, "HID1",
5860 SPR_NOACCESS, SPR_NOACCESS,
5861 &spr_read_generic, &spr_write_generic,
5862 0x00000000);
5863 /* XXX : not implemented */
5864 spr_register(env, SPR_HID2, "HID2",
5865 SPR_NOACCESS, SPR_NOACCESS,
5866 &spr_read_generic, &spr_write_generic,
5867 0x00000000);
5868 /* Memory management */
5869 gen_low_BATs(env);
5870 gen_high_BATs(env);
5871 gen_6xx_7xx_soft_tlb(env, 64, 2);
5872 init_excp_7x5(env);
5873 env->dcache_line_size = 32;
5874 env->icache_line_size = 32;
5875 /* Allocate hardware IRQ controller */
5876 ppc6xx_irq_init(env);
5877 }
5878
5879 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5880 {
5881 DeviceClass *dc = DEVICE_CLASS(oc);
5882 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5883
5884 dc->desc = "PowerPC 755";
5885 pcc->init_proc = init_proc_755;
5886 pcc->check_pow = check_pow_hid0;
5887 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5888 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5889 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5890 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5891 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5892 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5893 PPC_SEGMENT | PPC_EXTERN;
5894 pcc->insns_flags2 = PPC_NONE;
5895 pcc->msr_mask = 0x000000000005FF77ULL;
5896 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5897 pcc->excp_model = POWERPC_EXCP_7x5;
5898 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5899 pcc->bfd_mach = bfd_mach_ppc_750;
5900 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5901 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5902 }
5903
5904 static void init_proc_7400 (CPUPPCState *env)
5905 {
5906 gen_spr_ne_601(env);
5907 gen_spr_7xx(env);
5908 /* Time base */
5909 gen_tbl(env);
5910 /* 74xx specific SPR */
5911 gen_spr_74xx(env);
5912 /* XXX : not implemented */
5913 spr_register(env, SPR_UBAMR, "UBAMR",
5914 &spr_read_ureg, SPR_NOACCESS,
5915 &spr_read_ureg, SPR_NOACCESS,
5916 0x00000000);
5917 /* XXX: this seems not implemented on all revisions. */
5918 /* XXX : not implemented */
5919 spr_register(env, SPR_MSSCR1, "MSSCR1",
5920 SPR_NOACCESS, SPR_NOACCESS,
5921 &spr_read_generic, &spr_write_generic,
5922 0x00000000);
5923 /* Thermal management */
5924 gen_spr_thrm(env);
5925 /* Memory management */
5926 gen_low_BATs(env);
5927 init_excp_7400(env);
5928 env->dcache_line_size = 32;
5929 env->icache_line_size = 32;
5930 /* Allocate hardware IRQ controller */
5931 ppc6xx_irq_init(env);
5932 }
5933
5934 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5935 {
5936 DeviceClass *dc = DEVICE_CLASS(oc);
5937 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5938
5939 dc->desc = "PowerPC 7400 (aka G4)";
5940 pcc->init_proc = init_proc_7400;
5941 pcc->check_pow = check_pow_hid0;
5942 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5943 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5944 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5945 PPC_FLOAT_STFIWX |
5946 PPC_CACHE | PPC_CACHE_ICBI |
5947 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5948 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5949 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5950 PPC_MEM_TLBIA |
5951 PPC_SEGMENT | PPC_EXTERN |
5952 PPC_ALTIVEC;
5953 pcc->insns_flags2 = PPC_NONE;
5954 pcc->msr_mask = 0x000000000205FF77ULL;
5955 pcc->mmu_model = POWERPC_MMU_32B;
5956 pcc->excp_model = POWERPC_EXCP_74xx;
5957 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5958 pcc->bfd_mach = bfd_mach_ppc_7400;
5959 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5960 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5961 POWERPC_FLAG_BUS_CLK;
5962 }
5963
5964 static void init_proc_7410 (CPUPPCState *env)
5965 {
5966 gen_spr_ne_601(env);
5967 gen_spr_7xx(env);
5968 /* Time base */
5969 gen_tbl(env);
5970 /* 74xx specific SPR */
5971 gen_spr_74xx(env);
5972 /* XXX : not implemented */
5973 spr_register(env, SPR_UBAMR, "UBAMR",
5974 &spr_read_ureg, SPR_NOACCESS,
5975 &spr_read_ureg, SPR_NOACCESS,
5976 0x00000000);
5977 /* Thermal management */
5978 gen_spr_thrm(env);
5979 /* L2PMCR */
5980 /* XXX : not implemented */
5981 spr_register(env, SPR_L2PMCR, "L2PMCR",
5982 SPR_NOACCESS, SPR_NOACCESS,
5983 &spr_read_generic, &spr_write_generic,
5984 0x00000000);
5985 /* LDSTDB */
5986 /* XXX : not implemented */
5987 spr_register(env, SPR_LDSTDB, "LDSTDB",
5988 SPR_NOACCESS, SPR_NOACCESS,
5989 &spr_read_generic, &spr_write_generic,
5990 0x00000000);
5991 /* Memory management */
5992 gen_low_BATs(env);
5993 init_excp_7400(env);
5994 env->dcache_line_size = 32;
5995 env->icache_line_size = 32;
5996 /* Allocate hardware IRQ controller */
5997 ppc6xx_irq_init(env);
5998 }
5999
6000 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6001 {
6002 DeviceClass *dc = DEVICE_CLASS(oc);
6003 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6004
6005 dc->desc = "PowerPC 7410 (aka G4)";
6006 pcc->init_proc = init_proc_7410;
6007 pcc->check_pow = check_pow_hid0;
6008 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6009 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6010 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6011 PPC_FLOAT_STFIWX |
6012 PPC_CACHE | PPC_CACHE_ICBI |
6013 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6014 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6015 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6016 PPC_MEM_TLBIA |
6017 PPC_SEGMENT | PPC_EXTERN |
6018 PPC_ALTIVEC;
6019 pcc->insns_flags2 = PPC_NONE;
6020 pcc->msr_mask = 0x000000000205FF77ULL;
6021 pcc->mmu_model = POWERPC_MMU_32B;
6022 pcc->excp_model = POWERPC_EXCP_74xx;
6023 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6024 pcc->bfd_mach = bfd_mach_ppc_7400;
6025 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6027 POWERPC_FLAG_BUS_CLK;
6028 }
6029
6030 static void init_proc_7440 (CPUPPCState *env)
6031 {
6032 gen_spr_ne_601(env);
6033 gen_spr_7xx(env);
6034 /* Time base */
6035 gen_tbl(env);
6036 /* 74xx specific SPR */
6037 gen_spr_74xx(env);
6038 /* XXX : not implemented */
6039 spr_register(env, SPR_UBAMR, "UBAMR",
6040 &spr_read_ureg, SPR_NOACCESS,
6041 &spr_read_ureg, SPR_NOACCESS,
6042 0x00000000);
6043 /* LDSTCR */
6044 /* XXX : not implemented */
6045 spr_register(env, SPR_LDSTCR, "LDSTCR",
6046 SPR_NOACCESS, SPR_NOACCESS,
6047 &spr_read_generic, &spr_write_generic,
6048 0x00000000);
6049 /* ICTRL */
6050 /* XXX : not implemented */
6051 spr_register(env, SPR_ICTRL, "ICTRL",
6052 SPR_NOACCESS, SPR_NOACCESS,
6053 &spr_read_generic, &spr_write_generic,
6054 0x00000000);
6055 /* MSSSR0 */
6056 /* XXX : not implemented */
6057 spr_register(env, SPR_MSSSR0, "MSSSR0",
6058 SPR_NOACCESS, SPR_NOACCESS,
6059 &spr_read_generic, &spr_write_generic,
6060 0x00000000);
6061 /* PMC */
6062 /* XXX : not implemented */
6063 spr_register(env, SPR_PMC5, "PMC5",
6064 SPR_NOACCESS, SPR_NOACCESS,
6065 &spr_read_generic, &spr_write_generic,
6066 0x00000000);
6067 /* XXX : not implemented */
6068 spr_register(env, SPR_UPMC5, "UPMC5",
6069 &spr_read_ureg, SPR_NOACCESS,
6070 &spr_read_ureg, SPR_NOACCESS,
6071 0x00000000);
6072 /* XXX : not implemented */
6073 spr_register(env, SPR_PMC6, "PMC6",
6074 SPR_NOACCESS, SPR_NOACCESS,
6075 &spr_read_generic, &spr_write_generic,
6076 0x00000000);
6077 /* XXX : not implemented */
6078 spr_register(env, SPR_UPMC6, "UPMC6",
6079 &spr_read_ureg, SPR_NOACCESS,
6080 &spr_read_ureg, SPR_NOACCESS,
6081 0x00000000);
6082 /* Memory management */
6083 gen_low_BATs(env);
6084 gen_74xx_soft_tlb(env, 128, 2);
6085 init_excp_7450(env);
6086 env->dcache_line_size = 32;
6087 env->icache_line_size = 32;
6088 /* Allocate hardware IRQ controller */
6089 ppc6xx_irq_init(env);
6090 }
6091
6092 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6093 {
6094 DeviceClass *dc = DEVICE_CLASS(oc);
6095 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6096
6097 dc->desc = "PowerPC 7440 (aka G4)";
6098 pcc->init_proc = init_proc_7440;
6099 pcc->check_pow = check_pow_hid0_74xx;
6100 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6101 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6102 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6103 PPC_FLOAT_STFIWX |
6104 PPC_CACHE | PPC_CACHE_ICBI |
6105 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6106 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6107 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6108 PPC_MEM_TLBIA | PPC_74xx_TLB |
6109 PPC_SEGMENT | PPC_EXTERN |
6110 PPC_ALTIVEC;
6111 pcc->insns_flags2 = PPC_NONE;
6112 pcc->msr_mask = 0x000000000205FF77ULL;
6113 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6114 pcc->excp_model = POWERPC_EXCP_74xx;
6115 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6116 pcc->bfd_mach = bfd_mach_ppc_7400;
6117 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6118 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6119 POWERPC_FLAG_BUS_CLK;
6120 }
6121
6122 static void init_proc_7450 (CPUPPCState *env)
6123 {
6124 gen_spr_ne_601(env);
6125 gen_spr_7xx(env);
6126 /* Time base */
6127 gen_tbl(env);
6128 /* 74xx specific SPR */
6129 gen_spr_74xx(env);
6130 /* Level 3 cache control */
6131 gen_l3_ctrl(env);
6132 /* L3ITCR1 */
6133 /* XXX : not implemented */
6134 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6135 SPR_NOACCESS, SPR_NOACCESS,
6136 &spr_read_generic, &spr_write_generic,
6137 0x00000000);
6138 /* L3ITCR2 */
6139 /* XXX : not implemented */
6140 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6141 SPR_NOACCESS, SPR_NOACCESS,
6142 &spr_read_generic, &spr_write_generic,
6143 0x00000000);
6144 /* L3ITCR3 */
6145 /* XXX : not implemented */
6146 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6147 SPR_NOACCESS, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 0x00000000);
6150 /* L3OHCR */
6151 /* XXX : not implemented */
6152 spr_register(env, SPR_L3OHCR, "L3OHCR",
6153 SPR_NOACCESS, SPR_NOACCESS,
6154 &spr_read_generic, &spr_write_generic,
6155 0x00000000);
6156 /* XXX : not implemented */
6157 spr_register(env, SPR_UBAMR, "UBAMR",
6158 &spr_read_ureg, SPR_NOACCESS,
6159 &spr_read_ureg, SPR_NOACCESS,
6160 0x00000000);
6161 /* LDSTCR */
6162 /* XXX : not implemented */
6163 spr_register(env, SPR_LDSTCR, "LDSTCR",
6164 SPR_NOACCESS, SPR_NOACCESS,
6165 &spr_read_generic, &spr_write_generic,
6166 0x00000000);
6167 /* ICTRL */
6168 /* XXX : not implemented */
6169 spr_register(env, SPR_ICTRL, "ICTRL",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, &spr_write_generic,
6172 0x00000000);
6173 /* MSSSR0 */
6174 /* XXX : not implemented */
6175 spr_register(env, SPR_MSSSR0, "MSSSR0",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 /* PMC */
6180 /* XXX : not implemented */
6181 spr_register(env, SPR_PMC5, "PMC5",
6182 SPR_NOACCESS, SPR_NOACCESS,
6183 &spr_read_generic, &spr_write_generic,
6184 0x00000000);
6185 /* XXX : not implemented */
6186 spr_register(env, SPR_UPMC5, "UPMC5",
6187 &spr_read_ureg, SPR_NOACCESS,
6188 &spr_read_ureg, SPR_NOACCESS,
6189 0x00000000);
6190 /* XXX : not implemented */
6191 spr_register(env, SPR_PMC6, "PMC6",
6192 SPR_NOACCESS, SPR_NOACCESS,
6193 &spr_read_generic, &spr_write_generic,
6194 0x00000000);
6195 /* XXX : not implemented */
6196 spr_register(env, SPR_UPMC6, "UPMC6",
6197 &spr_read_ureg, SPR_NOACCESS,
6198 &spr_read_ureg, SPR_NOACCESS,
6199 0x00000000);
6200 /* Memory management */
6201 gen_low_BATs(env);
6202 gen_74xx_soft_tlb(env, 128, 2);
6203 init_excp_7450(env);
6204 env->dcache_line_size = 32;
6205 env->icache_line_size = 32;
6206 /* Allocate hardware IRQ controller */
6207 ppc6xx_irq_init(env);
6208 }
6209
6210 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6211 {
6212 DeviceClass *dc = DEVICE_CLASS(oc);
6213 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6214
6215 dc->desc = "PowerPC 7450 (aka G4)";
6216 pcc->init_proc = init_proc_7450;
6217 pcc->check_pow = check_pow_hid0_74xx;
6218 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6219 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6220 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6221 PPC_FLOAT_STFIWX |
6222 PPC_CACHE | PPC_CACHE_ICBI |
6223 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6224 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6225 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6226 PPC_MEM_TLBIA | PPC_74xx_TLB |
6227 PPC_SEGMENT | PPC_EXTERN |
6228 PPC_ALTIVEC;
6229 pcc->insns_flags2 = PPC_NONE;
6230 pcc->msr_mask = 0x000000000205FF77ULL;
6231 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6232 pcc->excp_model = POWERPC_EXCP_74xx;
6233 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6234 pcc->bfd_mach = bfd_mach_ppc_7400;
6235 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6236 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6237 POWERPC_FLAG_BUS_CLK;
6238 }
6239
6240 static void init_proc_7445 (CPUPPCState *env)
6241 {
6242 gen_spr_ne_601(env);
6243 gen_spr_7xx(env);
6244 /* Time base */
6245 gen_tbl(env);
6246 /* 74xx specific SPR */
6247 gen_spr_74xx(env);
6248 /* LDSTCR */
6249 /* XXX : not implemented */
6250 spr_register(env, SPR_LDSTCR, "LDSTCR",
6251 SPR_NOACCESS, SPR_NOACCESS,
6252 &spr_read_generic, &spr_write_generic,
6253 0x00000000);
6254 /* ICTRL */
6255 /* XXX : not implemented */
6256 spr_register(env, SPR_ICTRL, "ICTRL",
6257 SPR_NOACCESS, SPR_NOACCESS,
6258 &spr_read_generic, &spr_write_generic,
6259 0x00000000);
6260 /* MSSSR0 */
6261 /* XXX : not implemented */
6262 spr_register(env, SPR_MSSSR0, "MSSSR0",
6263 SPR_NOACCESS, SPR_NOACCESS,
6264 &spr_read_generic, &spr_write_generic,
6265 0x00000000);
6266 /* PMC */
6267 /* XXX : not implemented */
6268 spr_register(env, SPR_PMC5, "PMC5",
6269 SPR_NOACCESS, SPR_NOACCESS,
6270 &spr_read_generic, &spr_write_generic,
6271 0x00000000);
6272 /* XXX : not implemented */
6273 spr_register(env, SPR_UPMC5, "UPMC5",
6274 &spr_read_ureg, SPR_NOACCESS,
6275 &spr_read_ureg, SPR_NOACCESS,
6276 0x00000000);
6277 /* XXX : not implemented */
6278 spr_register(env, SPR_PMC6, "PMC6",
6279 SPR_NOACCESS, SPR_NOACCESS,
6280 &spr_read_generic, &spr_write_generic,
6281 0x00000000);
6282 /* XXX : not implemented */
6283 spr_register(env, SPR_UPMC6, "UPMC6",
6284 &spr_read_ureg, SPR_NOACCESS,
6285 &spr_read_ureg, SPR_NOACCESS,
6286 0x00000000);
6287 /* SPRGs */
6288 spr_register(env, SPR_SPRG4, "SPRG4",
6289 SPR_NOACCESS, SPR_NOACCESS,
6290 &spr_read_generic, &spr_write_generic,
6291 0x00000000);
6292 spr_register(env, SPR_USPRG4, "USPRG4",
6293 &spr_read_ureg, SPR_NOACCESS,
6294 &spr_read_ureg, SPR_NOACCESS,
6295 0x00000000);
6296 spr_register(env, SPR_SPRG5, "SPRG5",
6297 SPR_NOACCESS, SPR_NOACCESS,
6298 &spr_read_generic, &spr_write_generic,
6299 0x00000000);
6300 spr_register(env, SPR_USPRG5, "USPRG5",
6301 &spr_read_ureg, SPR_NOACCESS,
6302 &spr_read_ureg, SPR_NOACCESS,
6303 0x00000000);
6304 spr_register(env, SPR_SPRG6, "SPRG6",
6305 SPR_NOACCESS, SPR_NOACCESS,
6306 &spr_read_generic, &spr_write_generic,
6307 0x00000000);
6308 spr_register(env, SPR_USPRG6, "USPRG6",
6309 &spr_read_ureg, SPR_NOACCESS,
6310 &spr_read_ureg, SPR_NOACCESS,
6311 0x00000000);
6312 spr_register(env, SPR_SPRG7, "SPRG7",
6313 SPR_NOACCESS, SPR_NOACCESS,
6314 &spr_read_generic, &spr_write_generic,
6315 0x00000000);
6316 spr_register(env, SPR_USPRG7, "USPRG7",
6317 &spr_read_ureg, SPR_NOACCESS,
6318 &spr_read_ureg, SPR_NOACCESS,
6319 0x00000000);
6320 /* Memory management */
6321 gen_low_BATs(env);
6322 gen_high_BATs(env);
6323 gen_74xx_soft_tlb(env, 128, 2);
6324 init_excp_7450(env);
6325 env->dcache_line_size = 32;
6326 env->icache_line_size = 32;
6327 /* Allocate hardware IRQ controller */
6328 ppc6xx_irq_init(env);
6329 }
6330
6331 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6332 {
6333 DeviceClass *dc = DEVICE_CLASS(oc);
6334 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6335
6336 dc->desc = "PowerPC 7445 (aka G4)";
6337 pcc->init_proc = init_proc_7445;
6338 pcc->check_pow = check_pow_hid0_74xx;
6339 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6340 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6341 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6342 PPC_FLOAT_STFIWX |
6343 PPC_CACHE | PPC_CACHE_ICBI |
6344 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6345 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6346 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6347 PPC_MEM_TLBIA | PPC_74xx_TLB |
6348 PPC_SEGMENT | PPC_EXTERN |
6349 PPC_ALTIVEC;
6350 pcc->insns_flags2 = PPC_NONE;
6351 pcc->msr_mask = 0x000000000205FF77ULL;
6352 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6353 pcc->excp_model = POWERPC_EXCP_74xx;
6354 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6355 pcc->bfd_mach = bfd_mach_ppc_7400;
6356 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6357 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6358 POWERPC_FLAG_BUS_CLK;
6359 }
6360
6361 static void init_proc_7455 (CPUPPCState *env)
6362 {
6363 gen_spr_ne_601(env);
6364 gen_spr_7xx(env);
6365 /* Time base */
6366 gen_tbl(env);
6367 /* 74xx specific SPR */
6368 gen_spr_74xx(env);
6369 /* Level 3 cache control */
6370 gen_l3_ctrl(env);
6371 /* LDSTCR */
6372 /* XXX : not implemented */
6373 spr_register(env, SPR_LDSTCR, "LDSTCR",
6374 SPR_NOACCESS, SPR_NOACCESS,
6375 &spr_read_generic, &spr_write_generic,
6376 0x00000000);
6377 /* ICTRL */
6378 /* XXX : not implemented */
6379 spr_register(env, SPR_ICTRL, "ICTRL",
6380 SPR_NOACCESS, SPR_NOACCESS,
6381 &spr_read_generic, &spr_write_generic,
6382 0x00000000);
6383 /* MSSSR0 */
6384 /* XXX : not implemented */
6385 spr_register(env, SPR_MSSSR0, "MSSSR0",
6386 SPR_NOACCESS, SPR_NOACCESS,
6387 &spr_read_generic, &spr_write_generic,
6388 0x00000000);
6389 /* PMC */
6390 /* XXX : not implemented */
6391 spr_register(env, SPR_PMC5, "PMC5",
6392 SPR_NOACCESS, SPR_NOACCESS,
6393 &spr_read_generic, &spr_write_generic,
6394 0x00000000);
6395 /* XXX : not implemented */
6396 spr_register(env, SPR_UPMC5, "UPMC5",
6397 &spr_read_ureg, SPR_NOACCESS,
6398 &spr_read_ureg, SPR_NOACCESS,
6399 0x00000000);
6400 /* XXX : not implemented */
6401 spr_register(env, SPR_PMC6, "PMC6",
6402 SPR_NOACCESS, SPR_NOACCESS,
6403 &spr_read_generic, &spr_write_generic,
6404 0x00000000);
6405 /* XXX : not implemented */
6406 spr_register(env, SPR_UPMC6, "UPMC6",
6407 &spr_read_ureg, SPR_NOACCESS,
6408 &spr_read_ureg, SPR_NOACCESS,
6409 0x00000000);
6410 /* SPRGs */
6411 spr_register(env, SPR_SPRG4, "SPRG4",
6412 SPR_NOACCESS, SPR_NOACCESS,
6413 &spr_read_generic, &spr_write_generic,
6414 0x00000000);
6415 spr_register(env, SPR_USPRG4, "USPRG4",
6416 &spr_read_ureg, SPR_NOACCESS,
6417 &spr_read_ureg, SPR_NOACCESS,
6418 0x00000000);
6419 spr_register(env, SPR_SPRG5, "SPRG5",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_generic, &spr_write_generic,
6422 0x00000000);
6423 spr_register(env, SPR_USPRG5, "USPRG5",
6424 &spr_read_ureg, SPR_NOACCESS,
6425 &spr_read_ureg, SPR_NOACCESS,
6426 0x00000000);
6427 spr_register(env, SPR_SPRG6, "SPRG6",
6428 SPR_NOACCESS, SPR_NOACCESS,
6429 &spr_read_generic, &spr_write_generic,
6430 0x00000000);
6431 spr_register(env, SPR_USPRG6, "USPRG6",
6432 &spr_read_ureg, SPR_NOACCESS,
6433 &spr_read_ureg, SPR_NOACCESS,
6434 0x00000000);
6435 spr_register(env, SPR_SPRG7, "SPRG7",
6436 SPR_NOACCESS, SPR_NOACCESS,
6437 &spr_read_generic, &spr_write_generic,
6438 0x00000000);
6439 spr_register(env, SPR_USPRG7, "USPRG7",
6440 &spr_read_ureg, SPR_NOACCESS,
6441 &spr_read_ureg, SPR_NOACCESS,
6442 0x00000000);
6443 /* Memory management */
6444 gen_low_BATs(env);
6445 gen_high_BATs(env);
6446 gen_74xx_soft_tlb(env, 128, 2);
6447 init_excp_7450(env);
6448 env->dcache_line_size = 32;
6449 env->icache_line_size = 32;
6450 /* Allocate hardware IRQ controller */
6451 ppc6xx_irq_init(env);
6452 }
6453
6454 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6455 {
6456 DeviceClass *dc = DEVICE_CLASS(oc);
6457 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6458
6459 dc->desc = "PowerPC 7455 (aka G4)";
6460 pcc->init_proc = init_proc_7455;
6461 pcc->check_pow = check_pow_hid0_74xx;
6462 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6463 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6464 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6465 PPC_FLOAT_STFIWX |
6466 PPC_CACHE | PPC_CACHE_ICBI |
6467 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6468 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6469 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6470 PPC_MEM_TLBIA | PPC_74xx_TLB |
6471 PPC_SEGMENT | PPC_EXTERN |
6472 PPC_ALTIVEC;
6473 pcc->insns_flags2 = PPC_NONE;
6474 pcc->msr_mask = 0x000000000205FF77ULL;
6475 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6476 pcc->excp_model = POWERPC_EXCP_74xx;
6477 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6478 pcc->bfd_mach = bfd_mach_ppc_7400;
6479 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6480 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6481 POWERPC_FLAG_BUS_CLK;
6482 }
6483
6484 static void init_proc_7457 (CPUPPCState *env)
6485 {
6486 gen_spr_ne_601(env);
6487 gen_spr_7xx(env);
6488 /* Time base */
6489 gen_tbl(env);
6490 /* 74xx specific SPR */
6491 gen_spr_74xx(env);
6492 /* Level 3 cache control */
6493 gen_l3_ctrl(env);
6494 /* L3ITCR1 */
6495 /* XXX : not implemented */
6496 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6497 SPR_NOACCESS, SPR_NOACCESS,
6498 &spr_read_generic, &spr_write_generic,
6499 0x00000000);
6500 /* L3ITCR2 */
6501 /* XXX : not implemented */
6502 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6503 SPR_NOACCESS, SPR_NOACCESS,
6504 &spr_read_generic, &spr_write_generic,
6505 0x00000000);
6506 /* L3ITCR3 */
6507 /* XXX : not implemented */
6508 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6509 SPR_NOACCESS, SPR_NOACCESS,
6510 &spr_read_generic, &spr_write_generic,
6511 0x00000000);
6512 /* L3OHCR */
6513 /* XXX : not implemented */
6514 spr_register(env, SPR_L3OHCR, "L3OHCR",
6515 SPR_NOACCESS, SPR_NOACCESS,
6516 &spr_read_generic, &spr_write_generic,
6517 0x00000000);
6518 /* LDSTCR */
6519 /* XXX : not implemented */
6520 spr_register(env, SPR_LDSTCR, "LDSTCR",
6521 SPR_NOACCESS, SPR_NOACCESS,
6522 &spr_read_generic, &spr_write_generic,
6523 0x00000000);
6524 /* ICTRL */
6525 /* XXX : not implemented */
6526 spr_register(env, SPR_ICTRL, "ICTRL",
6527 SPR_NOACCESS, SPR_NOACCESS,
6528 &spr_read_generic, &spr_write_generic,
6529 0x00000000);
6530 /* MSSSR0 */
6531 /* XXX : not implemented */
6532 spr_register(env, SPR_MSSSR0, "MSSSR0",
6533 SPR_NOACCESS, SPR_NOACCESS,
6534 &spr_read_generic, &spr_write_generic,
6535 0x00000000);
6536 /* PMC */
6537 /* XXX : not implemented */
6538 spr_register(env, SPR_PMC5, "PMC5",
6539 SPR_NOACCESS, SPR_NOACCESS,
6540 &spr_read_generic, &spr_write_generic,
6541 0x00000000);
6542 /* XXX : not implemented */
6543 spr_register(env, SPR_UPMC5, "UPMC5",
6544 &spr_read_ureg, SPR_NOACCESS,
6545 &spr_read_ureg, SPR_NOACCESS,
6546 0x00000000);
6547 /* XXX : not implemented */
6548 spr_register(env, SPR_PMC6, "PMC6",
6549 SPR_NOACCESS, SPR_NOACCESS,
6550 &spr_read_generic, &spr_write_generic,
6551 0x00000000);
6552 /* XXX : not implemented */
6553 spr_register(env, SPR_UPMC6, "UPMC6",
6554 &spr_read_ureg, SPR_NOACCESS,
6555 &spr_read_ureg, SPR_NOACCESS,
6556 0x00000000);
6557 /* SPRGs */
6558 spr_register(env, SPR_SPRG4, "SPRG4",
6559 SPR_NOACCESS, SPR_NOACCESS,
6560 &spr_read_generic, &spr_write_generic,
6561 0x00000000);
6562 spr_register(env, SPR_USPRG4, "USPRG4",
6563 &spr_read_ureg, SPR_NOACCESS,
6564 &spr_read_ureg, SPR_NOACCESS,
6565 0x00000000);
6566 spr_register(env, SPR_SPRG5, "SPRG5",
6567 SPR_NOACCESS, SPR_NOACCESS,
6568 &spr_read_generic, &spr_write_generic,
6569 0x00000000);
6570 spr_register(env, SPR_USPRG5, "USPRG5",
6571 &spr_read_ureg, SPR_NOACCESS,
6572 &spr_read_ureg, SPR_NOACCESS,
6573 0x00000000);
6574 spr_register(env, SPR_SPRG6, "SPRG6",
6575 SPR_NOACCESS, SPR_NOACCESS,
6576 &spr_read_generic, &spr_write_generic,
6577 0x00000000);
6578 spr_register(env, SPR_USPRG6, "USPRG6",
6579 &spr_read_ureg, SPR_NOACCESS,
6580 &spr_read_ureg, SPR_NOACCESS,
6581 0x00000000);
6582 spr_register(env, SPR_SPRG7, "SPRG7",
6583 SPR_NOACCESS, SPR_NOACCESS,
6584 &spr_read_generic, &spr_write_generic,
6585 0x00000000);
6586 spr_register(env, SPR_USPRG7, "USPRG7",
6587 &spr_read_ureg, SPR_NOACCESS,
6588 &spr_read_ureg, SPR_NOACCESS,
6589 0x00000000);
6590 /* Memory management */
6591 gen_low_BATs(env);
6592 gen_high_BATs(env);
6593 gen_74xx_soft_tlb(env, 128, 2);
6594 init_excp_7450(env);
6595 env->dcache_line_size = 32;
6596 env->icache_line_size = 32;
6597 /* Allocate hardware IRQ controller */
6598 ppc6xx_irq_init(env);
6599 }
6600
6601 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6602 {
6603 DeviceClass *dc = DEVICE_CLASS(oc);
6604 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6605
6606 dc->desc = "PowerPC 7457 (aka G4)";
6607 pcc->init_proc = init_proc_7457;
6608 pcc->check_pow = check_pow_hid0_74xx;
6609 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6610 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6611 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6612 PPC_FLOAT_STFIWX |
6613 PPC_CACHE | PPC_CACHE_ICBI |
6614 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6615 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6616 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6617 PPC_MEM_TLBIA | PPC_74xx_TLB |
6618 PPC_SEGMENT | PPC_EXTERN |
6619 PPC_ALTIVEC;
6620 pcc->insns_flags2 = PPC_NONE;
6621 pcc->msr_mask = 0x000000000205FF77ULL;
6622 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6623 pcc->excp_model = POWERPC_EXCP_74xx;
6624 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6625 pcc->bfd_mach = bfd_mach_ppc_7400;
6626 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6627 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6628 POWERPC_FLAG_BUS_CLK;
6629 }
6630
6631 #if defined (TARGET_PPC64)
6632 #if defined(CONFIG_USER_ONLY)
6633 #define POWERPC970_HID5_INIT 0x00000080
6634 #else
6635 #define POWERPC970_HID5_INIT 0x00000000
6636 #endif
6637
6638 static int check_pow_970 (CPUPPCState *env)
6639 {
6640 if (env->spr[SPR_HID0] & 0x00600000)
6641 return 1;
6642
6643 return 0;
6644 }
6645
6646 static void init_proc_970 (CPUPPCState *env)
6647 {
6648 gen_spr_ne_601(env);
6649 gen_spr_7xx(env);
6650 /* Time base */
6651 gen_tbl(env);
6652 /* Hardware implementation registers */
6653 /* XXX : not implemented */
6654 spr_register(env, SPR_HID0, "HID0",
6655 SPR_NOACCESS, SPR_NOACCESS,
6656 &spr_read_generic, &spr_write_clear,
6657 0x60000000);
6658 /* XXX : not implemented */
6659 spr_register(env, SPR_HID1, "HID1",
6660 SPR_NOACCESS, SPR_NOACCESS,
6661 &spr_read_generic, &spr_write_generic,
6662 0x00000000);
6663 /* XXX : not implemented */
6664 spr_register(env, SPR_750FX_HID2, "HID2",
6665 SPR_NOACCESS, SPR_NOACCESS,
6666 &spr_read_generic, &spr_write_generic,
6667 0x00000000);
6668 /* XXX : not implemented */
6669 spr_register(env, SPR_970_HID5, "HID5",
6670 SPR_NOACCESS, SPR_NOACCESS,
6671 &spr_read_generic, &spr_write_generic,
6672 POWERPC970_HID5_INIT);
6673 /* XXX : not implemented */
6674 spr_register(env, SPR_L2CR, "L2CR",
6675 SPR_NOACCESS, SPR_NOACCESS,
6676 &spr_read_generic, &spr_write_generic,
6677 0x00000000);
6678 /* Memory management */
6679 /* XXX: not correct */
6680 gen_low_BATs(env);
6681 /* XXX : not implemented */
6682 spr_register(env, SPR_MMUCFG, "MMUCFG",
6683 SPR_NOACCESS, SPR_NOACCESS,
6684 &spr_read_generic, SPR_NOACCESS,
6685 0x00000000); /* TOFIX */
6686 /* XXX : not implemented */
6687 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6688 SPR_NOACCESS, SPR_NOACCESS,
6689 &spr_read_generic, &spr_write_generic,
6690 0x00000000); /* TOFIX */
6691 spr_register(env, SPR_HIOR, "SPR_HIOR",
6692 SPR_NOACCESS, SPR_NOACCESS,
6693 &spr_read_hior, &spr_write_hior,
6694 0x00000000);
6695 #if !defined(CONFIG_USER_ONLY)
6696 env->slb_nr = 32;
6697 #endif
6698 init_excp_970(env);
6699 env->dcache_line_size = 128;
6700 env->icache_line_size = 128;
6701 /* Allocate hardware IRQ controller */
6702 ppc970_irq_init(env);
6703 /* Can't find information on what this should be on reset. This
6704 * value is the one used by 74xx processors. */
6705 vscr_init(env, 0x00010000);
6706 }
6707
6708 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6709 {
6710 DeviceClass *dc = DEVICE_CLASS(oc);
6711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6712
6713 dc->desc = "PowerPC 970";
6714 pcc->init_proc = init_proc_970;
6715 pcc->check_pow = check_pow_970;
6716 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6717 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6718 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6719 PPC_FLOAT_STFIWX |
6720 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6721 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6722 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6723 PPC_64B | PPC_ALTIVEC |
6724 PPC_SEGMENT_64B | PPC_SLBI;
6725 pcc->insns_flags2 = PPC_NONE;
6726 pcc->msr_mask = 0x900000000204FF36ULL;
6727 pcc->mmu_model = POWERPC_MMU_64B;
6728 pcc->excp_model = POWERPC_EXCP_970;
6729 pcc->bus_model = PPC_FLAGS_INPUT_970;
6730 pcc->bfd_mach = bfd_mach_ppc64;
6731 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6732 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6733 POWERPC_FLAG_BUS_CLK;
6734 }
6735
6736 static int check_pow_970FX (CPUPPCState *env)
6737 {
6738 if (env->spr[SPR_HID0] & 0x00600000)
6739 return 1;
6740
6741 return 0;
6742 }
6743
6744 static void init_proc_970FX (CPUPPCState *env)
6745 {
6746 gen_spr_ne_601(env);
6747 gen_spr_7xx(env);
6748 /* Time base */
6749 gen_tbl(env);
6750 /* Hardware implementation registers */
6751 /* XXX : not implemented */
6752 spr_register(env, SPR_HID0, "HID0",
6753 SPR_NOACCESS, SPR_NOACCESS,
6754 &spr_read_generic, &spr_write_clear,
6755 0x60000000);
6756 /* XXX : not implemented */
6757 spr_register(env, SPR_HID1, "HID1",
6758 SPR_NOACCESS, SPR_NOACCESS,
6759 &spr_read_generic, &spr_write_generic,
6760 0x00000000);
6761 /* XXX : not implemented */
6762 spr_register(env, SPR_750FX_HID2, "HID2",
6763 SPR_NOACCESS, SPR_NOACCESS,
6764 &spr_read_generic, &spr_write_generic,
6765 0x00000000);
6766 /* XXX : not implemented */
6767 spr_register(env, SPR_970_HID5, "HID5",
6768 SPR_NOACCESS, SPR_NOACCESS,
6769 &spr_read_generic, &spr_write_generic,
6770 POWERPC970_HID5_INIT);
6771 /* XXX : not implemented */
6772 spr_register(env, SPR_L2CR, "L2CR",
6773 SPR_NOACCESS, SPR_NOACCESS,
6774 &spr_read_generic, &spr_write_generic,
6775 0x00000000);
6776 /* Memory management */
6777 /* XXX: not correct */
6778 gen_low_BATs(env);
6779 /* XXX : not implemented */
6780 spr_register(env, SPR_MMUCFG, "MMUCFG",
6781 SPR_NOACCESS, SPR_NOACCESS,
6782 &spr_read_generic, SPR_NOACCESS,
6783 0x00000000); /* TOFIX */
6784 /* XXX : not implemented */
6785 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6786 SPR_NOACCESS, SPR_NOACCESS,
6787 &spr_read_generic, &spr_write_generic,
6788 0x00000000); /* TOFIX */
6789 spr_register(env, SPR_HIOR, "SPR_HIOR",
6790 SPR_NOACCESS, SPR_NOACCESS,
6791 &spr_read_hior, &spr_write_hior,
6792 0x00000000);
6793 spr_register(env, SPR_CTRL, "SPR_CTRL",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 &spr_read_generic, &spr_write_generic,
6796 0x00000000);
6797 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6798 SPR_NOACCESS, SPR_NOACCESS,
6799 &spr_read_generic, &spr_write_generic,
6800 0x00000000);
6801 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6802 &spr_read_generic, &spr_write_generic,
6803 &spr_read_generic, &spr_write_generic,
6804 0x00000000);
6805 #if !defined(CONFIG_USER_ONLY)
6806 env->slb_nr = 64;
6807 #endif
6808 init_excp_970(env);
6809 env->dcache_line_size = 128;
6810 env->icache_line_size = 128;
6811 /* Allocate hardware IRQ controller */
6812 ppc970_irq_init(env);
6813 /* Can't find information on what this should be on reset. This
6814 * value is the one used by 74xx processors. */
6815 vscr_init(env, 0x00010000);
6816 }
6817
6818 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6819 {
6820 DeviceClass *dc = DEVICE_CLASS(oc);
6821 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6822
6823 dc->desc = "PowerPC 970FX (aka G5)";
6824 pcc->init_proc = init_proc_970FX;
6825 pcc->check_pow = check_pow_970FX;
6826 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6827 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6828 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6829 PPC_FLOAT_STFIWX |
6830 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6831 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6832 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6833 PPC_64B | PPC_ALTIVEC |
6834 PPC_SEGMENT_64B | PPC_SLBI;
6835 pcc->insns_flags2 = PPC_NONE;
6836 pcc->msr_mask = 0x800000000204FF36ULL;
6837 pcc->mmu_model = POWERPC_MMU_64B;
6838 pcc->excp_model = POWERPC_EXCP_970;
6839 pcc->bus_model = PPC_FLAGS_INPUT_970;
6840 pcc->bfd_mach = bfd_mach_ppc64;
6841 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6842 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6843 POWERPC_FLAG_BUS_CLK;
6844 }
6845
6846 static int check_pow_970GX (CPUPPCState *env)
6847 {
6848 if (env->spr[SPR_HID0] & 0x00600000)
6849 return 1;
6850
6851 return 0;
6852 }
6853
6854 static void init_proc_970GX (CPUPPCState *env)
6855 {
6856 gen_spr_ne_601(env);
6857 gen_spr_7xx(env);
6858 /* Time base */
6859 gen_tbl(env);
6860 /* Hardware implementation registers */
6861 /* XXX : not implemented */
6862 spr_register(env, SPR_HID0, "HID0",
6863 SPR_NOACCESS, SPR_NOACCESS,
6864 &spr_read_generic, &spr_write_clear,
6865 0x60000000);
6866 /* XXX : not implemented */
6867 spr_register(env, SPR_HID1, "HID1",
6868 SPR_NOACCESS, SPR_NOACCESS,
6869 &spr_read_generic, &spr_write_generic,
6870 0x00000000);
6871 /* XXX : not implemented */
6872 spr_register(env, SPR_750FX_HID2, "HID2",
6873 SPR_NOACCESS, SPR_NOACCESS,
6874 &spr_read_generic, &spr_write_generic,
6875 0x00000000);
6876 /* XXX : not implemented */
6877 spr_register(env, SPR_970_HID5, "HID5",
6878 SPR_NOACCESS, SPR_NOACCESS,
6879 &spr_read_generic, &spr_write_generic,
6880 POWERPC970_HID5_INIT);
6881 /* XXX : not implemented */
6882 spr_register(env, SPR_L2CR, "L2CR",
6883 SPR_NOACCESS, SPR_NOACCESS,
6884 &spr_read_generic, &spr_write_generic,
6885 0x00000000);
6886 /* Memory management */
6887 /* XXX: not correct */
6888 gen_low_BATs(env);
6889 /* XXX : not implemented */
6890 spr_register(env, SPR_MMUCFG, "MMUCFG",
6891 SPR_NOACCESS, SPR_NOACCESS,
6892 &spr_read_generic, SPR_NOACCESS,
6893 0x00000000); /* TOFIX */
6894 /* XXX : not implemented */
6895 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6896 SPR_NOACCESS, SPR_NOACCESS,
6897 &spr_read_generic, &spr_write_generic,
6898 0x00000000); /* TOFIX */
6899 spr_register(env, SPR_HIOR, "SPR_HIOR",
6900 SPR_NOACCESS, SPR_NOACCESS,
6901 &spr_read_hior, &spr_write_hior,
6902 0x00000000);
6903 #if !defined(CONFIG_USER_ONLY)
6904 env->slb_nr = 32;
6905 #endif
6906 init_excp_970(env);
6907 env->dcache_line_size = 128;
6908 env->icache_line_size = 128;
6909 /* Allocate hardware IRQ controller */
6910 ppc970_irq_init(env);
6911 /* Can't find information on what this should be on reset. This
6912 * value is the one used by 74xx processors. */
6913 vscr_init(env, 0x00010000);
6914 }
6915
6916 POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6917 {
6918 DeviceClass *dc = DEVICE_CLASS(oc);
6919 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6920
6921 dc->desc = "PowerPC 970 GX";
6922 pcc->init_proc = init_proc_970GX;
6923 pcc->check_pow = check_pow_970GX;
6924 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6925 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6926 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6927 PPC_FLOAT_STFIWX |
6928 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6929 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6930 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6931 PPC_64B | PPC_ALTIVEC |
6932 PPC_SEGMENT_64B | PPC_SLBI;
6933 pcc->insns_flags2 = PPC_NONE;
6934 pcc->msr_mask = 0x800000000204FF36ULL;
6935 pcc->mmu_model = POWERPC_MMU_64B;
6936 pcc->excp_model = POWERPC_EXCP_970;
6937 pcc->bus_model = PPC_FLAGS_INPUT_970;
6938 pcc->bfd_mach = bfd_mach_ppc64;
6939 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6940 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6941 POWERPC_FLAG_BUS_CLK;
6942 }
6943
6944 static int check_pow_970MP (CPUPPCState *env)
6945 {
6946 if (env->spr[SPR_HID0] & 0x01C00000)
6947 return 1;
6948
6949 return 0;
6950 }
6951
6952 static void init_proc_970MP (CPUPPCState *env)
6953 {
6954 gen_spr_ne_601(env);
6955 gen_spr_7xx(env);
6956 /* Time base */
6957 gen_tbl(env);
6958 /* Hardware implementation registers */
6959 /* XXX : not implemented */
6960 spr_register(env, SPR_HID0, "HID0",
6961 SPR_NOACCESS, SPR_NOACCESS,
6962 &spr_read_generic, &spr_write_clear,
6963 0x60000000);
6964 /* XXX : not implemented */
6965 spr_register(env, SPR_HID1, "HID1",
6966 SPR_NOACCESS, SPR_NOACCESS,
6967 &spr_read_generic, &spr_write_generic,
6968 0x00000000);
6969 /* XXX : not implemented */
6970 spr_register(env, SPR_750FX_HID2, "HID2",
6971 SPR_NOACCESS, SPR_NOACCESS,
6972 &spr_read_generic, &spr_write_generic,
6973 0x00000000);
6974 /* XXX : not implemented */
6975 spr_register(env, SPR_970_HID5, "HID5",
6976 SPR_NOACCESS, SPR_NOACCESS,
6977 &spr_read_generic, &spr_write_generic,
6978 POWERPC970_HID5_INIT);
6979 /* XXX : not implemented */
6980 spr_register(env, SPR_L2CR, "L2CR",
6981 SPR_NOACCESS, SPR_NOACCESS,
6982 &spr_read_generic, &spr_write_generic,
6983 0x00000000);
6984 /* Memory management */
6985 /* XXX: not correct */
6986 gen_low_BATs(env);
6987 /* XXX : not implemented */
6988 spr_register(env, SPR_MMUCFG, "MMUCFG",
6989 SPR_NOACCESS, SPR_NOACCESS,
6990 &spr_read_generic, SPR_NOACCESS,
6991 0x00000000); /* TOFIX */
6992 /* XXX : not implemented */
6993 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6994 SPR_NOACCESS, SPR_NOACCESS,
6995 &spr_read_generic, &spr_write_generic,
6996 0x00000000); /* TOFIX */
6997 spr_register(env, SPR_HIOR, "SPR_HIOR",
6998 SPR_NOACCESS, SPR_NOACCESS,
6999 &spr_read_hior, &spr_write_hior,
7000 0x00000000);
7001 #if !defined(CONFIG_USER_ONLY)
7002 env->slb_nr = 32;
7003 #endif
7004 init_excp_970(env);
7005 env->dcache_line_size = 128;
7006 env->icache_line_size = 128;
7007 /* Allocate hardware IRQ controller */
7008 ppc970_irq_init(env);
7009 /* Can't find information on what this should be on reset. This
7010 * value is the one used by 74xx processors. */
7011 vscr_init(env, 0x00010000);
7012 }
7013
7014 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
7015 {
7016 DeviceClass *dc = DEVICE_CLASS(oc);
7017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7018
7019 dc->desc = "PowerPC 970 MP";
7020 pcc->init_proc = init_proc_970MP;
7021 pcc->check_pow = check_pow_970MP;
7022 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7023 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7024 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7025 PPC_FLOAT_STFIWX |
7026 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7027 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7028 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7029 PPC_64B | PPC_ALTIVEC |
7030 PPC_SEGMENT_64B | PPC_SLBI;
7031 pcc->insns_flags2 = PPC_NONE;
7032 pcc->msr_mask = 0x900000000204FF36ULL;
7033 pcc->mmu_model = POWERPC_MMU_64B;
7034 pcc->excp_model = POWERPC_EXCP_970;
7035 pcc->bus_model = PPC_FLAGS_INPUT_970;
7036 pcc->bfd_mach = bfd_mach_ppc64;
7037 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7038 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7039 POWERPC_FLAG_BUS_CLK;
7040 }
7041
7042 static void init_proc_POWER7 (CPUPPCState *env)
7043 {
7044 gen_spr_ne_601(env);
7045 gen_spr_7xx(env);
7046 /* Time base */
7047 gen_tbl(env);
7048 /* Processor identification */
7049 spr_register(env, SPR_PIR, "PIR",
7050 SPR_NOACCESS, SPR_NOACCESS,
7051 &spr_read_generic, &spr_write_pir,
7052 0x00000000);
7053 #if !defined(CONFIG_USER_ONLY)
7054 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7055 spr_register_kvm(env, SPR_PURR, "PURR",
7056 &spr_read_purr, SPR_NOACCESS,
7057 &spr_read_purr, SPR_NOACCESS,
7058 KVM_REG_PPC_PURR, 0x00000000);
7059 spr_register_kvm(env, SPR_SPURR, "SPURR",
7060 &spr_read_purr, SPR_NOACCESS,
7061 &spr_read_purr, SPR_NOACCESS,
7062 KVM_REG_PPC_SPURR, 0x00000000);
7063 spr_register(env, SPR_CFAR, "SPR_CFAR",
7064 SPR_NOACCESS, SPR_NOACCESS,
7065 &spr_read_cfar, &spr_write_cfar,
7066 0x00000000);
7067 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7068 SPR_NOACCESS, SPR_NOACCESS,
7069 &spr_read_generic, &spr_write_generic,
7070 KVM_REG_PPC_DSCR, 0x00000000);
7071 #endif /* !CONFIG_USER_ONLY */
7072 /* Memory management */
7073 /* XXX : not implemented */
7074 spr_register(env, SPR_MMUCFG, "MMUCFG",
7075 SPR_NOACCESS, SPR_NOACCESS,
7076 &spr_read_generic, SPR_NOACCESS,
7077 0x00000000); /* TOFIX */
7078 /* XXX : not implemented */
7079 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7080 SPR_NOACCESS, SPR_NOACCESS,
7081 &spr_read_generic, &spr_write_generic,
7082 0x80800000);
7083 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7084 SPR_NOACCESS, SPR_NOACCESS,
7085 &spr_read_generic, &spr_write_generic,
7086 0x80800000);
7087 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7088 &spr_read_generic, &spr_write_generic,
7089 &spr_read_generic, &spr_write_generic,
7090 0x00000000);
7091 #if !defined(CONFIG_USER_ONLY)
7092 env->slb_nr = 32;
7093 #endif
7094 init_excp_POWER7(env);
7095 env->dcache_line_size = 128;
7096 env->icache_line_size = 128;
7097 /* Allocate hardware IRQ controller */
7098 ppcPOWER7_irq_init(env);
7099 /* Can't find information on what this should be on reset. This
7100 * value is the one used by 74xx processors. */
7101 vscr_init(env, 0x00010000);
7102 }
7103
7104 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7105 {
7106 DeviceClass *dc = DEVICE_CLASS(oc);
7107 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7108
7109 dc->desc = "POWER7";
7110 pcc->init_proc = init_proc_POWER7;
7111 pcc->check_pow = check_pow_nocheck;
7112 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7113 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7114 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7115 PPC_FLOAT_STFIWX |
7116 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7117 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7118 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7119 PPC_64B | PPC_ALTIVEC |
7120 PPC_SEGMENT_64B | PPC_SLBI |
7121 PPC_POPCNTB | PPC_POPCNTWD;
7122 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
7123 pcc->msr_mask = 0x800000000204FF36ULL;
7124 pcc->mmu_model = POWERPC_MMU_2_06;
7125 pcc->excp_model = POWERPC_EXCP_POWER7;
7126 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7127 pcc->bfd_mach = bfd_mach_ppc64;
7128 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7129 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7130 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
7131 }
7132
7133 static void init_proc_620 (CPUPPCState *env)
7134 {
7135 gen_spr_ne_601(env);
7136 gen_spr_620(env);
7137 /* Time base */
7138 gen_tbl(env);
7139 /* Hardware implementation registers */
7140 /* XXX : not implemented */
7141 spr_register(env, SPR_HID0, "HID0",
7142 SPR_NOACCESS, SPR_NOACCESS,
7143 &spr_read_generic, &spr_write_generic,
7144 0x00000000);
7145 /* Memory management */
7146 gen_low_BATs(env);
7147 init_excp_620(env);
7148 env->dcache_line_size = 64;
7149 env->icache_line_size = 64;
7150 /* Allocate hardware IRQ controller */
7151 ppc6xx_irq_init(env);
7152 }
7153
7154 POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
7155 {
7156 DeviceClass *dc = DEVICE_CLASS(oc);
7157 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7158
7159 dc->desc = "PowerPC 620";
7160 pcc->init_proc = init_proc_620;
7161 pcc->check_pow = check_pow_nocheck; /* Check this */
7162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7163 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7164 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7165 PPC_FLOAT_STFIWX |
7166 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7167 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7168 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7169 PPC_SEGMENT | PPC_EXTERN |
7170 PPC_64B | PPC_SLBI;
7171 pcc->insns_flags2 = PPC_NONE;
7172 pcc->msr_mask = 0x800000000005FF77ULL;
7173 pcc->mmu_model = POWERPC_MMU_620;
7174 pcc->excp_model = POWERPC_EXCP_970;
7175 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7176 pcc->bfd_mach = bfd_mach_ppc64;
7177 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
7178 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7179 }
7180
7181 #endif /* defined (TARGET_PPC64) */
7182
7183
7184 typedef struct PowerPCCPUAlias {
7185 const char *alias;
7186 const char *model;
7187 } PowerPCCPUAlias;
7188
7189 static const PowerPCCPUAlias ppc_cpu_aliases[] = {
7190 { "403", "403GC" },
7191 { "405", "405D4" },
7192 { "405CR", "405CRc" },
7193 { "405GP", "405GPd" },
7194 { "405GPe", "405CRc" },
7195 { "x2vp7", "x2vp4" },
7196 { "x2vp50", "x2vp20" },
7197
7198 { "440EP", "440EPb" },
7199 { "440GP", "440GPc" },
7200 { "440GR", "440GRa" },
7201 { "440GX", "440GXf" },
7202
7203 { "RCPU", "MPC5xx" },
7204 /* MPC5xx microcontrollers */
7205 { "MGT560", "MPC5xx" },
7206 { "MPC509", "MPC5xx" },
7207 { "MPC533", "MPC5xx" },
7208 { "MPC534", "MPC5xx" },
7209 { "MPC555", "MPC5xx" },
7210 { "MPC556", "MPC5xx" },
7211 { "MPC560", "MPC5xx" },
7212 { "MPC561", "MPC5xx" },
7213 { "MPC562", "MPC5xx" },
7214 { "MPC563", "MPC5xx" },
7215 { "MPC564", "MPC5xx" },
7216 { "MPC565", "MPC5xx" },
7217 { "MPC566", "MPC5xx" },
7218
7219 { "PowerQUICC", "MPC8xx" },
7220 /* MPC8xx microcontrollers */
7221 { "MGT823", "MPC8xx" },
7222 { "MPC821", "MPC8xx" },
7223 { "MPC823", "MPC8xx" },
7224 { "MPC850", "MPC8xx" },
7225 { "MPC852T", "MPC8xx" },
7226 { "MPC855T", "MPC8xx" },
7227 { "MPC857", "MPC8xx" },
7228 { "MPC859", "MPC8xx" },
7229 { "MPC860", "MPC8xx" },
7230 { "MPC862", "MPC8xx" },
7231 { "MPC866", "MPC8xx" },
7232 { "MPC870", "MPC8xx" },
7233 { "MPC875", "MPC8xx" },
7234 { "MPC880", "MPC8xx" },
7235 { "MPC885", "MPC8xx" },
7236
7237 /* PowerPC MPC603 microcontrollers */
7238 { "MPC8240", "603" },
7239
7240 { "MPC52xx", "MPC5200" },
7241 { "MPC5200", "MPC5200_v12" },
7242 { "MPC5200B", "MPC5200B_v21" },
7243
7244 { "MPC82xx", "MPC8280" },
7245 { "PowerQUICC-II", "MPC82xx" },
7246 { "MPC8241", "G2HiP4" },
7247 { "MPC8245", "G2HiP4" },
7248 { "MPC8247", "G2leGP3" },
7249 { "MPC8248", "G2leGP3" },
7250 { "MPC8250", "MPC8250_HiP4" },
7251 { "MPC8250_HiP3", "G2HiP3" },
7252 { "MPC8250_HiP4", "G2HiP4" },
7253 { "MPC8255", "MPC8255_HiP4" },
7254 { "MPC8255_HiP3", "G2HiP3" },
7255 { "MPC8255_HiP4", "G2HiP4" },
7256 { "MPC8260", "MPC8260_HiP4" },
7257 { "MPC8260_HiP3", "G2HiP3" },
7258 { "MPC8260_HiP4", "G2HiP4" },
7259 { "MPC8264", "MPC8264_HiP4" },
7260 { "MPC8264_HiP3", "G2HiP3" },
7261 { "MPC8264_HiP4", "G2HiP4" },
7262 { "MPC8265", "MPC8265_HiP4" },
7263 { "MPC8265_HiP3", "G2HiP3" },
7264 { "MPC8265_HiP4", "G2HiP4" },
7265 { "MPC8266", "MPC8266_HiP4" },
7266 { "MPC8266_HiP3", "G2HiP3" },
7267 { "MPC8266_HiP4", "G2HiP4" },
7268 { "MPC8270", "G2leGP3" },
7269 { "MPC8271", "G2leGP3" },
7270 { "MPC8272", "G2leGP3" },
7271 { "MPC8275", "G2leGP3" },
7272 { "MPC8280", "G2leGP3" },
7273 { "e200", "e200z6" },
7274 { "e300", "e300c3" },
7275 { "MPC8347", "MPC8347T" },
7276 { "MPC8347A", "MPC8347AT" },
7277 { "MPC8347E", "MPC8347ET" },
7278 { "MPC8347EA", "MPC8347EAT" },
7279 { "e500", "e500v2_v22" },
7280 { "e500v1", "e500_v20" },
7281 { "e500v2", "e500v2_v22" },
7282 { "MPC8533", "MPC8533_v11" },
7283 { "MPC8533E", "MPC8533E_v11" },
7284 { "MPC8540", "MPC8540_v21" },
7285 { "MPC8541", "MPC8541_v11" },
7286 { "MPC8541E", "MPC8541E_v11" },
7287 { "MPC8543", "MPC8543_v21" },
7288 { "MPC8543E", "MPC8543E_v21" },
7289 { "MPC8544", "MPC8544_v11" },
7290 { "MPC8544E", "MPC8544E_v11" },
7291 { "MPC8545", "MPC8545_v21" },
7292 { "MPC8545E", "MPC8545E_v21" },
7293 { "MPC8547E", "MPC8547E_v21" },
7294 { "MPC8548", "MPC8548_v21" },
7295 { "MPC8548E", "MPC8548E_v21" },
7296 { "MPC8555", "MPC8555_v11" },
7297 { "MPC8555E", "MPC8555E_v11" },
7298 { "MPC8560", "MPC8560_v21" },
7299 { "601", "601_v2" },
7300 { "601v", "601_v2" },
7301 { "Vanilla", "603" },
7302 { "603e", "603e_v4.1" },
7303 { "Stretch", "603e" },
7304 { "Vaillant", "603e7v" },
7305 { "603r", "603e7t" },
7306 { "Goldeneye", "603r" },
7307 { "604e", "604e_v2.4" },
7308 { "Sirocco", "604e" },
7309 { "Mach5", "604r" },
7310 { "740", "740_v3.1" },
7311 { "Arthur", "740" },
7312 { "750", "750_v3.1" },
7313 { "Typhoon", "750" },
7314 { "G3", "750" },
7315 { "Conan/Doyle", "750p" },
7316 { "750cl", "750cl_v2.0" },
7317 { "750cx", "750cx_v2.2" },
7318 { "750cxe", "750cxe_v3.1b" },
7319 { "750fx", "750fx_v2.3" },
7320 { "750gx", "750gx_v1.2" },
7321 { "750l", "750l_v3.2" },
7322 { "LoneStar", "750l" },
7323 { "745", "745_v2.8" },
7324 { "755", "755_v2.8" },
7325 { "Goldfinger", "755" },
7326 { "7400", "7400_v2.9" },
7327 { "Max", "7400" },
7328 { "G4", "7400" },
7329 { "7410", "7410_v1.4" },
7330 { "Nitro", "7410" },
7331 { "7448", "7448_v2.1" },
7332 { "7450", "7450_v2.1" },
7333 { "Vger", "7450" },
7334 { "7441", "7441_v2.3" },
7335 { "7451", "7451_v2.3" },
7336 { "7445", "7445_v3.2" },
7337 { "7455", "7455_v3.2" },
7338 { "Apollo6", "7455" },
7339 { "7447", "7447_v1.2" },
7340 { "7457", "7457_v1.2" },
7341 { "Apollo7", "7457" },
7342 { "7447A", "7447A_v1.2" },
7343 { "7457A", "7457A_v1.2" },
7344 { "Apollo7PM", "7457A_v1.0" },
7345 #if defined(TARGET_PPC64)
7346 { "Trident", "620" },
7347 { "POWER3", "630" },
7348 { "Boxer", "POWER3" },
7349 { "Dino", "POWER3" },
7350 { "POWER3+", "631" },
7351 { "POWER7", "POWER7_v2.3" },
7352 { "970fx", "970fx_v3.1" },
7353 { "970mp", "970mp_v1.1" },
7354 { "Apache", "RS64" },
7355 { "A35", "RS64" },
7356 { "NorthStar", "RS64-II" },
7357 { "A50", "RS64-II" },
7358 { "Pulsar", "RS64-III" },
7359 { "IceStar", "RS64-IV" },
7360 { "IStar", "RS64-IV" },
7361 { "SStar", "RS64-IV" },
7362 #endif
7363 { "RIOS", "POWER" },
7364 { "RSC", "POWER" },
7365 { "RSC3308", "POWER" },
7366 { "RSC4608", "POWER" },
7367 { "RSC2", "POWER2" },
7368 { "P2SC", "POWER2" },
7369
7370 /* Generic PowerPCs */
7371 #if defined(TARGET_PPC64)
7372 { "ppc64", "970fx" },
7373 #endif
7374 { "ppc32", "604" },
7375 { "ppc", "ppc32" },
7376 { "default", "ppc" },
7377 };
7378
7379 /*****************************************************************************/
7380 /* Generic CPU instantiation routine */
7381 static void init_ppc_proc(PowerPCCPU *cpu)
7382 {
7383 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7384 CPUPPCState *env = &cpu->env;
7385 #if !defined(CONFIG_USER_ONLY)
7386 int i;
7387
7388 env->irq_inputs = NULL;
7389 /* Set all exception vectors to an invalid address */
7390 for (i = 0; i < POWERPC_EXCP_NB; i++)
7391 env->excp_vectors[i] = (target_ulong)(-1ULL);
7392 env->hreset_excp_prefix = 0x00000000;
7393 env->ivor_mask = 0x00000000;
7394 env->ivpr_mask = 0x00000000;
7395 /* Default MMU definitions */
7396 env->nb_BATs = 0;
7397 env->nb_tlb = 0;
7398 env->nb_ways = 0;
7399 env->tlb_type = TLB_NONE;
7400 #endif
7401 /* Register SPR common to all PowerPC implementations */
7402 gen_spr_generic(env);
7403 spr_register(env, SPR_PVR, "PVR",
7404 /* Linux permits userspace to read PVR */
7405 #if defined(CONFIG_LINUX_USER)
7406 &spr_read_generic,
7407 #else
7408 SPR_NOACCESS,
7409 #endif
7410 SPR_NOACCESS,
7411 &spr_read_generic, SPR_NOACCESS,
7412 pcc->pvr);
7413 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7414 if (pcc->svr != POWERPC_SVR_NONE) {
7415 if (pcc->svr & POWERPC_SVR_E500) {
7416 spr_register(env, SPR_E500_SVR, "SVR",
7417 SPR_NOACCESS, SPR_NOACCESS,
7418 &spr_read_generic, SPR_NOACCESS,
7419 pcc->svr & ~POWERPC_SVR_E500);
7420 } else {
7421 spr_register(env, SPR_SVR, "SVR",
7422 SPR_NOACCESS, SPR_NOACCESS,
7423 &spr_read_generic, SPR_NOACCESS,
7424 pcc->svr);
7425 }
7426 }
7427 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7428 (*pcc->init_proc)(env);
7429 #if !defined(CONFIG_USER_ONLY)
7430 env->excp_prefix = env->hreset_excp_prefix;
7431 #endif
7432 /* MSR bits & flags consistency checks */
7433 if (env->msr_mask & (1 << 25)) {
7434 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7435 case POWERPC_FLAG_SPE:
7436 case POWERPC_FLAG_VRE:
7437 break;
7438 default:
7439 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7440 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7441 exit(1);
7442 }
7443 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7444 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7445 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7446 exit(1);
7447 }
7448 if (env->msr_mask & (1 << 17)) {
7449 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7450 case POWERPC_FLAG_TGPR:
7451 case POWERPC_FLAG_CE:
7452 break;
7453 default:
7454 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7455 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7456 exit(1);
7457 }
7458 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7459 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7460 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7461 exit(1);
7462 }
7463 if (env->msr_mask & (1 << 10)) {
7464 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7465 POWERPC_FLAG_UBLE)) {
7466 case POWERPC_FLAG_SE:
7467 case POWERPC_FLAG_DWE:
7468 case POWERPC_FLAG_UBLE:
7469 break;
7470 default:
7471 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7472 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7473 "POWERPC_FLAG_UBLE\n");
7474 exit(1);
7475 }
7476 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7477 POWERPC_FLAG_UBLE)) {
7478 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7479 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7480 "POWERPC_FLAG_UBLE\n");
7481 exit(1);
7482 }
7483 if (env->msr_mask & (1 << 9)) {
7484 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7485 case POWERPC_FLAG_BE:
7486 case POWERPC_FLAG_DE:
7487 break;
7488 default:
7489 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7490 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7491 exit(1);
7492 }
7493 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7494 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7495 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7496 exit(1);
7497 }
7498 if (env->msr_mask & (1 << 2)) {
7499 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7500 case POWERPC_FLAG_PX:
7501 case POWERPC_FLAG_PMM:
7502 break;
7503 default:
7504 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7505 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7506 exit(1);
7507 }
7508 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7509 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7510 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7511 exit(1);
7512 }
7513 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7514 fprintf(stderr, "PowerPC flags inconsistency\n"
7515 "Should define the time-base and decrementer clock source\n");
7516 exit(1);
7517 }
7518 /* Allocate TLBs buffer when needed */
7519 #if !defined(CONFIG_USER_ONLY)
7520 if (env->nb_tlb != 0) {
7521 int nb_tlb = env->nb_tlb;
7522 if (env->id_tlbs != 0)
7523 nb_tlb *= 2;
7524 switch (env->tlb_type) {
7525 case TLB_6XX:
7526 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
7527 break;
7528 case TLB_EMB:
7529 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
7530 break;
7531 case TLB_MAS:
7532 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
7533 break;
7534 }
7535 /* Pre-compute some useful values */
7536 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7537 }
7538 if (env->irq_inputs == NULL) {
7539 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7540 " Attempt QEMU to crash very soon !\n");
7541 }
7542 #endif
7543 if (env->check_pow == NULL) {
7544 fprintf(stderr, "WARNING: no power management check handler "
7545 "registered.\n"
7546 " Attempt QEMU to crash very soon !\n");
7547 }
7548 }
7549
7550 #if defined(PPC_DUMP_CPU)
7551 static void dump_ppc_sprs (CPUPPCState *env)
7552 {
7553 ppc_spr_t *spr;
7554 #if !defined(CONFIG_USER_ONLY)
7555 uint32_t sr, sw;
7556 #endif
7557 uint32_t ur, uw;
7558 int i, j, n;
7559
7560 printf("Special purpose registers:\n");
7561 for (i = 0; i < 32; i++) {
7562 for (j = 0; j < 32; j++) {
7563 n = (i << 5) | j;
7564 spr = &env->spr_cb[n];
7565 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7566 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7567 #if !defined(CONFIG_USER_ONLY)
7568 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7569 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7570 if (sw || sr || uw || ur) {
7571 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7572 (i << 5) | j, (i << 5) | j, spr->name,
7573 sw ? 'w' : '-', sr ? 'r' : '-',
7574 uw ? 'w' : '-', ur ? 'r' : '-');
7575 }
7576 #else
7577 if (uw || ur) {
7578 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7579 (i << 5) | j, (i << 5) | j, spr->name,
7580 uw ? 'w' : '-', ur ? 'r' : '-');
7581 }
7582 #endif
7583 }
7584 }
7585 fflush(stdout);
7586 fflush(stderr);
7587 }
7588 #endif
7589
7590 /*****************************************************************************/
7591 #include <stdlib.h>
7592 #include <string.h>
7593
7594 /* Opcode types */
7595 enum {
7596 PPC_DIRECT = 0, /* Opcode routine */
7597 PPC_INDIRECT = 1, /* Indirect opcode table */
7598 };
7599
7600 static inline int is_indirect_opcode (void *handler)
7601 {
7602 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
7603 }
7604
7605 static inline opc_handler_t **ind_table(void *handler)
7606 {
7607 return (opc_handler_t **)((uintptr_t)handler & ~3);
7608 }
7609
7610 /* Instruction table creation */
7611 /* Opcodes tables creation */
7612 static void fill_new_table (opc_handler_t **table, int len)
7613 {
7614 int i;
7615
7616 for (i = 0; i < len; i++)
7617 table[i] = &invalid_handler;
7618 }
7619
7620 static int create_new_table (opc_handler_t **table, unsigned char idx)
7621 {
7622 opc_handler_t **tmp;
7623
7624 tmp = malloc(0x20 * sizeof(opc_handler_t));
7625 fill_new_table(tmp, 0x20);
7626 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7627
7628 return 0;
7629 }
7630
7631 static int insert_in_table (opc_handler_t **table, unsigned char idx,
7632 opc_handler_t *handler)
7633 {
7634 if (table[idx] != &invalid_handler)
7635 return -1;
7636 table[idx] = handler;
7637
7638 return 0;
7639 }
7640
7641 static int register_direct_insn (opc_handler_t **ppc_opcodes,
7642 unsigned char idx, opc_handler_t *handler)
7643 {
7644 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7645 printf("*** ERROR: opcode %02x already assigned in main "
7646 "opcode table\n", idx);
7647 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7648 printf(" Registered handler '%s' - new handler '%s'\n",
7649 ppc_opcodes[idx]->oname, handler->oname);
7650 #endif
7651 return -1;
7652 }
7653
7654 return 0;
7655 }
7656
7657 static int register_ind_in_table (opc_handler_t **table,
7658 unsigned char idx1, unsigned char idx2,
7659 opc_handler_t *handler)
7660 {
7661 if (table[idx1] == &invalid_handler) {
7662 if (create_new_table(table, idx1) < 0) {
7663 printf("*** ERROR: unable to create indirect table "
7664 "idx=%02x\n", idx1);
7665 return -1;
7666 }
7667 } else {
7668 if (!is_indirect_opcode(table[idx1])) {
7669 printf("*** ERROR: idx %02x already assigned to a direct "
7670 "opcode\n", idx1);
7671 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7672 printf(" Registered handler '%s' - new handler '%s'\n",
7673 ind_table(table[idx1])[idx2]->oname, handler->oname);
7674 #endif
7675 return -1;
7676 }
7677 }
7678 if (handler != NULL &&
7679 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7680 printf("*** ERROR: opcode %02x already assigned in "
7681 "opcode table %02x\n", idx2, idx1);
7682 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7683 printf(" Registered handler '%s' - new handler '%s'\n",
7684 ind_table(table[idx1])[idx2]->oname, handler->oname);
7685 #endif
7686 return -1;
7687 }
7688
7689 return 0;
7690 }
7691
7692 static int register_ind_insn (opc_handler_t **ppc_opcodes,
7693 unsigned char idx1, unsigned char idx2,
7694 opc_handler_t *handler)
7695 {
7696 int ret;
7697
7698 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7699
7700 return ret;
7701 }
7702
7703 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
7704 unsigned char idx1, unsigned char idx2,
7705 unsigned char idx3, opc_handler_t *handler)
7706 {
7707 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7708 printf("*** ERROR: unable to join indirect table idx "
7709 "[%02x-%02x]\n", idx1, idx2);
7710 return -1;
7711 }
7712 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7713 handler) < 0) {
7714 printf("*** ERROR: unable to insert opcode "
7715 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7716 return -1;
7717 }
7718
7719 return 0;
7720 }
7721
7722 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
7723 {
7724 if (insn->opc2 != 0xFF) {
7725 if (insn->opc3 != 0xFF) {
7726 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7727 insn->opc3, &insn->handler) < 0)
7728 return -1;
7729 } else {
7730 if (register_ind_insn(ppc_opcodes, insn->opc1,
7731 insn->opc2, &insn->handler) < 0)
7732 return -1;
7733 }
7734 } else {
7735 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7736 return -1;
7737 }
7738
7739 return 0;
7740 }
7741
7742 static int test_opcode_table (opc_handler_t **table, int len)
7743 {
7744 int i, count, tmp;
7745
7746 for (i = 0, count = 0; i < len; i++) {
7747 /* Consistency fixup */
7748 if (table[i] == NULL)
7749 table[i] = &invalid_handler;
7750 if (table[i] != &invalid_handler) {
7751 if (is_indirect_opcode(table[i])) {
7752 tmp = test_opcode_table(ind_table(table[i]), 0x20);
7753 if (tmp == 0) {
7754 free(table[i]);
7755 table[i] = &invalid_handler;
7756 } else {
7757 count++;
7758 }
7759 } else {
7760 count++;
7761 }
7762 }
7763 }
7764
7765 return count;
7766 }
7767
7768 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
7769 {
7770 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
7771 printf("*** WARNING: no opcode defined !\n");
7772 }
7773
7774 /*****************************************************************************/
7775 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7776 {
7777 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7778 CPUPPCState *env = &cpu->env;
7779 opcode_t *opc;
7780
7781 fill_new_table(env->opcodes, 0x40);
7782 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7783 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7784 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7785 if (register_insn(env->opcodes, opc) < 0) {
7786 error_setg(errp, "ERROR initializing PowerPC instruction "
7787 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7788 opc->opc3);
7789 return;
7790 }
7791 }
7792 }
7793 fix_opcode_tables(env->opcodes);
7794 fflush(stdout);
7795 fflush(stderr);
7796 }
7797
7798 #if defined(PPC_DUMP_CPU)
7799 static void dump_ppc_insns (CPUPPCState *env)
7800 {
7801 opc_handler_t **table, *handler;
7802 const char *p, *q;
7803 uint8_t opc1, opc2, opc3;
7804
7805 printf("Instructions set:\n");
7806 /* opc1 is 6 bits long */
7807 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7808 table = env->opcodes;
7809 handler = table[opc1];
7810 if (is_indirect_opcode(handler)) {
7811 /* opc2 is 5 bits long */
7812 for (opc2 = 0; opc2 < 0x20; opc2++) {
7813 table = env->opcodes;
7814 handler = env->opcodes[opc1];
7815 table = ind_table(handler);
7816 handler = table[opc2];
7817 if (is_indirect_opcode(handler)) {
7818 table = ind_table(handler);
7819 /* opc3 is 5 bits long */
7820 for (opc3 = 0; opc3 < 0x20; opc3++) {
7821 handler = table[opc3];
7822 if (handler->handler != &gen_invalid) {
7823 /* Special hack to properly dump SPE insns */
7824 p = strchr(handler->oname, '_');
7825 if (p == NULL) {
7826 printf("INSN: %02x %02x %02x (%02d %04d) : "
7827 "%s\n",
7828 opc1, opc2, opc3, opc1,
7829 (opc3 << 5) | opc2,
7830 handler->oname);
7831 } else {
7832 q = "speundef";
7833 if ((p - handler->oname) != strlen(q) ||
7834 memcmp(handler->oname, q, strlen(q)) != 0) {
7835 /* First instruction */
7836 printf("INSN: %02x %02x %02x (%02d %04d) : "
7837 "%.*s\n",
7838 opc1, opc2 << 1, opc3, opc1,
7839 (opc3 << 6) | (opc2 << 1),
7840 (int)(p - handler->oname),
7841 handler->oname);
7842 }
7843 if (strcmp(p + 1, q) != 0) {
7844 /* Second instruction */
7845 printf("INSN: %02x %02x %02x (%02d %04d) : "
7846 "%s\n",
7847 opc1, (opc2 << 1) | 1, opc3, opc1,
7848 (opc3 << 6) | (opc2 << 1) | 1,
7849 p + 1);
7850 }
7851 }
7852 }
7853 }
7854 } else {
7855 if (handler->handler != &gen_invalid) {
7856 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7857 opc1, opc2, opc1, opc2, handler->oname);
7858 }
7859 }
7860 }
7861 } else {
7862 if (handler->handler != &gen_invalid) {
7863 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7864 opc1, opc1, handler->oname);
7865 }
7866 }
7867 }
7868 }
7869 #endif
7870
7871 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7872 {
7873 if (n < 32) {
7874 stfq_p(mem_buf, env->fpr[n]);
7875 return 8;
7876 }
7877 if (n == 32) {
7878 stl_p(mem_buf, env->fpscr);
7879 return 4;
7880 }
7881 return 0;
7882 }
7883
7884 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7885 {
7886 if (n < 32) {
7887 env->fpr[n] = ldfq_p(mem_buf);
7888 return 8;
7889 }
7890 if (n == 32) {
7891 /* FPSCR not implemented */
7892 return 4;
7893 }
7894 return 0;
7895 }
7896
7897 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7898 {
7899 if (n < 32) {
7900 #ifdef HOST_WORDS_BIGENDIAN
7901 stq_p(mem_buf, env->avr[n].u64[0]);
7902 stq_p(mem_buf+8, env->avr[n].u64[1]);
7903 #else
7904 stq_p(mem_buf, env->avr[n].u64[1]);
7905 stq_p(mem_buf+8, env->avr[n].u64[0]);
7906 #endif
7907 return 16;
7908 }
7909 if (n == 32) {
7910 stl_p(mem_buf, env->vscr);
7911 return 4;
7912 }
7913 if (n == 33) {
7914 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7915 return 4;
7916 }
7917 return 0;
7918 }
7919
7920 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7921 {
7922 if (n < 32) {
7923 #ifdef HOST_WORDS_BIGENDIAN
7924 env->avr[n].u64[0] = ldq_p(mem_buf);
7925 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7926 #else
7927 env->avr[n].u64[1] = ldq_p(mem_buf);
7928 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7929 #endif
7930 return 16;
7931 }
7932 if (n == 32) {
7933 env->vscr = ldl_p(mem_buf);
7934 return 4;
7935 }
7936 if (n == 33) {
7937 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7938 return 4;
7939 }
7940 return 0;
7941 }
7942
7943 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7944 {
7945 if (n < 32) {
7946 #if defined(TARGET_PPC64)
7947 stl_p(mem_buf, env->gpr[n] >> 32);
7948 #else
7949 stl_p(mem_buf, env->gprh[n]);
7950 #endif
7951 return 4;
7952 }
7953 if (n == 32) {
7954 stq_p(mem_buf, env->spe_acc);
7955 return 8;
7956 }
7957 if (n == 33) {
7958 stl_p(mem_buf, env->spe_fscr);
7959 return 4;
7960 }
7961 return 0;
7962 }
7963
7964 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7965 {
7966 if (n < 32) {
7967 #if defined(TARGET_PPC64)
7968 target_ulong lo = (uint32_t)env->gpr[n];
7969 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7970 env->gpr[n] = lo | hi;
7971 #else
7972 env->gprh[n] = ldl_p(mem_buf);
7973 #endif
7974 return 4;
7975 }
7976 if (n == 32) {
7977 env->spe_acc = ldq_p(mem_buf);
7978 return 8;
7979 }
7980 if (n == 33) {
7981 env->spe_fscr = ldl_p(mem_buf);
7982 return 4;
7983 }
7984 return 0;
7985 }
7986
7987 static int ppc_fixup_cpu(PowerPCCPU *cpu)
7988 {
7989 CPUPPCState *env = &cpu->env;
7990
7991 /* TCG doesn't (yet) emulate some groups of instructions that
7992 * are implemented on some otherwise supported CPUs (e.g. VSX
7993 * and decimal floating point instructions on POWER7). We
7994 * remove unsupported instruction groups from the cpu state's
7995 * instruction masks and hope the guest can cope. For at
7996 * least the pseries machine, the unavailability of these
7997 * instructions can be advertised to the guest via the device
7998 * tree. */
7999 if ((env->insns_flags & ~PPC_TCG_INSNS)
8000 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
8001 fprintf(stderr, "Warning: Disabling some instructions which are not "
8002 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
8003 env->insns_flags & ~PPC_TCG_INSNS,
8004 env->insns_flags2 & ~PPC_TCG_INSNS2);
8005 }
8006 env->insns_flags &= PPC_TCG_INSNS;
8007 env->insns_flags2 &= PPC_TCG_INSNS2;
8008 return 0;
8009 }
8010
8011 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
8012 {
8013 PowerPCCPU *cpu = POWERPC_CPU(dev);
8014 CPUPPCState *env = &cpu->env;
8015 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8016 Error *local_err = NULL;
8017 #if !defined(CONFIG_USER_ONLY)
8018 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
8019 #endif
8020
8021 #if !defined(CONFIG_USER_ONLY)
8022 if (smp_threads > max_smt) {
8023 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
8024 max_smt, kvm_enabled() ? "KVM" : "TCG");
8025 return;
8026 }
8027 #endif
8028
8029 if (kvm_enabled()) {
8030 if (kvmppc_fixup_cpu(cpu) != 0) {
8031 error_setg(errp, "Unable to virtualize selected CPU with KVM");
8032 return;
8033 }
8034 } else {
8035 if (ppc_fixup_cpu(cpu) != 0) {
8036 error_setg(errp, "Unable to emulate selected CPU with TCG");
8037 return;
8038 }
8039 }
8040
8041 #if defined(TARGET_PPCEMB)
8042 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8043 error_setg(errp, "CPU does not possess a BookE MMU. "
8044 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
8045 "or choose another CPU model.");
8046 return;
8047 }
8048 #endif
8049
8050 create_ppc_opcodes(cpu, &local_err);
8051 if (local_err != NULL) {
8052 error_propagate(errp, local_err);
8053 return;
8054 }
8055 init_ppc_proc(cpu);
8056
8057 if (pcc->insns_flags & PPC_FLOAT) {
8058 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
8059 33, "power-fpu.xml", 0);
8060 }
8061 if (pcc->insns_flags & PPC_ALTIVEC) {
8062 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
8063 34, "power-altivec.xml", 0);
8064 }
8065 if (pcc->insns_flags & PPC_SPE) {
8066 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
8067 34, "power-spe.xml", 0);
8068 }
8069
8070 qemu_init_vcpu(env);
8071
8072 pcc->parent_realize(dev, errp);
8073
8074 #if defined(PPC_DUMP_CPU)
8075 {
8076 const char *mmu_model, *excp_model, *bus_model;
8077 switch (env->mmu_model) {
8078 case POWERPC_MMU_32B:
8079 mmu_model = "PowerPC 32";
8080 break;
8081 case POWERPC_MMU_SOFT_6xx:
8082 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8083 break;
8084 case POWERPC_MMU_SOFT_74xx:
8085 mmu_model = "PowerPC 74xx with software driven TLBs";
8086 break;
8087 case POWERPC_MMU_SOFT_4xx:
8088 mmu_model = "PowerPC 4xx with software driven TLBs";
8089 break;
8090 case POWERPC_MMU_SOFT_4xx_Z:
8091 mmu_model = "PowerPC 4xx with software driven TLBs "
8092 "and zones protections";
8093 break;
8094 case POWERPC_MMU_REAL:
8095 mmu_model = "PowerPC real mode only";
8096 break;
8097 case POWERPC_MMU_MPC8xx:
8098 mmu_model = "PowerPC MPC8xx";
8099 break;
8100 case POWERPC_MMU_BOOKE:
8101 mmu_model = "PowerPC BookE";
8102 break;
8103 case POWERPC_MMU_BOOKE206:
8104 mmu_model = "PowerPC BookE 2.06";
8105 break;
8106 case POWERPC_MMU_601:
8107 mmu_model = "PowerPC 601";
8108 break;
8109 #if defined (TARGET_PPC64)
8110 case POWERPC_MMU_64B:
8111 mmu_model = "PowerPC 64";
8112 break;
8113 case POWERPC_MMU_620:
8114 mmu_model = "PowerPC 620";
8115 break;
8116 #endif
8117 default:
8118 mmu_model = "Unknown or invalid";
8119 break;
8120 }
8121 switch (env->excp_model) {
8122 case POWERPC_EXCP_STD:
8123 excp_model = "PowerPC";
8124 break;
8125 case POWERPC_EXCP_40x:
8126 excp_model = "PowerPC 40x";
8127 break;
8128 case POWERPC_EXCP_601:
8129 excp_model = "PowerPC 601";
8130 break;
8131 case POWERPC_EXCP_602:
8132 excp_model = "PowerPC 602";
8133 break;
8134 case POWERPC_EXCP_603:
8135 excp_model = "PowerPC 603";
8136 break;
8137 case POWERPC_EXCP_603E:
8138 excp_model = "PowerPC 603e";
8139 break;
8140 case POWERPC_EXCP_604:
8141 excp_model = "PowerPC 604";
8142 break;
8143 case POWERPC_EXCP_7x0:
8144 excp_model = "PowerPC 740/750";
8145 break;
8146 case POWERPC_EXCP_7x5:
8147 excp_model = "PowerPC 745/755";
8148 break;
8149 case POWERPC_EXCP_74xx:
8150 excp_model = "PowerPC 74xx";
8151 break;
8152 case POWERPC_EXCP_BOOKE:
8153 excp_model = "PowerPC BookE";
8154 break;
8155 #if defined (TARGET_PPC64)
8156 case POWERPC_EXCP_970:
8157 excp_model = "PowerPC 970";
8158 break;
8159 #endif
8160 default:
8161 excp_model = "Unknown or invalid";
8162 break;
8163 }
8164 switch (env->bus_model) {
8165 case PPC_FLAGS_INPUT_6xx:
8166 bus_model = "PowerPC 6xx";
8167 break;
8168 case PPC_FLAGS_INPUT_BookE:
8169 bus_model = "PowerPC BookE";
8170 break;
8171 case PPC_FLAGS_INPUT_405:
8172 bus_model = "PowerPC 405";
8173 break;
8174 case PPC_FLAGS_INPUT_401:
8175 bus_model = "PowerPC 401/403";
8176 break;
8177 case PPC_FLAGS_INPUT_RCPU:
8178 bus_model = "RCPU / MPC8xx";
8179 break;
8180 #if defined (TARGET_PPC64)
8181 case PPC_FLAGS_INPUT_970:
8182 bus_model = "PowerPC 970";
8183 break;
8184 #endif
8185 default:
8186 bus_model = "Unknown or invalid";
8187 break;
8188 }
8189 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8190 " MMU model : %s\n",
8191 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
8192 #if !defined(CONFIG_USER_ONLY)
8193 if (env->tlb != NULL) {
8194 printf(" %d %s TLB in %d ways\n",
8195 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8196 env->nb_ways);
8197 }
8198 #endif
8199 printf(" Exceptions model : %s\n"
8200 " Bus model : %s\n",
8201 excp_model, bus_model);
8202 printf(" MSR features :\n");
8203 if (env->flags & POWERPC_FLAG_SPE)
8204 printf(" signal processing engine enable"
8205 "\n");
8206 else if (env->flags & POWERPC_FLAG_VRE)
8207 printf(" vector processor enable\n");
8208 if (env->flags & POWERPC_FLAG_TGPR)
8209 printf(" temporary GPRs\n");
8210 else if (env->flags & POWERPC_FLAG_CE)
8211 printf(" critical input enable\n");
8212 if (env->flags & POWERPC_FLAG_SE)
8213 printf(" single-step trace mode\n");
8214 else if (env->flags & POWERPC_FLAG_DWE)
8215 printf(" debug wait enable\n");
8216 else if (env->flags & POWERPC_FLAG_UBLE)
8217 printf(" user BTB lock enable\n");
8218 if (env->flags & POWERPC_FLAG_BE)
8219 printf(" branch-step trace mode\n");
8220 else if (env->flags & POWERPC_FLAG_DE)
8221 printf(" debug interrupt enable\n");
8222 if (env->flags & POWERPC_FLAG_PX)
8223 printf(" inclusive protection\n");
8224 else if (env->flags & POWERPC_FLAG_PMM)
8225 printf(" performance monitor mark\n");
8226 if (env->flags == POWERPC_FLAG_NONE)
8227 printf(" none\n");
8228 printf(" Time-base/decrementer clock source: %s\n",
8229 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8230 }
8231 dump_ppc_insns(env);
8232 dump_ppc_sprs(env);
8233 fflush(stdout);
8234 #endif
8235 }
8236
8237 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8238 {
8239 ObjectClass *oc = (ObjectClass *)a;
8240 uint32_t pvr = *(uint32_t *)b;
8241 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8242
8243 /* -cpu host does a PVR lookup during construction */
8244 if (unlikely(strcmp(object_class_get_name(oc),
8245 TYPE_HOST_POWERPC_CPU) == 0)) {
8246 return -1;
8247 }
8248
8249 #if defined(TARGET_PPCEMB)
8250 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8251 return -1;
8252 }
8253 #endif
8254
8255 return pcc->pvr == pvr ? 0 : -1;
8256 }
8257
8258 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8259 {
8260 GSList *list, *item;
8261 PowerPCCPUClass *pcc = NULL;
8262
8263 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8264 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8265 if (item != NULL) {
8266 pcc = POWERPC_CPU_CLASS(item->data);
8267 }
8268 g_slist_free(list);
8269
8270 return pcc;
8271 }
8272
8273 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
8274 {
8275 ObjectClass *oc = (ObjectClass *)a;
8276 const char *name = b;
8277 #if defined(TARGET_PPCEMB)
8278 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8279 #endif
8280
8281 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
8282 #if defined(TARGET_PPCEMB)
8283 pcc->mmu_model == POWERPC_MMU_BOOKE &&
8284 #endif
8285 strcmp(object_class_get_name(oc) + strlen(name),
8286 "-" TYPE_POWERPC_CPU) == 0) {
8287 return 0;
8288 }
8289 return -1;
8290 }
8291
8292 #include <ctype.h>
8293
8294 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8295 {
8296 GSList *list, *item;
8297 ObjectClass *ret = NULL;
8298 const char *p;
8299 int i, len;
8300
8301 /* Check if the given name is a PVR */
8302 len = strlen(name);
8303 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8304 p = name + 2;
8305 goto check_pvr;
8306 } else if (len == 8) {
8307 p = name;
8308 check_pvr:
8309 for (i = 0; i < 8; i++) {
8310 if (!qemu_isxdigit(*p++))
8311 break;
8312 }
8313 if (i == 8) {
8314 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
8315 return ret;
8316 }
8317 }
8318
8319 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
8320 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
8321 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
8322 }
8323 }
8324
8325 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8326 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8327 if (item != NULL) {
8328 ret = OBJECT_CLASS(item->data);
8329 }
8330 g_slist_free(list);
8331
8332 return ret;
8333 }
8334
8335 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
8336 {
8337 PowerPCCPU *cpu;
8338 CPUPPCState *env;
8339 ObjectClass *oc;
8340 Error *err = NULL;
8341
8342 oc = ppc_cpu_class_by_name(cpu_model);
8343 if (oc == NULL) {
8344 return NULL;
8345 }
8346
8347 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
8348 env = &cpu->env;
8349 env->cpu_model_str = cpu_model;
8350
8351 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
8352 if (err != NULL) {
8353 fprintf(stderr, "%s\n", error_get_pretty(err));
8354 error_free(err);
8355 object_unref(OBJECT(cpu));
8356 return NULL;
8357 }
8358
8359 return cpu;
8360 }
8361
8362 /* Sort by PVR, ordering special case "host" last. */
8363 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8364 {
8365 ObjectClass *oc_a = (ObjectClass *)a;
8366 ObjectClass *oc_b = (ObjectClass *)b;
8367 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8368 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8369 const char *name_a = object_class_get_name(oc_a);
8370 const char *name_b = object_class_get_name(oc_b);
8371
8372 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8373 return 1;
8374 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8375 return -1;
8376 } else {
8377 /* Avoid an integer overflow during subtraction */
8378 if (pcc_a->pvr < pcc_b->pvr) {
8379 return -1;
8380 } else if (pcc_a->pvr > pcc_b->pvr) {
8381 return 1;
8382 } else {
8383 return 0;
8384 }
8385 }
8386 }
8387
8388 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8389 {
8390 ObjectClass *oc = data;
8391 CPUListState *s = user_data;
8392 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8393 const char *typename = object_class_get_name(oc);
8394 char *name;
8395
8396 #if defined(TARGET_PPCEMB)
8397 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8398 return;
8399 }
8400 #endif
8401 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8402 return;
8403 }
8404
8405 name = g_strndup(typename,
8406 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8407 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
8408 name, pcc->pvr);
8409 g_free(name);
8410 }
8411
8412 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8413 {
8414 CPUListState s = {
8415 .file = f,
8416 .cpu_fprintf = cpu_fprintf,
8417 };
8418 GSList *list;
8419 int i;
8420
8421 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8422 list = g_slist_sort(list, ppc_cpu_list_compare);
8423 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8424 g_slist_free(list);
8425
8426 #ifdef CONFIG_KVM
8427 cpu_fprintf(f, "\n");
8428 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8429 #endif
8430
8431 cpu_fprintf(f, "\n");
8432 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
8433 ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
8434 if (oc == NULL) {
8435 /* Hide aliases that point to a TODO or TODO_USER_ONLY model */
8436 continue;
8437 }
8438 cpu_fprintf(f, "PowerPC %-16s\n",
8439 ppc_cpu_aliases[i].alias);
8440 }
8441 }
8442
8443 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8444 {
8445 ObjectClass *oc = data;
8446 CpuDefinitionInfoList **first = user_data;
8447 const char *typename;
8448 CpuDefinitionInfoList *entry;
8449 CpuDefinitionInfo *info;
8450 #if defined(TARGET_PPCEMB)
8451 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8452
8453 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
8454 return;
8455 }
8456 #endif
8457
8458 typename = object_class_get_name(oc);
8459 info = g_malloc0(sizeof(*info));
8460 info->name = g_strndup(typename,
8461 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8462
8463 entry = g_malloc0(sizeof(*entry));
8464 entry->value = info;
8465 entry->next = *first;
8466 *first = entry;
8467 }
8468
8469 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
8470 {
8471 CpuDefinitionInfoList *cpu_list = NULL;
8472 GSList *list;
8473
8474 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8475 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8476 g_slist_free(list);
8477
8478 return cpu_list;
8479 }
8480
8481 /* CPUClass::reset() */
8482 static void ppc_cpu_reset(CPUState *s)
8483 {
8484 PowerPCCPU *cpu = POWERPC_CPU(s);
8485 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8486 CPUPPCState *env = &cpu->env;
8487 target_ulong msr;
8488
8489 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
8490 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
8491 log_cpu_state(env, 0);
8492 }
8493
8494 pcc->parent_reset(s);
8495
8496 msr = (target_ulong)0;
8497 if (0) {
8498 /* XXX: find a suitable condition to enable the hypervisor mode */
8499 msr |= (target_ulong)MSR_HVB;
8500 }
8501 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8502 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8503 msr |= (target_ulong)1 << MSR_EP;
8504 #if defined(DO_SINGLE_STEP) && 0
8505 /* Single step trace mode */
8506 msr |= (target_ulong)1 << MSR_SE;
8507 msr |= (target_ulong)1 << MSR_BE;
8508 #endif
8509 #if defined(CONFIG_USER_ONLY)
8510 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8511 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8512 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8513 msr |= (target_ulong)1 << MSR_PR;
8514 #else
8515 env->excp_prefix = env->hreset_excp_prefix;
8516 env->nip = env->hreset_vector | env->excp_prefix;
8517 if (env->mmu_model != POWERPC_MMU_REAL) {
8518 ppc_tlb_invalidate_all(env);
8519 }
8520 #endif
8521 env->msr = msr & env->msr_mask;
8522 #if defined(TARGET_PPC64)
8523 if (env->mmu_model & POWERPC_MMU_64) {
8524 env->msr |= (1ULL << MSR_SF);
8525 }
8526 #endif
8527 hreg_compute_hflags(env);
8528 env->reserve_addr = (target_ulong)-1ULL;
8529 /* Be sure no exception or interrupt is pending */
8530 env->pending_interrupts = 0;
8531 env->exception_index = POWERPC_EXCP_NONE;
8532 env->error_code = 0;
8533
8534 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
8535 env->vpa_addr = 0;
8536 env->slb_shadow_addr = 0;
8537 env->slb_shadow_size = 0;
8538 env->dtl_addr = 0;
8539 env->dtl_size = 0;
8540 #endif /* TARGET_PPC64 */
8541
8542 /* Flush all TLBs */
8543 tlb_flush(env, 1);
8544 }
8545
8546 static void ppc_cpu_initfn(Object *obj)
8547 {
8548 CPUState *cs = CPU(obj);
8549 PowerPCCPU *cpu = POWERPC_CPU(obj);
8550 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8551 CPUPPCState *env = &cpu->env;
8552
8553 cs->env_ptr = env;
8554 cpu_exec_init(env);
8555
8556 env->msr_mask = pcc->msr_mask;
8557 env->mmu_model = pcc->mmu_model;
8558 env->excp_model = pcc->excp_model;
8559 env->bus_model = pcc->bus_model;
8560 env->insns_flags = pcc->insns_flags;
8561 env->insns_flags2 = pcc->insns_flags2;
8562 env->flags = pcc->flags;
8563 env->bfd_mach = pcc->bfd_mach;
8564 env->check_pow = pcc->check_pow;
8565
8566 #if defined(TARGET_PPC64)
8567 if (pcc->sps) {
8568 env->sps = *pcc->sps;
8569 } else if (env->mmu_model & POWERPC_MMU_64) {
8570 /* Use default sets of page sizes */
8571 static const struct ppc_segment_page_sizes defsps = {
8572 .sps = {
8573 { .page_shift = 12, /* 4K */
8574 .slb_enc = 0,
8575 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8576 },
8577 { .page_shift = 24, /* 16M */
8578 .slb_enc = 0x100,
8579 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8580 },
8581 },
8582 };
8583 env->sps = defsps;
8584 }
8585 #endif /* defined(TARGET_PPC64) */
8586
8587 if (tcg_enabled()) {
8588 ppc_translate_init();
8589 }
8590 }
8591
8592 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8593 {
8594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8595 CPUClass *cc = CPU_CLASS(oc);
8596 DeviceClass *dc = DEVICE_CLASS(oc);
8597
8598 pcc->parent_realize = dc->realize;
8599 dc->realize = ppc_cpu_realizefn;
8600
8601 pcc->parent_reset = cc->reset;
8602 cc->reset = ppc_cpu_reset;
8603
8604 cc->class_by_name = ppc_cpu_class_by_name;
8605 }
8606
8607 static const TypeInfo ppc_cpu_type_info = {
8608 .name = TYPE_POWERPC_CPU,
8609 .parent = TYPE_CPU,
8610 .instance_size = sizeof(PowerPCCPU),
8611 .instance_init = ppc_cpu_initfn,
8612 .abstract = true,
8613 .class_size = sizeof(PowerPCCPUClass),
8614 .class_init = ppc_cpu_class_init,
8615 };
8616
8617 static void ppc_cpu_register_types(void)
8618 {
8619 type_register_static(&ppc_cpu_type_info);
8620 }
8621
8622 type_init(ppc_cpu_register_types)
Qemu with PowerPC KVM improvements