hw/pcie.h

   1 /*
   2  * pcie.h
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef QEMU_PCIE_H
  22 #define QEMU_PCIE_H
  23
  24 #include "hw.h"
  25 #include "pci_regs.h"
  26 #include "pcie_regs.h"
  27
  28 typedef enum {
  29     /* for attention and power indicator */
  30     PCI_EXP_HP_IND_RESERVED     = PCI_EXP_SLTCTL_IND_RESERVED,
  31     PCI_EXP_HP_IND_ON           = PCI_EXP_SLTCTL_IND_ON,
  32     PCI_EXP_HP_IND_BLINK        = PCI_EXP_SLTCTL_IND_BLINK,
  33     PCI_EXP_HP_IND_OFF          = PCI_EXP_SLTCTL_IND_OFF,
  34 } PCIExpressIndicator;
  35
  36 typedef enum {
  37     /* these bits must match the bits in Slot Control/Status registers.
  38      * PCI_EXP_HP_EV_xxx = PCI_EXP_SLTCTL_xxxE = PCI_EXP_SLTSTA_xxx
  39      *
  40      * Not all the bits of slot control register match with the ones of
  41      * slot status. Not some bits of slot status register is used to
  42      * show status, not to report event occurence.
  43      * So such bits must be masked out when checking the software
  44      * notification condition.
  45      */
  46     PCI_EXP_HP_EV_ABP           = PCI_EXP_SLTCTL_ABPE,
  47                                         /* attention button pressed */
  48     PCI_EXP_HP_EV_PDC           = PCI_EXP_SLTCTL_PDCE,
  49                                         /* presence detect changed */
  50     PCI_EXP_HP_EV_CCI           = PCI_EXP_SLTCTL_CCIE,
  51                                         /* command completed */
  52
  53     PCI_EXP_HP_EV_SUPPORTED     = PCI_EXP_HP_EV_ABP |
  54                                   PCI_EXP_HP_EV_PDC |
  55                                   PCI_EXP_HP_EV_CCI,
  56                                                 /* supported event mask  */
  57
  58     /* events not listed aren't supported */
  59 } PCIExpressHotPlugEvent;
  60
  61 struct PCIExpressDevice {
  62     /* Offset of express capability in config space */
  63     uint8_t exp_cap;
  64
  65     /* TODO FLR */
  66
  67     /* SLOT */
  68     unsigned int hpev_intx;     /* INTx for hot plug event (0-3:INT[A-D]#)
  69                                  * default is 0 = INTA#
  70                                  * If the chip wants to use other interrupt
  71                                  * line, initialize this member with the
  72                                  * desired number.
  73                                  * If the chip dynamically changes this member,
  74                                  * also initialize it when loaded as
  75                                  * appropreately.
  76                                  */
  77     bool hpev_notified; /* Logical AND of conditions for hot plug event.
  78                          Following 6.7.3.4:
  79                          Software Notification of Hot-Plug Events, an interrupt
  80                          is sent whenever the logical and of these conditions
  81                          transitions from false to true. */
  82 };
  83
  84 /* PCI express capability helper functions */
  85 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port);
  86 void pcie_cap_exit(PCIDevice *dev);
  87 uint8_t pcie_cap_get_type(const PCIDevice *dev);
  88 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
  89 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
  90
  91 void pcie_cap_deverr_init(PCIDevice *dev);
  92 void pcie_cap_deverr_reset(PCIDevice *dev);
  93
  94 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
  95 void pcie_cap_slot_reset(PCIDevice *dev);
  96 void pcie_cap_slot_write_config(PCIDevice *dev,
  97                                 uint32_t addr, uint32_t val, int len);
  98 int pcie_cap_slot_post_load(void *opaque, int version_id);
  99 void pcie_cap_slot_push_attention_button(PCIDevice *dev);
 100
 101 void pcie_cap_root_init(PCIDevice *dev);
 102 void pcie_cap_root_reset(PCIDevice *dev);
 103
 104 void pcie_cap_flr_init(PCIDevice *dev);
 105 void pcie_cap_flr_write_config(PCIDevice *dev,
 106                            uint32_t addr, uint32_t val, int len);
 107
 108 void pcie_cap_ari_init(PCIDevice *dev);
 109 void pcie_cap_ari_reset(PCIDevice *dev);
 110 bool pcie_cap_is_ari_enabled(const PCIDevice *dev);
 111
 112 /* PCI express extended capability helper functions */
 113 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);
 114 void pcie_add_capability(PCIDevice *dev,
 115                          uint16_t cap_id, uint8_t cap_ver,
 116                          uint16_t offset, uint16_t size);
 117
 118 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
 119
 120 #endif /* QEMU_PCIE_H */