target-xtensa/op_helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "helper.h"
  30 #include "qemu/host-utils.h"
  31
  32 static void do_unaligned_access(CPUXtensaState *env,
  33         target_ulong addr, int is_write, int is_user, uintptr_t retaddr);
  34
  35 #define ALIGNED_ONLY
  36 #define MMUSUFFIX _mmu
  37
  38 #define SHIFT 0
  39 #include "exec/softmmu_template.h"
  40
  41 #define SHIFT 1
  42 #include "exec/softmmu_template.h"
  43
  44 #define SHIFT 2
  45 #include "exec/softmmu_template.h"
  46
  47 #define SHIFT 3
  48 #include "exec/softmmu_template.h"
  49
  50 static void do_unaligned_access(CPUXtensaState *env,
  51         target_ulong addr, int is_write, int is_user, uintptr_t retaddr)
  52 {
  53     if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
  54             !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
  55         cpu_restore_state(env, retaddr);
  56         HELPER(exception_cause_vaddr)(env,
  57                 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
  58     }
  59 }
  60
  61 void tlb_fill(CPUXtensaState *env,
  62         target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
  63 {
  64     uint32_t paddr;
  65     uint32_t page_size;
  66     unsigned access;
  67     int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
  68             &paddr, &page_size, &access);
  69
  70     qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
  71             vaddr, is_write, mmu_idx, paddr, ret);
  72
  73     if (ret == 0) {
  74         tlb_set_page(env,
  75                 vaddr & TARGET_PAGE_MASK,
  76                 paddr & TARGET_PAGE_MASK,
  77                 access, mmu_idx, page_size);
  78     } else {
  79         cpu_restore_state(env, retaddr);
  80         HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
  81     }
  82 }
  83
  84 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
  85 {
  86     uint32_t paddr;
  87     uint32_t page_size;
  88     unsigned access;
  89     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
  90             &paddr, &page_size, &access);
  91     if (ret == 0) {
  92         tb_invalidate_phys_addr(paddr);
  93     }
  94 }
  95
  96 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
  97 {
  98     env->exception_index = excp;
  99     cpu_loop_exit(env);
 100 }
 101
 102 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 103 {
 104     uint32_t vector;
 105
 106     env->pc = pc;
 107     if (env->sregs[PS] & PS_EXCM) {
 108         if (env->config->ndepc) {
 109             env->sregs[DEPC] = pc;
 110         } else {
 111             env->sregs[EPC1] = pc;
 112         }
 113         vector = EXC_DOUBLE;
 114     } else {
 115         env->sregs[EPC1] = pc;
 116         vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 117     }
 118
 119     env->sregs[EXCCAUSE] = cause;
 120     env->sregs[PS] |= PS_EXCM;
 121
 122     HELPER(exception)(env, vector);
 123 }
 124
 125 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
 126         uint32_t pc, uint32_t cause, uint32_t vaddr)
 127 {
 128     env->sregs[EXCVADDR] = vaddr;
 129     HELPER(exception_cause)(env, pc, cause);
 130 }
 131
 132 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
 133 {
 134     if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 135         HELPER(debug_exception)(env, env->pc, cause);
 136     }
 137 }
 138
 139 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
 140 {
 141     unsigned level = env->config->debug_level;
 142
 143     env->pc = pc;
 144     env->sregs[DEBUGCAUSE] = cause;
 145     env->sregs[EPC1 + level - 1] = pc;
 146     env->sregs[EPS2 + level - 2] = env->sregs[PS];
 147     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
 148         (level << PS_INTLEVEL_SHIFT);
 149     HELPER(exception)(env, EXC_DEBUG);
 150 }
 151
 152 uint32_t HELPER(nsa)(uint32_t v)
 153 {
 154     if (v & 0x80000000) {
 155         v = ~v;
 156     }
 157     return v ? clz32(v) - 1 : 31;
 158 }
 159
 160 uint32_t HELPER(nsau)(uint32_t v)
 161 {
 162     return v ? clz32(v) : 32;
 163 }
 164
 165 static void copy_window_from_phys(CPUXtensaState *env,
 166         uint32_t window, uint32_t phys, uint32_t n)
 167 {
 168     assert(phys < env->config->nareg);
 169     if (phys + n <= env->config->nareg) {
 170         memcpy(env->regs + window, env->phys_regs + phys,
 171                 n * sizeof(uint32_t));
 172     } else {
 173         uint32_t n1 = env->config->nareg - phys;
 174         memcpy(env->regs + window, env->phys_regs + phys,
 175                 n1 * sizeof(uint32_t));
 176         memcpy(env->regs + window + n1, env->phys_regs,
 177                 (n - n1) * sizeof(uint32_t));
 178     }
 179 }
 180
 181 static void copy_phys_from_window(CPUXtensaState *env,
 182         uint32_t phys, uint32_t window, uint32_t n)
 183 {
 184     assert(phys < env->config->nareg);
 185     if (phys + n <= env->config->nareg) {
 186         memcpy(env->phys_regs + phys, env->regs + window,
 187                 n * sizeof(uint32_t));
 188     } else {
 189         uint32_t n1 = env->config->nareg - phys;
 190         memcpy(env->phys_regs + phys, env->regs + window,
 191                 n1 * sizeof(uint32_t));
 192         memcpy(env->phys_regs, env->regs + window + n1,
 193                 (n - n1) * sizeof(uint32_t));
 194     }
 195 }
 196
 197
 198 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
 199 {
 200     return a & (env->config->nareg / 4 - 1);
 201 }
 202
 203 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
 204 {
 205     return 1 << windowbase_bound(a, env);
 206 }
 207
 208 void xtensa_sync_window_from_phys(CPUXtensaState *env)
 209 {
 210     copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
 211 }
 212
 213 void xtensa_sync_phys_from_window(CPUXtensaState *env)
 214 {
 215     copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
 216 }
 217
 218 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
 219 {
 220     xtensa_sync_phys_from_window(env);
 221     env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
 222     xtensa_sync_window_from_phys(env);
 223 }
 224
 225 static void rotate_window(CPUXtensaState *env, uint32_t delta)
 226 {
 227     rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
 228 }
 229
 230 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 231 {
 232     rotate_window_abs(env, v);
 233 }
 234
 235 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 236 {
 237     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
 238     if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 239         qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
 240                 pc, env->sregs[PS]);
 241         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 242     } else {
 243         env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
 244         rotate_window(env, callinc);
 245         env->sregs[WINDOW_START] |=
 246             windowstart_bit(env->sregs[WINDOW_BASE], env);
 247     }
 248 }
 249
 250 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
 251 {
 252     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 253     uint32_t windowstart = env->sregs[WINDOW_START];
 254     uint32_t m, n;
 255
 256     if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
 257         return;
 258     }
 259
 260     for (n = 1; ; ++n) {
 261         if (n > w) {
 262             return;
 263         }
 264         if (windowstart & windowstart_bit(windowbase + n, env)) {
 265             break;
 266         }
 267     }
 268
 269     m = windowbase_bound(windowbase + n, env);
 270     rotate_window(env, n);
 271     env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 272         (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 273     env->sregs[EPC1] = env->pc = pc;
 274
 275     if (windowstart & windowstart_bit(m + 1, env)) {
 276         HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
 277     } else if (windowstart & windowstart_bit(m + 2, env)) {
 278         HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
 279     } else {
 280         HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
 281     }
 282 }
 283
 284 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
 285 {
 286     int n = (env->regs[0] >> 30) & 0x3;
 287     int m = 0;
 288     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 289     uint32_t windowstart = env->sregs[WINDOW_START];
 290     uint32_t ret_pc = 0;
 291
 292     if (windowstart & windowstart_bit(windowbase - 1, env)) {
 293         m = 1;
 294     } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
 295         m = 2;
 296     } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
 297         m = 3;
 298     }
 299
 300     if (n == 0 || (m != 0 && m != n) ||
 301             ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
 302         qemu_log("Illegal retw instruction(pc = %08x), "
 303                 "PS = %08x, m = %d, n = %d\n",
 304                 pc, env->sregs[PS], m, n);
 305         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
 306     } else {
 307         int owb = windowbase;
 308
 309         ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
 310
 311         rotate_window(env, -n);
 312         if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
 313             env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
 314         } else {
 315             /* window underflow */
 316             env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
 317                 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
 318             env->sregs[EPC1] = env->pc = pc;
 319
 320             if (n == 1) {
 321                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
 322             } else if (n == 2) {
 323                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
 324             } else if (n == 3) {
 325                 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
 326             }
 327         }
 328     }
 329     return ret_pc;
 330 }
 331
 332 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
 333 {
 334     rotate_window(env, imm4);
 335 }
 336
 337 void HELPER(restore_owb)(CPUXtensaState *env)
 338 {
 339     rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
 340 }
 341
 342 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
 343 {
 344     if ((env->sregs[WINDOW_START] &
 345             (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
 346              windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
 347              windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
 348         HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
 349     }
 350 }
 351
 352 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
 353 {
 354     if (env->sregs[LBEG] != v) {
 355         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 356         env->sregs[LBEG] = v;
 357     }
 358 }
 359
 360 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
 361 {
 362     if (env->sregs[LEND] != v) {
 363         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 364         env->sregs[LEND] = v;
 365         tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
 366     }
 367 }
 368
 369 void HELPER(dump_state)(CPUXtensaState *env)
 370 {
 371     cpu_dump_state(env, stderr, fprintf, 0);
 372 }
 373
 374 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
 375 {
 376     CPUState *cpu;
 377
 378     env->pc = pc;
 379     env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
 380         (intlevel << PS_INTLEVEL_SHIFT);
 381     check_interrupts(env);
 382     if (env->pending_irq_level) {
 383         cpu_loop_exit(env);
 384         return;
 385     }
 386
 387     cpu = CPU(xtensa_env_get_cpu(env));
 388     env->halt_clock = qemu_get_clock_ns(vm_clock);
 389     cpu->halted = 1;
 390     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 391         xtensa_rearm_ccompare_timer(env);
 392     }
 393     HELPER(exception)(env, EXCP_HLT);
 394 }
 395
 396 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
 397 {
 398     xtensa_timer_irq(env, id, active);
 399 }
 400
 401 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
 402 {
 403     xtensa_advance_ccount(env, d);
 404 }
 405
 406 void HELPER(check_interrupts)(CPUXtensaState *env)
 407 {
 408     check_interrupts(env);
 409 }
 410
 411 /*!
 412  * Check vaddr accessibility/cache attributes and raise an exception if
 413  * specified by the ATOMCTL SR.
 414  *
 415  * Note: local memory exclusion is not implemented
 416  */
 417 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
 418 {
 419     uint32_t paddr, page_size, access;
 420     uint32_t atomctl = env->sregs[ATOMCTL];
 421     int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
 422             xtensa_get_cring(env), &paddr, &page_size, &access);
 423
 424     /*
 425      * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
 426      * see opcode description in the ISA
 427      */
 428     if (rc == 0 &&
 429             (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
 430         rc = STORE_PROHIBITED_CAUSE;
 431     }
 432
 433     if (rc) {
 434         HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
 435     }
 436
 437     /*
 438      * When data cache is not configured use ATOMCTL bypass field.
 439      * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
 440      * under the Conditional Store Option.
 441      */
 442     if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
 443         access = PAGE_CACHE_BYPASS;
 444     }
 445
 446     switch (access & PAGE_CACHE_MASK) {
 447     case PAGE_CACHE_WB:
 448         atomctl >>= 2;
 449     case PAGE_CACHE_WT:
 450         atomctl >>= 2;
 451     case PAGE_CACHE_BYPASS:
 452         if ((atomctl & 0x3) == 0) {
 453             HELPER(exception_cause_vaddr)(env, pc,
 454                     LOAD_STORE_ERROR_CAUSE, vaddr);
 455         }
 456         break;
 457
 458     case PAGE_CACHE_ISOLATE:
 459         HELPER(exception_cause_vaddr)(env, pc,
 460                 LOAD_STORE_ERROR_CAUSE, vaddr);
 461         break;
 462
 463     default:
 464         break;
 465     }
 466 }
 467
 468 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
 469 {
 470     v = (v & 0xffffff00) | 0x1;
 471     if (v != env->sregs[RASID]) {
 472         env->sregs[RASID] = v;
 473         tlb_flush(env, 1);
 474     }
 475 }
 476
 477 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
 478 {
 479     uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
 480
 481     switch (way) {
 482     case 4:
 483         return (tlbcfg >> 16) & 0x3;
 484
 485     case 5:
 486         return (tlbcfg >> 20) & 0x1;
 487
 488     case 6:
 489         return (tlbcfg >> 24) & 0x1;
 490
 491     default:
 492         return 0;
 493     }
 494 }
 495
 496 /*!
 497  * Get bit mask for the virtual address bits translated by the TLB way
 498  */
 499 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 500 {
 501     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 502         bool varway56 = dtlb ?
 503             env->config->dtlb.varway56 :
 504             env->config->itlb.varway56;
 505
 506         switch (way) {
 507         case 4:
 508             return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
 509
 510         case 5:
 511             if (varway56) {
 512                 return 0xf8000000 << get_page_size(env, dtlb, way);
 513             } else {
 514                 return 0xf8000000;
 515             }
 516
 517         case 6:
 518             if (varway56) {
 519                 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
 520             } else {
 521                 return 0xf0000000;
 522             }
 523
 524         default:
 525             return 0xfffff000;
 526         }
 527     } else {
 528         return REGION_PAGE_MASK;
 529     }
 530 }
 531
 532 /*!
 533  * Get bit mask for the 'VPN without index' field.
 534  * See ISA, 4.6.5.6, data format for RxTLB0
 535  */
 536 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
 537 {
 538     if (way < 4) {
 539         bool is32 = (dtlb ?
 540                 env->config->dtlb.nrefillentries :
 541                 env->config->itlb.nrefillentries) == 32;
 542         return is32 ? 0xffff8000 : 0xffffc000;
 543     } else if (way == 4) {
 544         return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
 545     } else if (way <= 6) {
 546         uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
 547         bool varway56 = dtlb ?
 548             env->config->dtlb.varway56 :
 549             env->config->itlb.varway56;
 550
 551         if (varway56) {
 552             return mask << (way == 5 ? 2 : 3);
 553         } else {
 554             return mask << 1;
 555         }
 556     } else {
 557         return 0xfffff000;
 558     }
 559 }
 560
 561 /*!
 562  * Split virtual address into VPN (with index) and entry index
 563  * for the given TLB way
 564  */
 565 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 566         uint32_t *vpn, uint32_t wi, uint32_t *ei)
 567 {
 568     bool varway56 = dtlb ?
 569         env->config->dtlb.varway56 :
 570         env->config->itlb.varway56;
 571
 572     if (!dtlb) {
 573         wi &= 7;
 574     }
 575
 576     if (wi < 4) {
 577         bool is32 = (dtlb ?
 578                 env->config->dtlb.nrefillentries :
 579                 env->config->itlb.nrefillentries) == 32;
 580         *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
 581     } else {
 582         switch (wi) {
 583         case 4:
 584             {
 585                 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
 586                 *ei = (v >> eibase) & 0x3;
 587             }
 588             break;
 589
 590         case 5:
 591             if (varway56) {
 592                 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
 593                 *ei = (v >> eibase) & 0x3;
 594             } else {
 595                 *ei = (v >> 27) & 0x1;
 596             }
 597             break;
 598
 599         case 6:
 600             if (varway56) {
 601                 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
 602                 *ei = (v >> eibase) & 0x7;
 603             } else {
 604                 *ei = (v >> 28) & 0x1;
 605             }
 606             break;
 607
 608         default:
 609             *ei = 0;
 610             break;
 611         }
 612     }
 613     *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 614 }
 615
 616 /*!
 617  * Split TLB address into TLB way, entry index and VPN (with index).
 618  * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
 619  */
 620 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
 621         uint32_t *vpn, uint32_t *wi, uint32_t *ei)
 622 {
 623     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 624         *wi = v & (dtlb ? 0xf : 0x7);
 625         split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
 626     } else {
 627         *vpn = v & REGION_PAGE_MASK;
 628         *wi = 0;
 629         *ei = (v >> 29) & 0x7;
 630     }
 631 }
 632
 633 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
 634         uint32_t v, bool dtlb, uint32_t *pwi)
 635 {
 636     uint32_t vpn;
 637     uint32_t wi;
 638     uint32_t ei;
 639
 640     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 641     if (pwi) {
 642         *pwi = wi;
 643     }
 644     return xtensa_tlb_get_entry(env, dtlb, wi, ei);
 645 }
 646
 647 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 648 {
 649     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 650         uint32_t wi;
 651         const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 652         return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
 653     } else {
 654         return v & REGION_PAGE_MASK;
 655     }
 656 }
 657
 658 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 659 {
 660     const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
 661     return entry->paddr | entry->attr;
 662 }
 663
 664 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 665 {
 666     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 667         uint32_t wi;
 668         xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
 669         if (entry->variable && entry->asid) {
 670             tlb_flush_page(env, entry->vaddr);
 671             entry->asid = 0;
 672         }
 673     }
 674 }
 675
 676 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
 677 {
 678     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 679         uint32_t wi;
 680         uint32_t ei;
 681         uint8_t ring;
 682         int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
 683
 684         switch (res) {
 685         case 0:
 686             if (ring >= xtensa_get_ring(env)) {
 687                 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
 688             }
 689             break;
 690
 691         case INST_TLB_MULTI_HIT_CAUSE:
 692         case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
 693             HELPER(exception_cause_vaddr)(env, env->pc, res, v);
 694             break;
 695         }
 696         return 0;
 697     } else {
 698         return (v & REGION_PAGE_MASK) | 0x1;
 699     }
 700 }
 701
 702 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 703         xtensa_tlb_entry *entry, bool dtlb,
 704         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 705 {
 706     entry->vaddr = vpn;
 707     entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
 708     entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
 709     entry->attr = pte & 0xf;
 710 }
 711
 712 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 713         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
 714 {
 715     xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
 716
 717     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 718         if (entry->variable) {
 719             if (entry->asid) {
 720                 tlb_flush_page(env, entry->vaddr);
 721             }
 722             xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
 723             tlb_flush_page(env, entry->vaddr);
 724         } else {
 725             qemu_log("%s %d, %d, %d trying to set immutable entry\n",
 726                     __func__, dtlb, wi, ei);
 727         }
 728     } else {
 729         tlb_flush_page(env, entry->vaddr);
 730         if (xtensa_option_enabled(env->config,
 731                     XTENSA_OPTION_REGION_TRANSLATION)) {
 732             entry->paddr = pte & REGION_PAGE_MASK;
 733         }
 734         entry->attr = pte & 0xf;
 735     }
 736 }
 737
 738 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
 739 {
 740     uint32_t vpn;
 741     uint32_t wi;
 742     uint32_t ei;
 743     split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
 744     xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
 745 }
 746
 747
 748 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
 749 {
 750     uint32_t change = v ^ env->sregs[IBREAKENABLE];
 751     unsigned i;
 752
 753     for (i = 0; i < env->config->nibreak; ++i) {
 754         if (change & (1 << i)) {
 755             tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 756         }
 757     }
 758     env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
 759 }
 760
 761 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 762 {
 763     if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
 764         tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
 765         tb_invalidate_virtual_addr(env, v);
 766     }
 767     env->sregs[IBREAKA + i] = v;
 768 }
 769
 770 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
 771         uint32_t dbreakc)
 772 {
 773     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 774     uint32_t mask = dbreakc | ~DBREAKC_MASK;
 775
 776     if (env->cpu_watchpoint[i]) {
 777         cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 778     }
 779     if (dbreakc & DBREAKC_SB) {
 780         flags |= BP_MEM_WRITE;
 781     }
 782     if (dbreakc & DBREAKC_LB) {
 783         flags |= BP_MEM_READ;
 784     }
 785     /* contiguous mask after inversion is one less than some power of 2 */
 786     if ((~mask + 1) & ~mask) {
 787         qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
 788         /* cut mask after the first zero bit */
 789         mask = 0xffffffff << (32 - clo32(mask));
 790     }
 791     if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1,
 792             flags, &env->cpu_watchpoint[i])) {
 793         env->cpu_watchpoint[i] = NULL;
 794         qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
 795                 dbreaka & mask, ~mask + 1);
 796     }
 797 }
 798
 799 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
 800 {
 801     uint32_t dbreakc = env->sregs[DBREAKC + i];
 802
 803     if ((dbreakc & DBREAKC_SB_LB) &&
 804             env->sregs[DBREAKA + i] != v) {
 805         set_dbreak(env, i, v, dbreakc);
 806     }
 807     env->sregs[DBREAKA + i] = v;
 808 }
 809
 810 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
 811 {
 812     if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
 813         if (v & DBREAKC_SB_LB) {
 814             set_dbreak(env, i, env->sregs[DBREAKA + i], v);
 815         } else {
 816             if (env->cpu_watchpoint[i]) {
 817                 cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
 818                 env->cpu_watchpoint[i] = NULL;
 819             }
 820         }
 821     }
 822     env->sregs[DBREAKC + i] = v;
 823 }
 824
 825 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 826 {
 827     static const int rounding_mode[] = {
 828         float_round_nearest_even,
 829         float_round_to_zero,
 830         float_round_up,
 831         float_round_down,
 832     };
 833
 834     env->uregs[FCR] = v & 0xfffff07f;
 835     set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 836 }
 837
 838 float32 HELPER(abs_s)(float32 v)
 839 {
 840     return float32_abs(v);
 841 }
 842
 843 float32 HELPER(neg_s)(float32 v)
 844 {
 845     return float32_chs(v);
 846 }
 847
 848 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
 849 {
 850     return float32_add(a, b, &env->fp_status);
 851 }
 852
 853 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
 854 {
 855     return float32_sub(a, b, &env->fp_status);
 856 }
 857
 858 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
 859 {
 860     return float32_mul(a, b, &env->fp_status);
 861 }
 862
 863 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 864 {
 865     return float32_muladd(b, c, a, 0,
 866             &env->fp_status);
 867 }
 868
 869 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
 870 {
 871     return float32_muladd(b, c, a, float_muladd_negate_product,
 872             &env->fp_status);
 873 }
 874
 875 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
 876 {
 877     float_status fp_status = {0};
 878
 879     set_float_rounding_mode(rounding_mode, &fp_status);
 880     return float32_to_int32(
 881             float32_scalbn(v, scale, &fp_status), &fp_status);
 882 }
 883
 884 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
 885 {
 886     float_status fp_status = {0};
 887     float32 res;
 888
 889     set_float_rounding_mode(rounding_mode, &fp_status);
 890
 891     res = float32_scalbn(v, scale, &fp_status);
 892
 893     if (float32_is_neg(v) && !float32_is_any_nan(v)) {
 894         return float32_to_int32(res, &fp_status);
 895     } else {
 896         return float32_to_uint32(res, &fp_status);
 897     }
 898 }
 899
 900 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 901 {
 902     return float32_scalbn(int32_to_float32(v, &env->fp_status),
 903             (int32_t)scale, &env->fp_status);
 904 }
 905
 906 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
 907 {
 908     return float32_scalbn(uint32_to_float32(v, &env->fp_status),
 909             (int32_t)scale, &env->fp_status);
 910 }
 911
 912 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
 913 {
 914     if (v) {
 915         env->sregs[BR] |= br;
 916     } else {
 917         env->sregs[BR] &= ~br;
 918     }
 919 }
 920
 921 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 922 {
 923     set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
 924 }
 925
 926 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 927 {
 928     set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
 929 }
 930
 931 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 932 {
 933     int v = float32_compare_quiet(a, b, &env->fp_status);
 934     set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
 935 }
 936
 937 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 938 {
 939     set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
 940 }
 941
 942 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 943 {
 944     int v = float32_compare_quiet(a, b, &env->fp_status);
 945     set_br(env, v == float_relation_less || v == float_relation_unordered, br);
 946 }
 947
 948 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 949 {
 950     set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
 951 }
 952
 953 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
 954 {
 955     int v = float32_compare_quiet(a, b, &env->fp_status);
 956     set_br(env, v != float_relation_greater, br);
 957 }