hw/alpha_typhoon.c

   1 /*
   2  * DEC 21272 (TSUNAMI/TYPHOON) chipset emulation.
   3  *
   4  * Written by Richard Henderson.
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  */
   8
   9 #include "cpu.h"
  10 #include "exec/exec-all.h"
  11 #include "hw.h"
  12 #include "devices.h"
  13 #include "sysemu/sysemu.h"
  14 #include "alpha_sys.h"
  15 #include "exec/address-spaces.h"
  16
  17
  18 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
  19
  20 typedef struct TyphoonCchip {
  21     MemoryRegion region;
  22     uint64_t misc;
  23     uint64_t drir;
  24     uint64_t dim[4];
  25     uint32_t iic[4];
  26     AlphaCPU *cpu[4];
  27 } TyphoonCchip;
  28
  29 typedef struct TyphoonWindow {
  30     uint32_t base_addr;
  31     uint32_t mask;
  32     uint32_t translated_base_pfn;
  33 } TyphoonWindow;
  34
  35 typedef struct TyphoonPchip {
  36     MemoryRegion region;
  37     MemoryRegion reg_iack;
  38     MemoryRegion reg_mem;
  39     MemoryRegion reg_io;
  40     MemoryRegion reg_conf;
  41     uint64_t ctl;
  42     TyphoonWindow win[4];
  43 } TyphoonPchip;
  44
  45 #define TYPHOON_PCI_HOST_BRIDGE(obj) \
  46     OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE)
  47
  48 typedef struct TyphoonState {
  49     PCIHostState parent_obj;
  50
  51     TyphoonCchip cchip;
  52     TyphoonPchip pchip;
  53     MemoryRegion dchip_region;
  54     MemoryRegion ram_region;
  55
  56     /* QEMU emulation state.  */
  57     uint32_t latch_tmp;
  58 } TyphoonState;
  59
  60 /* Called when one of DRIR or DIM changes.  */
  61 static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
  62 {
  63     /* If there are any non-masked interrupts, tell the cpu.  */
  64     if (cpu != NULL) {
  65         CPUAlphaState *env = &cpu->env;
  66         if (req) {
  67             cpu_interrupt(env, CPU_INTERRUPT_HARD);
  68         } else {
  69             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  70         }
  71     }
  72 }
  73
  74 static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
  75 {
  76     CPUAlphaState *env = cpu_single_env;
  77     TyphoonState *s = opaque;
  78     uint64_t ret = 0;
  79
  80     if (addr & 4) {
  81         return s->latch_tmp;
  82     }
  83
  84     switch (addr) {
  85     case 0x0000:
  86         /* CSC: Cchip System Configuration Register.  */
  87         /* All sorts of data here; probably the only thing relevant is
  88            PIP<14> Pchip 1 Present = 0.  */
  89         break;
  90
  91     case 0x0040:
  92         /* MTR: Memory Timing Register.  */
  93         /* All sorts of stuff related to real DRAM.  */
  94         break;
  95
  96     case 0x0080:
  97         /* MISC: Miscellaneous Register.  */
  98         ret = s->cchip.misc | (env->cpu_index & 3);
  99         break;
 100
 101     case 0x00c0:
 102         /* MPD: Memory Presence Detect Register.  */
 103         break;
 104
 105     case 0x0100: /* AAR0 */
 106     case 0x0140: /* AAR1 */
 107     case 0x0180: /* AAR2 */
 108     case 0x01c0: /* AAR3 */
 109         /* AAR: Array Address Register.  */
 110         /* All sorts of information about DRAM.  */
 111         break;
 112
 113     case 0x0200:
 114         /* DIM0: Device Interrupt Mask Register, CPU0.  */
 115         ret = s->cchip.dim[0];
 116         break;
 117     case 0x0240:
 118         /* DIM1: Device Interrupt Mask Register, CPU1.  */
 119         ret = s->cchip.dim[1];
 120         break;
 121     case 0x0280:
 122         /* DIR0: Device Interrupt Request Register, CPU0.  */
 123         ret = s->cchip.dim[0] & s->cchip.drir;
 124         break;
 125     case 0x02c0:
 126         /* DIR1: Device Interrupt Request Register, CPU1.  */
 127         ret = s->cchip.dim[1] & s->cchip.drir;
 128         break;
 129     case 0x0300:
 130         /* DRIR: Device Raw Interrupt Request Register.  */
 131         ret = s->cchip.drir;
 132         break;
 133
 134     case 0x0340:
 135         /* PRBEN: Probe Enable Register.  */
 136         break;
 137
 138     case 0x0380:
 139         /* IIC0: Interval Ignore Count Register, CPU0.  */
 140         ret = s->cchip.iic[0];
 141         break;
 142     case 0x03c0:
 143         /* IIC1: Interval Ignore Count Register, CPU1.  */
 144         ret = s->cchip.iic[1];
 145         break;
 146
 147     case 0x0400: /* MPR0 */
 148     case 0x0440: /* MPR1 */
 149     case 0x0480: /* MPR2 */
 150     case 0x04c0: /* MPR3 */
 151         /* MPR: Memory Programming Register.  */
 152         break;
 153
 154     case 0x0580:
 155         /* TTR: TIGbus Timing Register.  */
 156         /* All sorts of stuff related to interrupt delivery timings.  */
 157         break;
 158     case 0x05c0:
 159         /* TDR: TIGbug Device Timing Register.  */
 160         break;
 161
 162     case 0x0600:
 163         /* DIM2: Device Interrupt Mask Register, CPU2.  */
 164         ret = s->cchip.dim[2];
 165         break;
 166     case 0x0640:
 167         /* DIM3: Device Interrupt Mask Register, CPU3.  */
 168         ret = s->cchip.dim[3];
 169         break;
 170     case 0x0680:
 171         /* DIR2: Device Interrupt Request Register, CPU2.  */
 172         ret = s->cchip.dim[2] & s->cchip.drir;
 173         break;
 174     case 0x06c0:
 175         /* DIR3: Device Interrupt Request Register, CPU3.  */
 176         ret = s->cchip.dim[3] & s->cchip.drir;
 177         break;
 178
 179     case 0x0700:
 180         /* IIC2: Interval Ignore Count Register, CPU2.  */
 181         ret = s->cchip.iic[2];
 182         break;
 183     case 0x0740:
 184         /* IIC3: Interval Ignore Count Register, CPU3.  */
 185         ret = s->cchip.iic[3];
 186         break;
 187
 188     case 0x0780:
 189         /* PWR: Power Management Control.   */
 190         break;
 191
 192     case 0x0c00: /* CMONCTLA */
 193     case 0x0c40: /* CMONCTLB */
 194     case 0x0c80: /* CMONCNT01 */
 195     case 0x0cc0: /* CMONCNT23 */
 196         break;
 197
 198     default:
 199         cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
 200         return -1;
 201     }
 202
 203     s->latch_tmp = ret >> 32;
 204     return ret;
 205 }
 206
 207 static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
 208 {
 209     /* Skip this.  It's all related to DRAM timing and setup.  */
 210     return 0;
 211 }
 212
 213 static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
 214 {
 215     TyphoonState *s = opaque;
 216     uint64_t ret = 0;
 217
 218     if (addr & 4) {
 219         return s->latch_tmp;
 220     }
 221
 222     switch (addr) {
 223     case 0x0000:
 224         /* WSBA0: Window Space Base Address Register.  */
 225         ret = s->pchip.win[0].base_addr;
 226         break;
 227     case 0x0040:
 228         /* WSBA1 */
 229         ret = s->pchip.win[1].base_addr;
 230         break;
 231     case 0x0080:
 232         /* WSBA2 */
 233         ret = s->pchip.win[2].base_addr;
 234         break;
 235     case 0x00c0:
 236         /* WSBA3 */
 237         ret = s->pchip.win[3].base_addr;
 238         break;
 239
 240     case 0x0100:
 241         /* WSM0: Window Space Mask Register.  */
 242         ret = s->pchip.win[0].mask;
 243         break;
 244     case 0x0140:
 245         /* WSM1 */
 246         ret = s->pchip.win[1].mask;
 247         break;
 248     case 0x0180:
 249         /* WSM2 */
 250         ret = s->pchip.win[2].mask;
 251         break;
 252     case 0x01c0:
 253         /* WSM3 */
 254         ret = s->pchip.win[3].mask;
 255         break;
 256
 257     case 0x0200:
 258         /* TBA0: Translated Base Address Register.  */
 259         ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10;
 260         break;
 261     case 0x0240:
 262         /* TBA1 */
 263         ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10;
 264         break;
 265     case 0x0280:
 266         /* TBA2 */
 267         ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10;
 268         break;
 269     case 0x02c0:
 270         /* TBA3 */
 271         ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10;
 272         break;
 273
 274     case 0x0300:
 275         /* PCTL: Pchip Control Register.  */
 276         ret = s->pchip.ctl;
 277         break;
 278     case 0x0340:
 279         /* PLAT: Pchip Master Latency Register.  */
 280         break;
 281     case 0x03c0:
 282         /* PERROR: Pchip Error Register.  */
 283         break;
 284     case 0x0400:
 285         /* PERRMASK: Pchip Error Mask Register.  */
 286         break;
 287     case 0x0440:
 288         /* PERRSET: Pchip Error Set Register.  */
 289         break;
 290     case 0x0480:
 291         /* TLBIV: Translation Buffer Invalidate Virtual Register (WO).  */
 292         break;
 293     case 0x04c0:
 294         /* TLBIA: Translation Buffer Invalidate All Register (WO).  */
 295         break;
 296     case 0x0500: /* PMONCTL */
 297     case 0x0540: /* PMONCNT */
 298     case 0x0800: /* SPRST */
 299         break;
 300
 301     default:
 302         cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
 303         return -1;
 304     }
 305
 306     s->latch_tmp = ret >> 32;
 307     return ret;
 308 }
 309
 310 static void cchip_write(void *opaque, hwaddr addr,
 311                         uint64_t v32, unsigned size)
 312 {
 313     TyphoonState *s = opaque;
 314     uint64_t val, oldval, newval;
 315
 316     if (addr & 4) {
 317         val = v32 << 32 | s->latch_tmp;
 318         addr ^= 4;
 319     } else {
 320         s->latch_tmp = v32;
 321         return;
 322     }
 323
 324     switch (addr) {
 325     case 0x0000:
 326         /* CSC: Cchip System Configuration Register.  */
 327         /* All sorts of data here; nothing relevant RW.  */
 328         break;
 329
 330     case 0x0040:
 331         /* MTR: Memory Timing Register.  */
 332         /* All sorts of stuff related to real DRAM.  */
 333         break;
 334
 335     case 0x0080:
 336         /* MISC: Miscellaneous Register.  */
 337         newval = oldval = s->cchip.misc;
 338         newval &= ~(val & 0x10000ff0);     /* W1C fields */
 339         if (val & 0x100000) {
 340             newval &= ~0xff0000ull;        /* ACL clears ABT and ABW */
 341         } else {
 342             newval |= val & 0x00f00000;    /* ABT field is W1S */
 343             if ((newval & 0xf0000) == 0) {
 344                 newval |= val & 0xf0000;   /* ABW field is W1S iff zero */
 345             }
 346         }
 347         newval |= (val & 0xf000) >> 4;     /* IPREQ field sets IPINTR.  */
 348
 349         newval &= ~0xf0000000000ull;       /* WO and RW fields */
 350         newval |= val & 0xf0000000000ull;
 351         s->cchip.misc = newval;
 352
 353         /* Pass on changes to IPI and ITI state.  */
 354         if ((newval ^ oldval) & 0xff0) {
 355             int i;
 356             for (i = 0; i < 4; ++i) {
 357                 AlphaCPU *cpu = s->cchip.cpu[i];
 358                 if (cpu != NULL) {
 359                     CPUAlphaState *env = &cpu->env;
 360                     /* IPI can be either cleared or set by the write.  */
 361                     if (newval & (1 << (i + 8))) {
 362                         cpu_interrupt(env, CPU_INTERRUPT_SMP);
 363                     } else {
 364                         cpu_reset_interrupt(env, CPU_INTERRUPT_SMP);
 365                     }
 366
 367                     /* ITI can only be cleared by the write.  */
 368                     if ((newval & (1 << (i + 4))) == 0) {
 369                         cpu_reset_interrupt(env, CPU_INTERRUPT_TIMER);
 370                     }
 371                 }
 372             }
 373         }
 374         break;
 375
 376     case 0x00c0:
 377         /* MPD: Memory Presence Detect Register.  */
 378         break;
 379
 380     case 0x0100: /* AAR0 */
 381     case 0x0140: /* AAR1 */
 382     case 0x0180: /* AAR2 */
 383     case 0x01c0: /* AAR3 */
 384         /* AAR: Array Address Register.  */
 385         /* All sorts of information about DRAM.  */
 386         break;
 387
 388     case 0x0200: /* DIM0 */
 389         /* DIM: Device Interrupt Mask Register, CPU0.  */
 390         s->cchip.dim[0] = val;
 391         cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir);
 392         break;
 393     case 0x0240: /* DIM1 */
 394         /* DIM: Device Interrupt Mask Register, CPU1.  */
 395         s->cchip.dim[0] = val;
 396         cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
 397         break;
 398
 399     case 0x0280: /* DIR0 (RO) */
 400     case 0x02c0: /* DIR1 (RO) */
 401     case 0x0300: /* DRIR (RO) */
 402         break;
 403
 404     case 0x0340:
 405         /* PRBEN: Probe Enable Register.  */
 406         break;
 407
 408     case 0x0380: /* IIC0 */
 409         s->cchip.iic[0] = val & 0xffffff;
 410         break;
 411     case 0x03c0: /* IIC1 */
 412         s->cchip.iic[1] = val & 0xffffff;
 413         break;
 414
 415     case 0x0400: /* MPR0 */
 416     case 0x0440: /* MPR1 */
 417     case 0x0480: /* MPR2 */
 418     case 0x04c0: /* MPR3 */
 419         /* MPR: Memory Programming Register.  */
 420         break;
 421
 422     case 0x0580:
 423         /* TTR: TIGbus Timing Register.  */
 424         /* All sorts of stuff related to interrupt delivery timings.  */
 425         break;
 426     case 0x05c0:
 427         /* TDR: TIGbug Device Timing Register.  */
 428         break;
 429
 430     case 0x0600:
 431         /* DIM2: Device Interrupt Mask Register, CPU2.  */
 432         s->cchip.dim[2] = val;
 433         cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir);
 434         break;
 435     case 0x0640:
 436         /* DIM3: Device Interrupt Mask Register, CPU3.  */
 437         s->cchip.dim[3] = val;
 438         cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir);
 439         break;
 440
 441     case 0x0680: /* DIR2 (RO) */
 442     case 0x06c0: /* DIR3 (RO) */
 443         break;
 444
 445     case 0x0700: /* IIC2 */
 446         s->cchip.iic[2] = val & 0xffffff;
 447         break;
 448     case 0x0740: /* IIC3 */
 449         s->cchip.iic[3] = val & 0xffffff;
 450         break;
 451
 452     case 0x0780:
 453         /* PWR: Power Management Control.   */
 454         break;
 455
 456     case 0x0c00: /* CMONCTLA */
 457     case 0x0c40: /* CMONCTLB */
 458     case 0x0c80: /* CMONCNT01 */
 459     case 0x0cc0: /* CMONCNT23 */
 460         break;
 461
 462     default:
 463         cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
 464         return;
 465     }
 466 }
 467
 468 static void dchip_write(void *opaque, hwaddr addr,
 469                         uint64_t val, unsigned size)
 470 {
 471     /* Skip this.  It's all related to DRAM timing and setup.  */
 472 }
 473
 474 static void pchip_write(void *opaque, hwaddr addr,
 475                         uint64_t v32, unsigned size)
 476 {
 477     TyphoonState *s = opaque;
 478     uint64_t val, oldval;
 479
 480     if (addr & 4) {
 481         val = v32 << 32 | s->latch_tmp;
 482         addr ^= 4;
 483     } else {
 484         s->latch_tmp = v32;
 485         return;
 486     }
 487
 488     switch (addr) {
 489     case 0x0000:
 490         /* WSBA0: Window Space Base Address Register.  */
 491         s->pchip.win[0].base_addr = val;
 492         break;
 493     case 0x0040:
 494         /* WSBA1 */
 495         s->pchip.win[1].base_addr = val;
 496         break;
 497     case 0x0080:
 498         /* WSBA2 */
 499         s->pchip.win[2].base_addr = val;
 500         break;
 501     case 0x00c0:
 502         /* WSBA3 */
 503         s->pchip.win[3].base_addr = val;
 504         break;
 505
 506     case 0x0100:
 507         /* WSM0: Window Space Mask Register.  */
 508         s->pchip.win[0].mask = val;
 509         break;
 510     case 0x0140:
 511         /* WSM1 */
 512         s->pchip.win[1].mask = val;
 513         break;
 514     case 0x0180:
 515         /* WSM2 */
 516         s->pchip.win[2].mask = val;
 517         break;
 518     case 0x01c0:
 519         /* WSM3 */
 520         s->pchip.win[3].mask = val;
 521         break;
 522
 523     case 0x0200:
 524         /* TBA0: Translated Base Address Register.  */
 525         s->pchip.win[0].translated_base_pfn = val >> 10;
 526         break;
 527     case 0x0240:
 528         /* TBA1 */
 529         s->pchip.win[1].translated_base_pfn = val >> 10;
 530         break;
 531     case 0x0280:
 532         /* TBA2 */
 533         s->pchip.win[2].translated_base_pfn = val >> 10;
 534         break;
 535     case 0x02c0:
 536         /* TBA3 */
 537         s->pchip.win[3].translated_base_pfn = val >> 10;
 538         break;
 539
 540     case 0x0300:
 541         /* PCTL: Pchip Control Register.  */
 542         oldval = s->pchip.ctl;
 543         oldval &= ~0x00001cff0fc7ffull;       /* RW fields */
 544         oldval |= val & 0x00001cff0fc7ffull;
 545
 546         s->pchip.ctl = oldval;
 547         break;
 548
 549     case 0x0340:
 550         /* PLAT: Pchip Master Latency Register.  */
 551         break;
 552     case 0x03c0:
 553         /* PERROR: Pchip Error Register.  */
 554         break;
 555     case 0x0400:
 556         /* PERRMASK: Pchip Error Mask Register.  */
 557         break;
 558     case 0x0440:
 559         /* PERRSET: Pchip Error Set Register.  */
 560         break;
 561
 562     case 0x0480:
 563         /* TLBIV: Translation Buffer Invalidate Virtual Register.  */
 564         break;
 565
 566     case 0x04c0:
 567         /* TLBIA: Translation Buffer Invalidate All Register (WO).  */
 568         break;
 569
 570     case 0x0500:
 571         /* PMONCTL */
 572     case 0x0540:
 573         /* PMONCNT */
 574     case 0x0800:
 575         /* SPRST */
 576         break;
 577
 578     default:
 579         cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
 580         return;
 581     }
 582 }
 583
 584 static const MemoryRegionOps cchip_ops = {
 585     .read = cchip_read,
 586     .write = cchip_write,
 587     .endianness = DEVICE_LITTLE_ENDIAN,
 588     .valid = {
 589         .min_access_size = 4,  /* ??? Should be 8.  */
 590         .max_access_size = 8,
 591     },
 592     .impl = {
 593         .min_access_size = 4,
 594         .max_access_size = 4,
 595     },
 596 };
 597
 598 static const MemoryRegionOps dchip_ops = {
 599     .read = dchip_read,
 600     .write = dchip_write,
 601     .endianness = DEVICE_LITTLE_ENDIAN,
 602     .valid = {
 603         .min_access_size = 4,  /* ??? Should be 8.  */
 604         .max_access_size = 8,
 605     },
 606     .impl = {
 607         .min_access_size = 4,
 608         .max_access_size = 8,
 609     },
 610 };
 611
 612 static const MemoryRegionOps pchip_ops = {
 613     .read = pchip_read,
 614     .write = pchip_write,
 615     .endianness = DEVICE_LITTLE_ENDIAN,
 616     .valid = {
 617         .min_access_size = 4,  /* ??? Should be 8.  */
 618         .max_access_size = 8,
 619     },
 620     .impl = {
 621         .min_access_size = 4,
 622         .max_access_size = 4,
 623     },
 624 };
 625
 626 static void typhoon_set_irq(void *opaque, int irq, int level)
 627 {
 628     TyphoonState *s = opaque;
 629     uint64_t drir;
 630     int i;
 631
 632     /* Set/Reset the bit in CCHIP.DRIR based on IRQ+LEVEL.  */
 633     drir = s->cchip.drir;
 634     if (level) {
 635         drir |= 1ull << irq;
 636     } else {
 637         drir &= ~(1ull << irq);
 638     }
 639     s->cchip.drir = drir;
 640
 641     for (i = 0; i < 4; ++i) {
 642         cpu_irq_change(s->cchip.cpu[i], s->cchip.dim[i] & drir);
 643     }
 644 }
 645
 646 static void typhoon_set_isa_irq(void *opaque, int irq, int level)
 647 {
 648     typhoon_set_irq(opaque, 55, level);
 649 }
 650
 651 static void typhoon_set_timer_irq(void *opaque, int irq, int level)
 652 {
 653     TyphoonState *s = opaque;
 654     int i;
 655
 656     /* Thankfully, the mc146818rtc code doesn't track the IRQ state,
 657        and so we don't have to worry about missing interrupts just
 658        because we never actually ACK the interrupt.  Just ignore any
 659        case of the interrupt level going low.  */
 660     if (level == 0) {
 661         return;
 662     }
 663
 664     /* Deliver the interrupt to each CPU, considering each CPU's IIC.  */
 665     for (i = 0; i < 4; ++i) {
 666         AlphaCPU *cpu = s->cchip.cpu[i];
 667         if (cpu != NULL) {
 668             uint32_t iic = s->cchip.iic[i];
 669
 670             /* ??? The verbage in Section 10.2.2.10 isn't 100% clear.
 671                Bit 24 is the OverFlow bit, RO, and set when the count
 672                decrements past 0.  When is OF cleared?  My guess is that
 673                OF is actually cleared when the IIC is written, and that
 674                the ICNT field always decrements.  At least, that's an
 675                interpretation that makes sense, and "allows the CPU to
 676                determine exactly how mant interval timer ticks were
 677                skipped".  At least within the next 4M ticks...  */
 678
 679             iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000);
 680             s->cchip.iic[i] = iic;
 681
 682             if (iic & 0x1000000) {
 683                 /* Set the ITI bit for this cpu.  */
 684                 s->cchip.misc |= 1 << (i + 4);
 685                 /* And signal the interrupt.  */
 686                 cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER);
 687             }
 688         }
 689     }
 690 }
 691
 692 static void typhoon_alarm_timer(void *opaque)
 693 {
 694     TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3);
 695     int cpu = (uintptr_t)opaque & 3;
 696
 697     /* Set the ITI bit for this cpu.  */
 698     s->cchip.misc |= 1 << (cpu + 4);
 699     cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER);
 700 }
 701
 702 PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
 703                      qemu_irq *p_rtc_irq,
 704                      AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
 705 {
 706     const uint64_t MB = 1024 * 1024;
 707     const uint64_t GB = 1024 * MB;
 708     MemoryRegion *addr_space = get_system_memory();
 709     MemoryRegion *addr_space_io = get_system_io();
 710     DeviceState *dev;
 711     TyphoonState *s;
 712     PCIHostState *phb;
 713     PCIBus *b;
 714     int i;
 715
 716     dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
 717     qdev_init_nofail(dev);
 718
 719     s = TYPHOON_PCI_HOST_BRIDGE(dev);
 720     phb = PCI_HOST_BRIDGE(dev);
 721
 722     /* Remember the CPUs so that we can deliver interrupts to them.  */
 723     for (i = 0; i < 4; i++) {
 724         AlphaCPU *cpu = cpus[i];
 725         s->cchip.cpu[i] = cpu;
 726         if (cpu != NULL) {
 727             cpu->alarm_timer = qemu_new_timer_ns(rtc_clock,
 728                                                  typhoon_alarm_timer,
 729                                                  (void *)((uintptr_t)s + i));
 730         }
 731     }
 732
 733     *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1);
 734
 735     /* Main memory region, 0x00.0000.0000.  Real hardware supports 32GB,
 736        but the address space hole reserved at this point is 8TB.  */
 737     memory_region_init_ram(&s->ram_region, "ram", ram_size);
 738     vmstate_register_ram_global(&s->ram_region);
 739     memory_region_add_subregion(addr_space, 0, &s->ram_region);
 740
 741     /* TIGbus, 0x801.0000.0000, 1GB.  */
 742     /* ??? The TIGbus is used for delivering interrupts, and access to
 743        the flash ROM.  I'm not sure that we need to implement it at all.  */
 744
 745     /* Pchip0 CSRs, 0x801.8000.0000, 256MB.  */
 746     memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB);
 747     memory_region_add_subregion(addr_space, 0x80180000000ULL,
 748                                 &s->pchip.region);
 749
 750     /* Cchip CSRs, 0x801.A000.0000, 256MB.  */
 751     memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB);
 752     memory_region_add_subregion(addr_space, 0x801a0000000ULL,
 753                                 &s->cchip.region);
 754
 755     /* Dchip CSRs, 0x801.B000.0000, 256MB.  */
 756     memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB);
 757     memory_region_add_subregion(addr_space, 0x801b0000000ULL,
 758                                 &s->dchip_region);
 759
 760     /* Pchip0 PCI memory, 0x800.0000.0000, 4GB.  */
 761     memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB);
 762     memory_region_add_subregion(addr_space, 0x80000000000ULL,
 763                                 &s->pchip.reg_mem);
 764
 765     /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB.  */
 766     /* ??? Ideally we drop the "system" i/o space on the floor and give the
 767        PCI subsystem the full address space reserved by the chipset.
 768        We can't do that until the MEM and IO paths in memory.c are unified.  */
 769     memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL,
 770                           "pci0-io", 32*MB);
 771     memory_region_add_subregion(addr_space, 0x801fc000000ULL,
 772                                 &s->pchip.reg_io);
 773
 774     b = pci_register_bus(dev, "pci",
 775                          typhoon_set_irq, sys_map_irq, s,
 776                          &s->pchip.reg_mem, addr_space_io, 0, 64);
 777     phb->bus = b;
 778
 779     /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB.  */
 780     memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,
 781                           "pci0-iack", 64*MB);
 782     memory_region_add_subregion(addr_space, 0x801f8000000ULL,
 783                                 &s->pchip.reg_iack);
 784
 785     /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB.  */
 786     memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b,
 787                           "pci0-conf", 16*MB);
 788     memory_region_add_subregion(addr_space, 0x801fe000000ULL,
 789                                 &s->pchip.reg_conf);
 790
 791     /* For the record, these are the mappings for the second PCI bus.
 792        We can get away with not implementing them because we indicate
 793        via the Cchip.CSC<PIP> bit that Pchip1 is not present.  */
 794     /* Pchip1 PCI memory, 0x802.0000.0000, 4GB.  */
 795     /* Pchip1 CSRs, 0x802.8000.0000, 256MB.  */
 796     /* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB.  */
 797     /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB.  */
 798     /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB.  */
 799
 800     /* Init the ISA bus.  */
 801     /* ??? Technically there should be a cy82c693ub pci-isa bridge.  */
 802     {
 803         qemu_irq isa_pci_irq, *isa_irqs;
 804
 805         *isa_bus = isa_bus_new(NULL, addr_space_io);
 806         isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);
 807         isa_irqs = i8259_init(*isa_bus, isa_pci_irq);
 808         isa_bus_irqs(*isa_bus, isa_irqs);
 809     }
 810
 811     return b;
 812 }
 813
 814 static int typhoon_pcihost_init(SysBusDevice *dev)
 815 {
 816     return 0;
 817 }
 818
 819 static void typhoon_pcihost_class_init(ObjectClass *klass, void *data)
 820 {
 821     DeviceClass *dc = DEVICE_CLASS(klass);
 822     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 823
 824     k->init = typhoon_pcihost_init;
 825     dc->no_user = 1;
 826 }
 827
 828 static const TypeInfo typhoon_pcihost_info = {
 829     .name          = TYPE_TYPHOON_PCI_HOST_BRIDGE,
 830     .parent        = TYPE_PCI_HOST_BRIDGE,
 831     .instance_size = sizeof(TyphoonState),
 832     .class_init    = typhoon_pcihost_class_init,
 833 };
 834
 835 static void typhoon_register_types(void)
 836 {
 837     type_register_static(&typhoon_pcihost_info);
 838 }
 839
 840 type_init(typhoon_register_types)