hw/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "hw.h"
  14 #include "pc.h"
  15 #include "vt82c686.h"
  16 #include "i2c.h"
  17 #include "smbus.h"
  18 #include "pci/pci.h"
  19 #include "isa.h"
  20 #include "sysbus.h"
  21 #include "mips.h"
  22 #include "apm.h"
  23 #include "acpi.h"
  24 #include "pm_smbus.h"
  25 #include "sysemu/sysemu.h"
  26 #include "qemu/timer.h"
  27 #include "exec/address-spaces.h"
  28
  29 typedef uint32_t pci_addr_t;
  30 #include "pci/pci_host.h"
  31 //#define DEBUG_VT82C686B
  32
  33 #ifdef DEBUG_VT82C686B
  34 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  35 #else
  36 #define DPRINTF(fmt, ...)
  37 #endif
  38
  39 typedef struct SuperIOConfig
  40 {
  41     uint8_t config[0xff];
  42     uint8_t index;
  43     uint8_t data;
  44 } SuperIOConfig;
  45
  46 typedef struct VT82C686BState {
  47     PCIDevice dev;
  48     SuperIOConfig superio_conf;
  49 } VT82C686BState;
  50
  51 static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
  52 {
  53     int can_write;
  54     SuperIOConfig *superio_conf = opaque;
  55
  56     DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x\n", addr, data);
  57     if (addr == 0x3f0) {
  58         superio_conf->index = data & 0xff;
  59     } else {
  60         /* 0x3f1 */
  61         switch (superio_conf->index) {
  62         case 0x00 ... 0xdf:
  63         case 0xe4:
  64         case 0xe5:
  65         case 0xe9 ... 0xed:
  66         case 0xf3:
  67         case 0xf5:
  68         case 0xf7:
  69         case 0xf9 ... 0xfb:
  70         case 0xfd ... 0xff:
  71             can_write = 0;
  72             break;
  73         default:
  74             can_write = 1;
  75
  76             if (can_write) {
  77                 switch (superio_conf->index) {
  78                 case 0xe7:
  79                     if ((data & 0xff) != 0xfe) {
  80                         DPRINTF("chage uart 1 base. unsupported yet\n");
  81                     }
  82                     break;
  83                 case 0xe8:
  84                     if ((data & 0xff) != 0xbe) {
  85                         DPRINTF("chage uart 2 base. unsupported yet\n");
  86                     }
  87                     break;
  88
  89                 default:
  90                     superio_conf->config[superio_conf->index] = data & 0xff;
  91                 }
  92             }
  93         }
  94         superio_conf->config[superio_conf->index] = data & 0xff;
  95     }
  96 }
  97
  98 static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
  99 {
 100     SuperIOConfig *superio_conf = opaque;
 101
 102     DPRINTF("superio_ioport_readb  address 0x%x\n", addr);
 103     return (superio_conf->config[superio_conf->index]);
 104 }
 105
 106 static void vt82c686b_reset(void * opaque)
 107 {
 108     PCIDevice *d = opaque;
 109     uint8_t *pci_conf = d->config;
 110     VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
 111
 112     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 113     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 114                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 115     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 116
 117     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 118     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 119     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 120     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 121     pci_conf[0x59] = 0x04;
 122     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 123     pci_conf[0x5f] = 0x04;
 124     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 125
 126     vt82c->superio_conf.config[0xe0] = 0x3c;
 127     vt82c->superio_conf.config[0xe2] = 0x03;
 128     vt82c->superio_conf.config[0xe3] = 0xfc;
 129     vt82c->superio_conf.config[0xe6] = 0xde;
 130     vt82c->superio_conf.config[0xe7] = 0xfe;
 131     vt82c->superio_conf.config[0xe8] = 0xbe;
 132 }
 133
 134 /* write config pci function0 registers. PCI-ISA bridge */
 135 static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
 136                                    uint32_t val, int len)
 137 {
 138     VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
 139
 140     DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x\n",
 141            address, val, len);
 142
 143     pci_default_write_config(d, address, val, len);
 144     if (address == 0x85) {  /* enable or disable super IO configure */
 145         if (val & 0x2) {
 146             /* floppy also uses 0x3f0 and 0x3f1.
 147              * But we do not emulate flopy,so just set it here. */
 148             isa_unassign_ioport(0x3f0, 2);
 149             register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
 150                                  &vt686->superio_conf);
 151             register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
 152                                   &vt686->superio_conf);
 153         } else {
 154             isa_unassign_ioport(0x3f0, 2);
 155         }
 156     }
 157 }
 158
 159 #define ACPI_DBG_IO_ADDR  0xb044
 160
 161 typedef struct VT686PMState {
 162     PCIDevice dev;
 163     MemoryRegion io;
 164     ACPIREGS ar;
 165     APMState apm;
 166     PMSMBus smb;
 167     uint32_t smb_io_base;
 168 } VT686PMState;
 169
 170 typedef struct VT686AC97State {
 171     PCIDevice dev;
 172 } VT686AC97State;
 173
 174 typedef struct VT686MC97State {
 175     PCIDevice dev;
 176 } VT686MC97State;
 177
 178 static void pm_update_sci(VT686PMState *s)
 179 {
 180     int sci_level, pmsts;
 181
 182     pmsts = acpi_pm1_evt_get_sts(&s->ar);
 183     sci_level = (((pmsts & s->ar.pm1.evt.en) &
 184                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 185                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 186                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 187                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 188     qemu_set_irq(s->dev.irq[0], sci_level);
 189     /* schedule a timer interruption if needed */
 190     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 191                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 192 }
 193
 194 static void pm_tmr_timer(ACPIREGS *ar)
 195 {
 196     VT686PMState *s = container_of(ar, VT686PMState, ar);
 197     pm_update_sci(s);
 198 }
 199
 200 static void pm_io_space_update(VT686PMState *s)
 201 {
 202     uint32_t pm_io_base;
 203
 204     pm_io_base = pci_get_long(s->dev.config + 0x40);
 205     pm_io_base &= 0xffc0;
 206
 207     memory_region_transaction_begin();
 208     memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
 209     memory_region_set_address(&s->io, pm_io_base);
 210     memory_region_transaction_commit();
 211 }
 212
 213 static void pm_write_config(PCIDevice *d,
 214                             uint32_t address, uint32_t val, int len)
 215 {
 216     DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x\n",
 217            address, val, len);
 218     pci_default_write_config(d, address, val, len);
 219 }
 220
 221 static int vmstate_acpi_post_load(void *opaque, int version_id)
 222 {
 223     VT686PMState *s = opaque;
 224
 225     pm_io_space_update(s);
 226     return 0;
 227 }
 228
 229 static const VMStateDescription vmstate_acpi = {
 230     .name = "vt82c686b_pm",
 231     .version_id = 1,
 232     .minimum_version_id = 1,
 233     .minimum_version_id_old = 1,
 234     .post_load = vmstate_acpi_post_load,
 235     .fields      = (VMStateField []) {
 236         VMSTATE_PCI_DEVICE(dev, VT686PMState),
 237         VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
 238         VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
 239         VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
 240         VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
 241         VMSTATE_TIMER(ar.tmr.timer, VT686PMState),
 242         VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
 243         VMSTATE_END_OF_LIST()
 244     }
 245 };
 246
 247 /*
 248  * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 249  * just register a PCI device now, functionalities will be implemented later.
 250  */
 251
 252 static int vt82c686b_ac97_initfn(PCIDevice *dev)
 253 {
 254     VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
 255     uint8_t *pci_conf = s->dev.config;
 256
 257     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 258                  PCI_COMMAND_PARITY);
 259     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
 260                  PCI_STATUS_DEVSEL_MEDIUM);
 261     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 262
 263     return 0;
 264 }
 265
 266 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
 267 {
 268     PCIDevice *dev;
 269
 270     dev = pci_create(bus, devfn, "VT82C686B_AC97");
 271     qdev_init_nofail(&dev->qdev);
 272 }
 273
 274 static void via_ac97_class_init(ObjectClass *klass, void *data)
 275 {
 276     DeviceClass *dc = DEVICE_CLASS(klass);
 277     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 278
 279     k->init = vt82c686b_ac97_initfn;
 280     k->vendor_id = PCI_VENDOR_ID_VIA;
 281     k->device_id = PCI_DEVICE_ID_VIA_AC97;
 282     k->revision = 0x50;
 283     k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
 284     dc->desc = "AC97";
 285 }
 286
 287 static const TypeInfo via_ac97_info = {
 288     .name          = "VT82C686B_AC97",
 289     .parent        = TYPE_PCI_DEVICE,
 290     .instance_size = sizeof(VT686AC97State),
 291     .class_init    = via_ac97_class_init,
 292 };
 293
 294 static int vt82c686b_mc97_initfn(PCIDevice *dev)
 295 {
 296     VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
 297     uint8_t *pci_conf = s->dev.config;
 298
 299     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 300                  PCI_COMMAND_VGA_PALETTE);
 301     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 302     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 303
 304     return 0;
 305 }
 306
 307 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
 308 {
 309     PCIDevice *dev;
 310
 311     dev = pci_create(bus, devfn, "VT82C686B_MC97");
 312     qdev_init_nofail(&dev->qdev);
 313 }
 314
 315 static void via_mc97_class_init(ObjectClass *klass, void *data)
 316 {
 317     DeviceClass *dc = DEVICE_CLASS(klass);
 318     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 319
 320     k->init = vt82c686b_mc97_initfn;
 321     k->vendor_id = PCI_VENDOR_ID_VIA;
 322     k->device_id = PCI_DEVICE_ID_VIA_MC97;
 323     k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
 324     k->revision = 0x30;
 325     dc->desc = "MC97";
 326 }
 327
 328 static const TypeInfo via_mc97_info = {
 329     .name          = "VT82C686B_MC97",
 330     .parent        = TYPE_PCI_DEVICE,
 331     .instance_size = sizeof(VT686MC97State),
 332     .class_init    = via_mc97_class_init,
 333 };
 334
 335 /* vt82c686 pm init */
 336 static int vt82c686b_pm_initfn(PCIDevice *dev)
 337 {
 338     VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
 339     uint8_t *pci_conf;
 340
 341     pci_conf = s->dev.config;
 342     pci_set_word(pci_conf + PCI_COMMAND, 0);
 343     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 344                  PCI_STATUS_DEVSEL_MEDIUM);
 345
 346     /* 0x48-0x4B is Power Management I/O Base */
 347     pci_set_long(pci_conf + 0x48, 0x00000001);
 348
 349     /* SMB ports:0xeee0~0xeeef */
 350     s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
 351     pci_conf[0x90] = s->smb_io_base | 1;
 352     pci_conf[0x91] = s->smb_io_base >> 8;
 353     pci_conf[0xd2] = 0x90;
 354     pm_smbus_init(&s->dev.qdev, &s->smb);
 355     memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
 356
 357     apm_init(dev, &s->apm, NULL, s);
 358
 359     memory_region_init(&s->io, "vt82c686-pm", 64);
 360     memory_region_set_enabled(&s->io, false);
 361     memory_region_add_subregion(get_system_io(), 0, &s->io);
 362
 363     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 364     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 365     acpi_pm1_cnt_init(&s->ar, &s->io);
 366
 367     return 0;
 368 }
 369
 370 i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 371                        qemu_irq sci_irq)
 372 {
 373     PCIDevice *dev;
 374     VT686PMState *s;
 375
 376     dev = pci_create(bus, devfn, "VT82C686B_PM");
 377     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 378
 379     s = DO_UPCAST(VT686PMState, dev, dev);
 380
 381     qdev_init_nofail(&dev->qdev);
 382
 383     return s->smb.smbus;
 384 }
 385
 386 static Property via_pm_properties[] = {
 387     DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
 388     DEFINE_PROP_END_OF_LIST(),
 389 };
 390
 391 static void via_pm_class_init(ObjectClass *klass, void *data)
 392 {
 393     DeviceClass *dc = DEVICE_CLASS(klass);
 394     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 395
 396     k->init = vt82c686b_pm_initfn;
 397     k->config_write = pm_write_config;
 398     k->vendor_id = PCI_VENDOR_ID_VIA;
 399     k->device_id = PCI_DEVICE_ID_VIA_ACPI;
 400     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 401     k->revision = 0x40;
 402     dc->desc = "PM";
 403     dc->vmsd = &vmstate_acpi;
 404     dc->props = via_pm_properties;
 405 }
 406
 407 static const TypeInfo via_pm_info = {
 408     .name          = "VT82C686B_PM",
 409     .parent        = TYPE_PCI_DEVICE,
 410     .instance_size = sizeof(VT686PMState),
 411     .class_init    = via_pm_class_init,
 412 };
 413
 414 static const VMStateDescription vmstate_via = {
 415     .name = "vt82c686b",
 416     .version_id = 1,
 417     .minimum_version_id = 1,
 418     .minimum_version_id_old = 1,
 419     .fields      = (VMStateField []) {
 420         VMSTATE_PCI_DEVICE(dev, VT82C686BState),
 421         VMSTATE_END_OF_LIST()
 422     }
 423 };
 424
 425 /* init the PCI-to-ISA bridge */
 426 static int vt82c686b_initfn(PCIDevice *d)
 427 {
 428     uint8_t *pci_conf;
 429     uint8_t *wmask;
 430     int i;
 431
 432     isa_bus_new(&d->qdev, pci_address_space_io(d));
 433
 434     pci_conf = d->config;
 435     pci_config_set_prog_interface(pci_conf, 0x0);
 436
 437     wmask = d->wmask;
 438     for (i = 0x00; i < 0xff; i++) {
 439        if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
 440            wmask[i] = 0x00;
 441        }
 442     }
 443
 444     qemu_register_reset(vt82c686b_reset, d);
 445
 446     return 0;
 447 }
 448
 449 ISABus *vt82c686b_init(PCIBus *bus, int devfn)
 450 {
 451     PCIDevice *d;
 452
 453     d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
 454
 455     return DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0"));
 456 }
 457
 458 static void via_class_init(ObjectClass *klass, void *data)
 459 {
 460     DeviceClass *dc = DEVICE_CLASS(klass);
 461     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 462
 463     k->init = vt82c686b_initfn;
 464     k->config_write = vt82c686b_write_config;
 465     k->vendor_id = PCI_VENDOR_ID_VIA;
 466     k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
 467     k->class_id = PCI_CLASS_BRIDGE_ISA;
 468     k->revision = 0x40;
 469     dc->desc = "ISA bridge";
 470     dc->no_user = 1;
 471     dc->vmsd = &vmstate_via;
 472 }
 473
 474 static const TypeInfo via_info = {
 475     .name          = "VT82C686B",
 476     .parent        = TYPE_PCI_DEVICE,
 477     .instance_size = sizeof(VT82C686BState),
 478     .class_init    = via_class_init,
 479 };
 480
 481 static void vt82c686b_register_types(void)
 482 {
 483     type_register_static(&via_ac97_info);
 484     type_register_static(&via_mc97_info);
 485     type_register_static(&via_pm_info);
 486     type_register_static(&via_info);
 487 }
 488
 489 type_init(vt82c686b_register_types)