hw/gt64xxx.c

   1 /*
   2  * QEMU GT64120 PCI host
   3  *
   4  * Copyright (c) 2006,2007 Aurelien Jarno
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "pc.h"
  30
  31 //#define DEBUG
  32
  33 #ifdef DEBUG
  34 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  35 #else
  36 #define DPRINTF(fmt, ...)
  37 #endif
  38
  39 #define GT_REGS                 (0x1000 >> 2)
  40
  41 /* CPU Configuration */
  42 #define GT_CPU                  (0x000 >> 2)
  43 #define GT_MULTI                (0x120 >> 2)
  44
  45 /* CPU Address Decode */
  46 #define GT_SCS10LD              (0x008 >> 2)
  47 #define GT_SCS10HD              (0x010 >> 2)
  48 #define GT_SCS32LD              (0x018 >> 2)
  49 #define GT_SCS32HD              (0x020 >> 2)
  50 #define GT_CS20LD               (0x028 >> 2)
  51 #define GT_CS20HD               (0x030 >> 2)
  52 #define GT_CS3BOOTLD            (0x038 >> 2)
  53 #define GT_CS3BOOTHD            (0x040 >> 2)
  54 #define GT_PCI0IOLD             (0x048 >> 2)
  55 #define GT_PCI0IOHD             (0x050 >> 2)
  56 #define GT_PCI0M0LD             (0x058 >> 2)
  57 #define GT_PCI0M0HD             (0x060 >> 2)
  58 #define GT_PCI0M1LD             (0x080 >> 2)
  59 #define GT_PCI0M1HD             (0x088 >> 2)
  60 #define GT_PCI1IOLD             (0x090 >> 2)
  61 #define GT_PCI1IOHD             (0x098 >> 2)
  62 #define GT_PCI1M0LD             (0x0a0 >> 2)
  63 #define GT_PCI1M0HD             (0x0a8 >> 2)
  64 #define GT_PCI1M1LD             (0x0b0 >> 2)
  65 #define GT_PCI1M1HD             (0x0b8 >> 2)
  66 #define GT_ISD                  (0x068 >> 2)
  67
  68 #define GT_SCS10AR              (0x0d0 >> 2)
  69 #define GT_SCS32AR              (0x0d8 >> 2)
  70 #define GT_CS20R                (0x0e0 >> 2)
  71 #define GT_CS3BOOTR             (0x0e8 >> 2)
  72
  73 #define GT_PCI0IOREMAP          (0x0f0 >> 2)
  74 #define GT_PCI0M0REMAP          (0x0f8 >> 2)
  75 #define GT_PCI0M1REMAP          (0x100 >> 2)
  76 #define GT_PCI1IOREMAP          (0x108 >> 2)
  77 #define GT_PCI1M0REMAP          (0x110 >> 2)
  78 #define GT_PCI1M1REMAP          (0x118 >> 2)
  79
  80 /* CPU Error Report */
  81 #define GT_CPUERR_ADDRLO        (0x070 >> 2)
  82 #define GT_CPUERR_ADDRHI        (0x078 >> 2)
  83 #define GT_CPUERR_DATALO        (0x128 >> 2)            /* GT-64120A only  */
  84 #define GT_CPUERR_DATAHI        (0x130 >> 2)            /* GT-64120A only  */
  85 #define GT_CPUERR_PARITY        (0x138 >> 2)            /* GT-64120A only  */
  86
  87 /* CPU Sync Barrier */
  88 #define GT_PCI0SYNC             (0x0c0 >> 2)
  89 #define GT_PCI1SYNC             (0x0c8 >> 2)
  90
  91 /* SDRAM and Device Address Decode */
  92 #define GT_SCS0LD               (0x400 >> 2)
  93 #define GT_SCS0HD               (0x404 >> 2)
  94 #define GT_SCS1LD               (0x408 >> 2)
  95 #define GT_SCS1HD               (0x40c >> 2)
  96 #define GT_SCS2LD               (0x410 >> 2)
  97 #define GT_SCS2HD               (0x414 >> 2)
  98 #define GT_SCS3LD               (0x418 >> 2)
  99 #define GT_SCS3HD               (0x41c >> 2)
 100 #define GT_CS0LD                (0x420 >> 2)
 101 #define GT_CS0HD                (0x424 >> 2)
 102 #define GT_CS1LD                (0x428 >> 2)
 103 #define GT_CS1HD                (0x42c >> 2)
 104 #define GT_CS2LD                (0x430 >> 2)
 105 #define GT_CS2HD                (0x434 >> 2)
 106 #define GT_CS3LD                (0x438 >> 2)
 107 #define GT_CS3HD                (0x43c >> 2)
 108 #define GT_BOOTLD               (0x440 >> 2)
 109 #define GT_BOOTHD               (0x444 >> 2)
 110 #define GT_ADERR                (0x470 >> 2)
 111
 112 /* SDRAM Configuration */
 113 #define GT_SDRAM_CFG            (0x448 >> 2)
 114 #define GT_SDRAM_OPMODE         (0x474 >> 2)
 115 #define GT_SDRAM_BM             (0x478 >> 2)
 116 #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 117
 118 /* SDRAM Parameters */
 119 #define GT_SDRAM_B0             (0x44c >> 2)
 120 #define GT_SDRAM_B1             (0x450 >> 2)
 121 #define GT_SDRAM_B2             (0x454 >> 2)
 122 #define GT_SDRAM_B3             (0x458 >> 2)
 123
 124 /* Device Parameters */
 125 #define GT_DEV_B0               (0x45c >> 2)
 126 #define GT_DEV_B1               (0x460 >> 2)
 127 #define GT_DEV_B2               (0x464 >> 2)
 128 #define GT_DEV_B3               (0x468 >> 2)
 129 #define GT_DEV_BOOT             (0x46c >> 2)
 130
 131 /* ECC */
 132 #define GT_ECC_ERRDATALO        (0x480 >> 2)            /* GT-64120A only  */
 133 #define GT_ECC_ERRDATAHI        (0x484 >> 2)            /* GT-64120A only  */
 134 #define GT_ECC_MEM              (0x488 >> 2)            /* GT-64120A only  */
 135 #define GT_ECC_CALC             (0x48c >> 2)            /* GT-64120A only  */
 136 #define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
 137
 138 /* DMA Record */
 139 #define GT_DMA0_CNT             (0x800 >> 2)
 140 #define GT_DMA1_CNT             (0x804 >> 2)
 141 #define GT_DMA2_CNT             (0x808 >> 2)
 142 #define GT_DMA3_CNT             (0x80c >> 2)
 143 #define GT_DMA0_SA              (0x810 >> 2)
 144 #define GT_DMA1_SA              (0x814 >> 2)
 145 #define GT_DMA2_SA              (0x818 >> 2)
 146 #define GT_DMA3_SA              (0x81c >> 2)
 147 #define GT_DMA0_DA              (0x820 >> 2)
 148 #define GT_DMA1_DA              (0x824 >> 2)
 149 #define GT_DMA2_DA              (0x828 >> 2)
 150 #define GT_DMA3_DA              (0x82c >> 2)
 151 #define GT_DMA0_NEXT            (0x830 >> 2)
 152 #define GT_DMA1_NEXT            (0x834 >> 2)
 153 #define GT_DMA2_NEXT            (0x838 >> 2)
 154 #define GT_DMA3_NEXT            (0x83c >> 2)
 155 #define GT_DMA0_CUR             (0x870 >> 2)
 156 #define GT_DMA1_CUR             (0x874 >> 2)
 157 #define GT_DMA2_CUR             (0x878 >> 2)
 158 #define GT_DMA3_CUR             (0x87c >> 2)
 159
 160 /* DMA Channel Control */
 161 #define GT_DMA0_CTRL            (0x840 >> 2)
 162 #define GT_DMA1_CTRL            (0x844 >> 2)
 163 #define GT_DMA2_CTRL            (0x848 >> 2)
 164 #define GT_DMA3_CTRL            (0x84c >> 2)
 165
 166 /* DMA Arbiter */
 167 #define GT_DMA_ARB              (0x860 >> 2)
 168
 169 /* Timer/Counter */
 170 #define GT_TC0                  (0x850 >> 2)
 171 #define GT_TC1                  (0x854 >> 2)
 172 #define GT_TC2                  (0x858 >> 2)
 173 #define GT_TC3                  (0x85c >> 2)
 174 #define GT_TC_CONTROL           (0x864 >> 2)
 175
 176 /* PCI Internal */
 177 #define GT_PCI0_CMD             (0xc00 >> 2)
 178 #define GT_PCI0_TOR             (0xc04 >> 2)
 179 #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 180 #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 181 #define GT_PCI0_BS_CS20         (0xc10 >> 2)
 182 #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 183 #define GT_PCI1_IACK            (0xc30 >> 2)
 184 #define GT_PCI0_IACK            (0xc34 >> 2)
 185 #define GT_PCI0_BARE            (0xc3c >> 2)
 186 #define GT_PCI0_PREFMBR         (0xc40 >> 2)
 187 #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 188 #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 189 #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 190 #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 191 #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 192 #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 193 #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 194 #define GT_PCI1_CMD             (0xc80 >> 2)
 195 #define GT_PCI1_TOR             (0xc84 >> 2)
 196 #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 197 #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 198 #define GT_PCI1_BS_CS20         (0xc90 >> 2)
 199 #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 200 #define GT_PCI1_BARE            (0xcbc >> 2)
 201 #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 202 #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 203 #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 204 #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 205 #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 206 #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 207 #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 208 #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 209 #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 210 #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 211 #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 212 #define GT_PCI0_CFGDATA         (0xcfc >> 2)
 213
 214 /* Interrupts */
 215 #define GT_INTRCAUSE            (0xc18 >> 2)
 216 #define GT_INTRMASK             (0xc1c >> 2)
 217 #define GT_PCI0_ICMASK          (0xc24 >> 2)
 218 #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 219 #define GT_CPU_INTSEL           (0xc70 >> 2)
 220 #define GT_PCI0_INTSEL          (0xc74 >> 2)
 221 #define GT_HINTRCAUSE           (0xc98 >> 2)
 222 #define GT_HINTRMASK            (0xc9c >> 2)
 223 #define GT_PCI0_HICMASK         (0xca4 >> 2)
 224 #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 225
 226
 227 typedef PCIHostState GT64120PCIState;
 228
 229 #define PCI_MAPPING_ENTRY(regname)            \
 230     target_phys_addr_t regname ##_start;      \
 231     target_phys_addr_t regname ##_length;     \
 232     int regname ##_handle
 233
 234 typedef struct GT64120State {
 235     GT64120PCIState *pci;
 236     uint32_t regs[GT_REGS];
 237     PCI_MAPPING_ENTRY(PCI0IO);
 238     PCI_MAPPING_ENTRY(ISD);
 239 } GT64120State;
 240
 241 /* Adjust range to avoid touching space which isn't mappable via PCI */
 242 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
 243                                     0x1fc00000 - 0x1fd00000  */
 244 static void check_reserved_space (target_phys_addr_t *start,
 245                                   target_phys_addr_t *length)
 246 {
 247     target_phys_addr_t begin = *start;
 248     target_phys_addr_t end = *start + *length;
 249
 250     if (end >= 0x1e000000LL && end < 0x1f100000LL)
 251         end = 0x1e000000LL;
 252     if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
 253         begin = 0x1f100000LL;
 254     if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
 255         end = 0x1fc00000LL;
 256     if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
 257         begin = 0x1fd00000LL;
 258     /* XXX: This is broken when a reserved range splits the requested range */
 259     if (end >= 0x1f100000LL && begin < 0x1e000000LL)
 260         end = 0x1e000000LL;
 261     if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
 262         end = 0x1fc00000LL;
 263
 264     *start = begin;
 265     *length = end - begin;
 266 }
 267
 268 static void gt64120_isd_mapping(GT64120State *s)
 269 {
 270     target_phys_addr_t start = s->regs[GT_ISD] << 21;
 271     target_phys_addr_t length = 0x1000;
 272
 273     if (s->ISD_length)
 274         cpu_register_physical_memory(s->ISD_start, s->ISD_length,
 275                                      IO_MEM_UNASSIGNED);
 276     check_reserved_space(&start, &length);
 277     length = 0x1000;
 278     /* Map new address */
 279     DPRINTF("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
 280             length, start, s->ISD_handle);
 281     s->ISD_start = start;
 282     s->ISD_length = length;
 283     cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
 284 }
 285
 286 static void gt64120_pci_mapping(GT64120State *s)
 287 {
 288     /* Update IO mapping */
 289     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
 290     {
 291       /* Unmap old IO address */
 292       if (s->PCI0IO_length)
 293       {
 294         cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
 295       }
 296       /* Map new IO address */
 297       s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 298       s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 299       isa_mem_base = s->PCI0IO_start;
 300 #ifdef TARGET_WORDS_BIGENDIAN
 301       isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 1);
 302 #else
 303       isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 0);
 304 #endif
 305     }
 306 }
 307
 308 static void gt64120_writel (void *opaque, target_phys_addr_t addr,
 309                             uint32_t val)
 310 {
 311     GT64120State *s = opaque;
 312     uint32_t saddr;
 313
 314     if (!(s->regs[GT_CPU] & 0x00001000))
 315         val = bswap32(val);
 316
 317     saddr = (addr & 0xfff) >> 2;
 318     switch (saddr) {
 319
 320     /* CPU Configuration */
 321     case GT_CPU:
 322         s->regs[GT_CPU] = val;
 323         break;
 324     case GT_MULTI:
 325         /* Read-only register as only one GT64xxx is present on the CPU bus */
 326         break;
 327
 328     /* CPU Address Decode */
 329     case GT_PCI0IOLD:
 330         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 331         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 332         gt64120_pci_mapping(s);
 333         break;
 334     case GT_PCI0M0LD:
 335         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 336         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 337         break;
 338     case GT_PCI0M1LD:
 339         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 340         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 341         break;
 342     case GT_PCI1IOLD:
 343         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 344         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 345         break;
 346     case GT_PCI1M0LD:
 347         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 348         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 349         break;
 350     case GT_PCI1M1LD:
 351         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 352         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 353         break;
 354     case GT_PCI0IOHD:
 355         s->regs[saddr] = val & 0x0000007f;
 356         gt64120_pci_mapping(s);
 357         break;
 358     case GT_PCI0M0HD:
 359     case GT_PCI0M1HD:
 360     case GT_PCI1IOHD:
 361     case GT_PCI1M0HD:
 362     case GT_PCI1M1HD:
 363         s->regs[saddr] = val & 0x0000007f;
 364         break;
 365     case GT_ISD:
 366         s->regs[saddr] = val & 0x00007fff;
 367         gt64120_isd_mapping(s);
 368         break;
 369
 370     case GT_PCI0IOREMAP:
 371     case GT_PCI0M0REMAP:
 372     case GT_PCI0M1REMAP:
 373     case GT_PCI1IOREMAP:
 374     case GT_PCI1M0REMAP:
 375     case GT_PCI1M1REMAP:
 376         s->regs[saddr] = val & 0x000007ff;
 377         break;
 378
 379     /* CPU Error Report */
 380     case GT_CPUERR_ADDRLO:
 381     case GT_CPUERR_ADDRHI:
 382     case GT_CPUERR_DATALO:
 383     case GT_CPUERR_DATAHI:
 384     case GT_CPUERR_PARITY:
 385         /* Read-only registers, do nothing */
 386         break;
 387
 388     /* CPU Sync Barrier */
 389     case GT_PCI0SYNC:
 390     case GT_PCI1SYNC:
 391         /* Read-only registers, do nothing */
 392         break;
 393
 394     /* SDRAM and Device Address Decode */
 395     case GT_SCS0LD:
 396     case GT_SCS0HD:
 397     case GT_SCS1LD:
 398     case GT_SCS1HD:
 399     case GT_SCS2LD:
 400     case GT_SCS2HD:
 401     case GT_SCS3LD:
 402     case GT_SCS3HD:
 403     case GT_CS0LD:
 404     case GT_CS0HD:
 405     case GT_CS1LD:
 406     case GT_CS1HD:
 407     case GT_CS2LD:
 408     case GT_CS2HD:
 409     case GT_CS3LD:
 410     case GT_CS3HD:
 411     case GT_BOOTLD:
 412     case GT_BOOTHD:
 413     case GT_ADERR:
 414     /* SDRAM Configuration */
 415     case GT_SDRAM_CFG:
 416     case GT_SDRAM_OPMODE:
 417     case GT_SDRAM_BM:
 418     case GT_SDRAM_ADDRDECODE:
 419         /* Accept and ignore SDRAM interleave configuration */
 420         s->regs[saddr] = val;
 421         break;
 422
 423     /* Device Parameters */
 424     case GT_DEV_B0:
 425     case GT_DEV_B1:
 426     case GT_DEV_B2:
 427     case GT_DEV_B3:
 428     case GT_DEV_BOOT:
 429         /* Not implemented */
 430         DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
 431         break;
 432
 433     /* ECC */
 434     case GT_ECC_ERRDATALO:
 435     case GT_ECC_ERRDATAHI:
 436     case GT_ECC_MEM:
 437     case GT_ECC_CALC:
 438     case GT_ECC_ERRADDR:
 439         /* Read-only registers, do nothing */
 440         break;
 441
 442     /* DMA Record */
 443     case GT_DMA0_CNT:
 444     case GT_DMA1_CNT:
 445     case GT_DMA2_CNT:
 446     case GT_DMA3_CNT:
 447     case GT_DMA0_SA:
 448     case GT_DMA1_SA:
 449     case GT_DMA2_SA:
 450     case GT_DMA3_SA:
 451     case GT_DMA0_DA:
 452     case GT_DMA1_DA:
 453     case GT_DMA2_DA:
 454     case GT_DMA3_DA:
 455     case GT_DMA0_NEXT:
 456     case GT_DMA1_NEXT:
 457     case GT_DMA2_NEXT:
 458     case GT_DMA3_NEXT:
 459     case GT_DMA0_CUR:
 460     case GT_DMA1_CUR:
 461     case GT_DMA2_CUR:
 462     case GT_DMA3_CUR:
 463         /* Not implemented */
 464         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 465         break;
 466
 467     /* DMA Channel Control */
 468     case GT_DMA0_CTRL:
 469     case GT_DMA1_CTRL:
 470     case GT_DMA2_CTRL:
 471     case GT_DMA3_CTRL:
 472         /* Not implemented */
 473         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 474         break;
 475
 476     /* DMA Arbiter */
 477     case GT_DMA_ARB:
 478         /* Not implemented */
 479         DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
 480         break;
 481
 482     /* Timer/Counter */
 483     case GT_TC0:
 484     case GT_TC1:
 485     case GT_TC2:
 486     case GT_TC3:
 487     case GT_TC_CONTROL:
 488         /* Not implemented */
 489         DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
 490         break;
 491
 492     /* PCI Internal */
 493     case GT_PCI0_CMD:
 494     case GT_PCI1_CMD:
 495         s->regs[saddr] = val & 0x0401fc0f;
 496         break;
 497     case GT_PCI0_TOR:
 498     case GT_PCI0_BS_SCS10:
 499     case GT_PCI0_BS_SCS32:
 500     case GT_PCI0_BS_CS20:
 501     case GT_PCI0_BS_CS3BT:
 502     case GT_PCI1_IACK:
 503     case GT_PCI0_IACK:
 504     case GT_PCI0_BARE:
 505     case GT_PCI0_PREFMBR:
 506     case GT_PCI0_SCS10_BAR:
 507     case GT_PCI0_SCS32_BAR:
 508     case GT_PCI0_CS20_BAR:
 509     case GT_PCI0_CS3BT_BAR:
 510     case GT_PCI0_SSCS10_BAR:
 511     case GT_PCI0_SSCS32_BAR:
 512     case GT_PCI0_SCS3BT_BAR:
 513     case GT_PCI1_TOR:
 514     case GT_PCI1_BS_SCS10:
 515     case GT_PCI1_BS_SCS32:
 516     case GT_PCI1_BS_CS20:
 517     case GT_PCI1_BS_CS3BT:
 518     case GT_PCI1_BARE:
 519     case GT_PCI1_PREFMBR:
 520     case GT_PCI1_SCS10_BAR:
 521     case GT_PCI1_SCS32_BAR:
 522     case GT_PCI1_CS20_BAR:
 523     case GT_PCI1_CS3BT_BAR:
 524     case GT_PCI1_SSCS10_BAR:
 525     case GT_PCI1_SSCS32_BAR:
 526     case GT_PCI1_SCS3BT_BAR:
 527     case GT_PCI1_CFGADDR:
 528     case GT_PCI1_CFGDATA:
 529         /* not implemented */
 530         break;
 531     case GT_PCI0_CFGADDR:
 532         s->pci->config_reg = val & 0x80fffffc;
 533         break;
 534     case GT_PCI0_CFGDATA:
 535         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800))
 536             val = bswap32(val);
 537         if (s->pci->config_reg & (1u << 31))
 538             pci_data_write(s->pci->bus, s->pci->config_reg, val, 4);
 539         break;
 540
 541     /* Interrupts */
 542     case GT_INTRCAUSE:
 543         /* not really implemented */
 544         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
 545         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
 546         DPRINTF("INTRCAUSE %x\n", val);
 547         break;
 548     case GT_INTRMASK:
 549         s->regs[saddr] = val & 0x3c3ffffe;
 550         DPRINTF("INTRMASK %x\n", val);
 551         break;
 552     case GT_PCI0_ICMASK:
 553         s->regs[saddr] = val & 0x03fffffe;
 554         DPRINTF("ICMASK %x\n", val);
 555         break;
 556     case GT_PCI0_SERR0MASK:
 557         s->regs[saddr] = val & 0x0000003f;
 558         DPRINTF("SERR0MASK %x\n", val);
 559         break;
 560
 561     /* Reserved when only PCI_0 is configured. */
 562     case GT_HINTRCAUSE:
 563     case GT_CPU_INTSEL:
 564     case GT_PCI0_INTSEL:
 565     case GT_HINTRMASK:
 566     case GT_PCI0_HICMASK:
 567     case GT_PCI1_SERR1MASK:
 568         /* not implemented */
 569         break;
 570
 571     /* SDRAM Parameters */
 572     case GT_SDRAM_B0:
 573     case GT_SDRAM_B1:
 574     case GT_SDRAM_B2:
 575     case GT_SDRAM_B3:
 576         /* We don't simulate electrical parameters of the SDRAM.
 577            Accept, but ignore the values. */
 578         s->regs[saddr] = val;
 579         break;
 580
 581     default:
 582         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 583         break;
 584     }
 585 }
 586
 587 static uint32_t gt64120_readl (void *opaque,
 588                                target_phys_addr_t addr)
 589 {
 590     GT64120State *s = opaque;
 591     uint32_t val;
 592     uint32_t saddr;
 593
 594     saddr = (addr & 0xfff) >> 2;
 595     switch (saddr) {
 596
 597     /* CPU Configuration */
 598     case GT_MULTI:
 599         /* Only one GT64xxx is present on the CPU bus, return
 600            the initial value */
 601         val = s->regs[saddr];
 602         break;
 603
 604     /* CPU Error Report */
 605     case GT_CPUERR_ADDRLO:
 606     case GT_CPUERR_ADDRHI:
 607     case GT_CPUERR_DATALO:
 608     case GT_CPUERR_DATAHI:
 609     case GT_CPUERR_PARITY:
 610         /* Emulated memory has no error, always return the initial
 611            values */
 612         val = s->regs[saddr];
 613         break;
 614
 615     /* CPU Sync Barrier */
 616     case GT_PCI0SYNC:
 617     case GT_PCI1SYNC:
 618         /* Reading those register should empty all FIFO on the PCI
 619            bus, which are not emulated. The return value should be
 620            a random value that should be ignored. */
 621         val = 0xc000ffee;
 622         break;
 623
 624     /* ECC */
 625     case GT_ECC_ERRDATALO:
 626     case GT_ECC_ERRDATAHI:
 627     case GT_ECC_MEM:
 628     case GT_ECC_CALC:
 629     case GT_ECC_ERRADDR:
 630         /* Emulated memory has no error, always return the initial
 631            values */
 632         val = s->regs[saddr];
 633         break;
 634
 635     case GT_CPU:
 636     case GT_SCS10LD:
 637     case GT_SCS10HD:
 638     case GT_SCS32LD:
 639     case GT_SCS32HD:
 640     case GT_CS20LD:
 641     case GT_CS20HD:
 642     case GT_CS3BOOTLD:
 643     case GT_CS3BOOTHD:
 644     case GT_SCS10AR:
 645     case GT_SCS32AR:
 646     case GT_CS20R:
 647     case GT_CS3BOOTR:
 648     case GT_PCI0IOLD:
 649     case GT_PCI0M0LD:
 650     case GT_PCI0M1LD:
 651     case GT_PCI1IOLD:
 652     case GT_PCI1M0LD:
 653     case GT_PCI1M1LD:
 654     case GT_PCI0IOHD:
 655     case GT_PCI0M0HD:
 656     case GT_PCI0M1HD:
 657     case GT_PCI1IOHD:
 658     case GT_PCI1M0HD:
 659     case GT_PCI1M1HD:
 660     case GT_PCI0IOREMAP:
 661     case GT_PCI0M0REMAP:
 662     case GT_PCI0M1REMAP:
 663     case GT_PCI1IOREMAP:
 664     case GT_PCI1M0REMAP:
 665     case GT_PCI1M1REMAP:
 666     case GT_ISD:
 667         val = s->regs[saddr];
 668         break;
 669     case GT_PCI0_IACK:
 670         /* Read the IRQ number */
 671         val = pic_read_irq(isa_pic);
 672         break;
 673
 674     /* SDRAM and Device Address Decode */
 675     case GT_SCS0LD:
 676     case GT_SCS0HD:
 677     case GT_SCS1LD:
 678     case GT_SCS1HD:
 679     case GT_SCS2LD:
 680     case GT_SCS2HD:
 681     case GT_SCS3LD:
 682     case GT_SCS3HD:
 683     case GT_CS0LD:
 684     case GT_CS0HD:
 685     case GT_CS1LD:
 686     case GT_CS1HD:
 687     case GT_CS2LD:
 688     case GT_CS2HD:
 689     case GT_CS3LD:
 690     case GT_CS3HD:
 691     case GT_BOOTLD:
 692     case GT_BOOTHD:
 693     case GT_ADERR:
 694         val = s->regs[saddr];
 695         break;
 696
 697     /* SDRAM Configuration */
 698     case GT_SDRAM_CFG:
 699     case GT_SDRAM_OPMODE:
 700     case GT_SDRAM_BM:
 701     case GT_SDRAM_ADDRDECODE:
 702         val = s->regs[saddr];
 703         break;
 704
 705     /* SDRAM Parameters */
 706     case GT_SDRAM_B0:
 707     case GT_SDRAM_B1:
 708     case GT_SDRAM_B2:
 709     case GT_SDRAM_B3:
 710         /* We don't simulate electrical parameters of the SDRAM.
 711            Just return the last written value. */
 712         val = s->regs[saddr];
 713         break;
 714
 715     /* Device Parameters */
 716     case GT_DEV_B0:
 717     case GT_DEV_B1:
 718     case GT_DEV_B2:
 719     case GT_DEV_B3:
 720     case GT_DEV_BOOT:
 721         val = s->regs[saddr];
 722         break;
 723
 724     /* DMA Record */
 725     case GT_DMA0_CNT:
 726     case GT_DMA1_CNT:
 727     case GT_DMA2_CNT:
 728     case GT_DMA3_CNT:
 729     case GT_DMA0_SA:
 730     case GT_DMA1_SA:
 731     case GT_DMA2_SA:
 732     case GT_DMA3_SA:
 733     case GT_DMA0_DA:
 734     case GT_DMA1_DA:
 735     case GT_DMA2_DA:
 736     case GT_DMA3_DA:
 737     case GT_DMA0_NEXT:
 738     case GT_DMA1_NEXT:
 739     case GT_DMA2_NEXT:
 740     case GT_DMA3_NEXT:
 741     case GT_DMA0_CUR:
 742     case GT_DMA1_CUR:
 743     case GT_DMA2_CUR:
 744     case GT_DMA3_CUR:
 745         val = s->regs[saddr];
 746         break;
 747
 748     /* DMA Channel Control */
 749     case GT_DMA0_CTRL:
 750     case GT_DMA1_CTRL:
 751     case GT_DMA2_CTRL:
 752     case GT_DMA3_CTRL:
 753         val = s->regs[saddr];
 754         break;
 755
 756     /* DMA Arbiter */
 757     case GT_DMA_ARB:
 758         val = s->regs[saddr];
 759         break;
 760
 761     /* Timer/Counter */
 762     case GT_TC0:
 763     case GT_TC1:
 764     case GT_TC2:
 765     case GT_TC3:
 766     case GT_TC_CONTROL:
 767         val = s->regs[saddr];
 768         break;
 769
 770     /* PCI Internal */
 771     case GT_PCI0_CFGADDR:
 772         val = s->pci->config_reg;
 773         break;
 774     case GT_PCI0_CFGDATA:
 775         if (!(s->pci->config_reg & (1 << 31)))
 776             val = 0xffffffff;
 777         else
 778             val = pci_data_read(s->pci->bus, s->pci->config_reg, 4);
 779         if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800))
 780             val = bswap32(val);
 781         break;
 782
 783     case GT_PCI0_CMD:
 784     case GT_PCI0_TOR:
 785     case GT_PCI0_BS_SCS10:
 786     case GT_PCI0_BS_SCS32:
 787     case GT_PCI0_BS_CS20:
 788     case GT_PCI0_BS_CS3BT:
 789     case GT_PCI1_IACK:
 790     case GT_PCI0_BARE:
 791     case GT_PCI0_PREFMBR:
 792     case GT_PCI0_SCS10_BAR:
 793     case GT_PCI0_SCS32_BAR:
 794     case GT_PCI0_CS20_BAR:
 795     case GT_PCI0_CS3BT_BAR:
 796     case GT_PCI0_SSCS10_BAR:
 797     case GT_PCI0_SSCS32_BAR:
 798     case GT_PCI0_SCS3BT_BAR:
 799     case GT_PCI1_CMD:
 800     case GT_PCI1_TOR:
 801     case GT_PCI1_BS_SCS10:
 802     case GT_PCI1_BS_SCS32:
 803     case GT_PCI1_BS_CS20:
 804     case GT_PCI1_BS_CS3BT:
 805     case GT_PCI1_BARE:
 806     case GT_PCI1_PREFMBR:
 807     case GT_PCI1_SCS10_BAR:
 808     case GT_PCI1_SCS32_BAR:
 809     case GT_PCI1_CS20_BAR:
 810     case GT_PCI1_CS3BT_BAR:
 811     case GT_PCI1_SSCS10_BAR:
 812     case GT_PCI1_SSCS32_BAR:
 813     case GT_PCI1_SCS3BT_BAR:
 814     case GT_PCI1_CFGADDR:
 815     case GT_PCI1_CFGDATA:
 816         val = s->regs[saddr];
 817         break;
 818
 819     /* Interrupts */
 820     case GT_INTRCAUSE:
 821         val = s->regs[saddr];
 822         DPRINTF("INTRCAUSE %x\n", val);
 823         break;
 824     case GT_INTRMASK:
 825         val = s->regs[saddr];
 826         DPRINTF("INTRMASK %x\n", val);
 827         break;
 828     case GT_PCI0_ICMASK:
 829         val = s->regs[saddr];
 830         DPRINTF("ICMASK %x\n", val);
 831         break;
 832     case GT_PCI0_SERR0MASK:
 833         val = s->regs[saddr];
 834         DPRINTF("SERR0MASK %x\n", val);
 835         break;
 836
 837     /* Reserved when only PCI_0 is configured. */
 838     case GT_HINTRCAUSE:
 839     case GT_CPU_INTSEL:
 840     case GT_PCI0_INTSEL:
 841     case GT_HINTRMASK:
 842     case GT_PCI0_HICMASK:
 843     case GT_PCI1_SERR1MASK:
 844         val = s->regs[saddr];
 845         break;
 846
 847     default:
 848         val = s->regs[saddr];
 849         DPRINTF ("Bad register offset 0x%x\n", (int)addr);
 850         break;
 851     }
 852
 853     if (!(s->regs[GT_CPU] & 0x00001000))
 854         val = bswap32(val);
 855
 856     return val;
 857 }
 858
 859 static CPUWriteMemoryFunc * const gt64120_write[] = {
 860     &gt64120_writel,
 861     &gt64120_writel,
 862     &gt64120_writel,
 863 };
 864
 865 static CPUReadMemoryFunc * const gt64120_read[] = {
 866     &gt64120_readl,
 867     &gt64120_readl,
 868     &gt64120_readl,
 869 };
 870
 871 static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
 872 {
 873     int slot;
 874
 875     slot = (pci_dev->devfn >> 3);
 876
 877     switch (slot) {
 878       /* PIIX4 USB */
 879       case 10:
 880         return 3;
 881       /* AMD 79C973 Ethernet */
 882       case 11:
 883         return 1;
 884       /* Crystal 4281 Sound */
 885       case 12:
 886         return 2;
 887       /* PCI slot 1 to 4 */
 888       case 18 ... 21:
 889         return ((slot - 18) + irq_num) & 0x03;
 890       /* Unknown device, don't do any translation */
 891       default:
 892         return irq_num;
 893     }
 894 }
 895
 896 static int pci_irq_levels[4];
 897
 898 static void pci_gt64120_set_irq(void *opaque, int irq_num, int level)
 899 {
 900     int i, pic_irq, pic_level;
 901     qemu_irq *pic = opaque;
 902
 903     pci_irq_levels[irq_num] = level;
 904
 905     /* now we change the pic irq level according to the piix irq mappings */
 906     /* XXX: optimize */
 907     pic_irq = piix4_dev->config[0x60 + irq_num];
 908     if (pic_irq < 16) {
 909         /* The pic level is the logical OR of all the PCI irqs mapped
 910            to it */
 911         pic_level = 0;
 912         for (i = 0; i < 4; i++) {
 913             if (pic_irq == piix4_dev->config[0x60 + i])
 914                 pic_level |= pci_irq_levels[i];
 915         }
 916         qemu_set_irq(pic[pic_irq], pic_level);
 917     }
 918 }
 919
 920
 921 static void gt64120_reset(void *opaque)
 922 {
 923     GT64120State *s = opaque;
 924
 925     /* FIXME: Malta specific hw assumptions ahead */
 926
 927     /* CPU Configuration */
 928 #ifdef TARGET_WORDS_BIGENDIAN
 929     s->regs[GT_CPU]           = 0x00000000;
 930 #else
 931     s->regs[GT_CPU]           = 0x00001000;
 932 #endif
 933     s->regs[GT_MULTI]         = 0x00000003;
 934
 935     /* CPU Address decode */
 936     s->regs[GT_SCS10LD]       = 0x00000000;
 937     s->regs[GT_SCS10HD]       = 0x00000007;
 938     s->regs[GT_SCS32LD]       = 0x00000008;
 939     s->regs[GT_SCS32HD]       = 0x0000000f;
 940     s->regs[GT_CS20LD]        = 0x000000e0;
 941     s->regs[GT_CS20HD]        = 0x00000070;
 942     s->regs[GT_CS3BOOTLD]     = 0x000000f8;
 943     s->regs[GT_CS3BOOTHD]     = 0x0000007f;
 944
 945     s->regs[GT_PCI0IOLD]      = 0x00000080;
 946     s->regs[GT_PCI0IOHD]      = 0x0000000f;
 947     s->regs[GT_PCI0M0LD]      = 0x00000090;
 948     s->regs[GT_PCI0M0HD]      = 0x0000001f;
 949     s->regs[GT_ISD]           = 0x000000a0;
 950     s->regs[GT_PCI0M1LD]      = 0x00000790;
 951     s->regs[GT_PCI0M1HD]      = 0x0000001f;
 952     s->regs[GT_PCI1IOLD]      = 0x00000100;
 953     s->regs[GT_PCI1IOHD]      = 0x0000000f;
 954     s->regs[GT_PCI1M0LD]      = 0x00000110;
 955     s->regs[GT_PCI1M0HD]      = 0x0000001f;
 956     s->regs[GT_PCI1M1LD]      = 0x00000120;
 957     s->regs[GT_PCI1M1HD]      = 0x0000002f;
 958
 959     s->regs[GT_SCS10AR]       = 0x00000000;
 960     s->regs[GT_SCS32AR]       = 0x00000008;
 961     s->regs[GT_CS20R]         = 0x000000e0;
 962     s->regs[GT_CS3BOOTR]      = 0x000000f8;
 963
 964     s->regs[GT_PCI0IOREMAP]   = 0x00000080;
 965     s->regs[GT_PCI0M0REMAP]   = 0x00000090;
 966     s->regs[GT_PCI0M1REMAP]   = 0x00000790;
 967     s->regs[GT_PCI1IOREMAP]   = 0x00000100;
 968     s->regs[GT_PCI1M0REMAP]   = 0x00000110;
 969     s->regs[GT_PCI1M1REMAP]   = 0x00000120;
 970
 971     /* CPU Error Report */
 972     s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
 973     s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
 974     s->regs[GT_CPUERR_DATALO] = 0xffffffff;
 975     s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
 976     s->regs[GT_CPUERR_PARITY] = 0x000000ff;
 977
 978     /* CPU Sync Barrier */
 979     s->regs[GT_PCI0SYNC]      = 0x00000000;
 980     s->regs[GT_PCI1SYNC]      = 0x00000000;
 981
 982     /* SDRAM and Device Address Decode */
 983     s->regs[GT_SCS0LD]        = 0x00000000;
 984     s->regs[GT_SCS0HD]        = 0x00000007;
 985     s->regs[GT_SCS1LD]        = 0x00000008;
 986     s->regs[GT_SCS1HD]        = 0x0000000f;
 987     s->regs[GT_SCS2LD]        = 0x00000010;
 988     s->regs[GT_SCS2HD]        = 0x00000017;
 989     s->regs[GT_SCS3LD]        = 0x00000018;
 990     s->regs[GT_SCS3HD]        = 0x0000001f;
 991     s->regs[GT_CS0LD]         = 0x000000c0;
 992     s->regs[GT_CS0HD]         = 0x000000c7;
 993     s->regs[GT_CS1LD]         = 0x000000c8;
 994     s->regs[GT_CS1HD]         = 0x000000cf;
 995     s->regs[GT_CS2LD]         = 0x000000d0;
 996     s->regs[GT_CS2HD]         = 0x000000df;
 997     s->regs[GT_CS3LD]         = 0x000000f0;
 998     s->regs[GT_CS3HD]         = 0x000000fb;
 999     s->regs[GT_BOOTLD]        = 0x000000fc;
1000     s->regs[GT_BOOTHD]        = 0x000000ff;
1001     s->regs[GT_ADERR]         = 0xffffffff;
1002
1003     /* SDRAM Configuration */
1004     s->regs[GT_SDRAM_CFG]     = 0x00000200;
1005     s->regs[GT_SDRAM_OPMODE]  = 0x00000000;
1006     s->regs[GT_SDRAM_BM]      = 0x00000007;
1007     s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1008
1009     /* SDRAM Parameters */
1010     s->regs[GT_SDRAM_B0]      = 0x00000005;
1011     s->regs[GT_SDRAM_B1]      = 0x00000005;
1012     s->regs[GT_SDRAM_B2]      = 0x00000005;
1013     s->regs[GT_SDRAM_B3]      = 0x00000005;
1014
1015     /* ECC */
1016     s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1017     s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1018     s->regs[GT_ECC_MEM]       = 0x00000000;
1019     s->regs[GT_ECC_CALC]      = 0x00000000;
1020     s->regs[GT_ECC_ERRADDR]   = 0x00000000;
1021
1022     /* Device Parameters */
1023     s->regs[GT_DEV_B0]        = 0x386fffff;
1024     s->regs[GT_DEV_B1]        = 0x386fffff;
1025     s->regs[GT_DEV_B2]        = 0x386fffff;
1026     s->regs[GT_DEV_B3]        = 0x386fffff;
1027     s->regs[GT_DEV_BOOT]      = 0x146fffff;
1028
1029     /* DMA registers are all zeroed at reset */
1030
1031     /* Timer/Counter */
1032     s->regs[GT_TC0]           = 0xffffffff;
1033     s->regs[GT_TC1]           = 0x00ffffff;
1034     s->regs[GT_TC2]           = 0x00ffffff;
1035     s->regs[GT_TC3]           = 0x00ffffff;
1036     s->regs[GT_TC_CONTROL]    = 0x00000000;
1037
1038     /* PCI Internal */
1039 #ifdef TARGET_WORDS_BIGENDIAN
1040     s->regs[GT_PCI0_CMD]      = 0x00000000;
1041 #else
1042     s->regs[GT_PCI0_CMD]      = 0x00010001;
1043 #endif
1044     s->regs[GT_PCI0_TOR]      = 0x0000070f;
1045     s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1046     s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1047     s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;
1048     s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1049     s->regs[GT_PCI1_IACK]     = 0x00000000;
1050     s->regs[GT_PCI0_IACK]     = 0x00000000;
1051     s->regs[GT_PCI0_BARE]     = 0x0000000f;
1052     s->regs[GT_PCI0_PREFMBR]  = 0x00000040;
1053     s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1054     s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1055     s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1056     s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1057     s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1058     s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1059     s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1060 #ifdef TARGET_WORDS_BIGENDIAN
1061     s->regs[GT_PCI1_CMD]      = 0x00000000;
1062 #else
1063     s->regs[GT_PCI1_CMD]      = 0x00010001;
1064 #endif
1065     s->regs[GT_PCI1_TOR]      = 0x0000070f;
1066     s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1067     s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1068     s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;
1069     s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1070     s->regs[GT_PCI1_BARE]     = 0x0000000f;
1071     s->regs[GT_PCI1_PREFMBR]  = 0x00000040;
1072     s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1073     s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1074     s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1075     s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1076     s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1077     s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1078     s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1079     s->regs[GT_PCI1_CFGADDR]  = 0x00000000;
1080     s->regs[GT_PCI1_CFGDATA]  = 0x00000000;
1081     s->regs[GT_PCI0_CFGADDR]  = 0x00000000;
1082
1083     /* Interrupt registers are all zeroed at reset */
1084
1085     gt64120_isd_mapping(s);
1086     gt64120_pci_mapping(s);
1087 }
1088
1089 static void gt64120_save(QEMUFile* f, void *opaque)
1090 {
1091     PCIDevice *d = opaque;
1092     pci_device_save(d, f);
1093 }
1094
1095 static int gt64120_load(QEMUFile* f, void *opaque, int version_id)
1096 {
1097     PCIDevice *d = opaque;
1098     int ret;
1099
1100     if (version_id != 1)
1101         return -EINVAL;
1102     ret = pci_device_load(d, f);
1103     if (ret < 0)
1104         return ret;
1105     return 0;
1106 }
1107
1108 PCIBus *pci_gt64120_init(qemu_irq *pic)
1109 {
1110     GT64120State *s;
1111     PCIDevice *d;
1112
1113     s = qemu_mallocz(sizeof(GT64120State));
1114     s->pci = qemu_mallocz(sizeof(GT64120PCIState));
1115
1116     s->pci->bus = pci_register_bus(NULL, "pci",
1117                                    pci_gt64120_set_irq, pci_gt64120_map_irq,
1118                                    pic, 144, 4);
1119     s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s);
1120     d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
1121                             0, NULL, NULL);
1122
1123     /* FIXME: Malta specific hw assumptions ahead */
1124
1125     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MARVELL);
1126     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MARVELL_GT6412X);
1127
1128     d->config[0x04] = 0x00;
1129     d->config[0x05] = 0x00;
1130     d->config[0x06] = 0x80;
1131     d->config[0x07] = 0x02;
1132
1133     d->config[0x08] = 0x10;
1134     d->config[0x09] = 0x00;
1135     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1136
1137     d->config[0x10] = 0x08;
1138     d->config[0x14] = 0x08;
1139     d->config[0x17] = 0x01;
1140     d->config[0x1B] = 0x1c;
1141     d->config[0x1F] = 0x1f;
1142     d->config[0x23] = 0x14;
1143     d->config[0x24] = 0x01;
1144     d->config[0x27] = 0x14;
1145     d->config[0x3D] = 0x01;
1146
1147     gt64120_reset(s);
1148
1149     register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);
1150
1151     return s->pci->bus;
1152 }