target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26 #include "sysemu/sysemu.h"
  27
  28 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  29 {
  30     /* Reset a single ARMCPRegInfo register */
  31     ARMCPRegInfo *ri = value;
  32     ARMCPU *cpu = opaque;
  33
  34     if (ri->type & ARM_CP_SPECIAL) {
  35         return;
  36     }
  37
  38     if (ri->resetfn) {
  39         ri->resetfn(&cpu->env, ri);
  40         return;
  41     }
  42
  43     /* A zero offset is never possible as it would be regs[0]
  44      * so we use it to indicate that reset is being handled elsewhere.
  45      * This is basically only used for fields in non-core coprocessors
  46      * (like the pxa2xx ones).
  47      */
  48     if (!ri->fieldoffset) {
  49         return;
  50     }
  51
  52     if (ri->type & ARM_CP_64BIT) {
  53         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  54     } else {
  55         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  56     }
  57 }
  58
  59 /* CPUClass::reset() */
  60 static void arm_cpu_reset(CPUState *s)
  61 {
  62     ARMCPU *cpu = ARM_CPU(s);
  63     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  64     CPUARMState *env = &cpu->env;
  65
  66     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  67         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  68         log_cpu_state(env, 0);
  69     }
  70
  71     acc->parent_reset(s);
  72
  73     memset(env, 0, offsetof(CPUARMState, breakpoints));
  74     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  75     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  76     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  77     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  78
  79     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  80         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  81     }
  82
  83 #if defined(CONFIG_USER_ONLY)
  84     env->uncached_cpsr = ARM_CPU_MODE_USR;
  85     /* For user mode we must enable access to coprocessors */
  86     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  87     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  88         env->cp15.c15_cpar = 3;
  89     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
  90         env->cp15.c15_cpar = 1;
  91     }
  92 #else
  93     /* SVC mode with interrupts disabled.  */
  94     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
  95     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
  96        clear at reset.  Initial SP and PC are loaded from ROM.  */
  97     if (IS_M(env)) {
  98         uint32_t pc;
  99         uint8_t *rom;
 100         env->uncached_cpsr &= ~CPSR_I;
 101         rom = rom_ptr(0);
 102         if (rom) {
 103             /* We should really use ldl_phys here, in case the guest
 104                modified flash and reset itself.  However images
 105                loaded via -kernel have not been copied yet, so load the
 106                values directly from there.  */
 107             env->regs[13] = ldl_p(rom);
 108             pc = ldl_p(rom + 4);
 109             env->thumb = pc & 1;
 110             env->regs[15] = pc & ~1;
 111         }
 112     }
 113     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 114 #endif
 115     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 116     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 117     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 118     set_float_detect_tininess(float_tininess_before_rounding,
 119                               &env->vfp.fp_status);
 120     set_float_detect_tininess(float_tininess_before_rounding,
 121                               &env->vfp.standard_fp_status);
 122     tlb_flush(env, 1);
 123     /* Reset is a state change for some CPUARMState fields which we
 124      * bake assumptions about into translated code, so we need to
 125      * tb_flush().
 126      */
 127     tb_flush(env);
 128 }
 129
 130 static inline void set_feature(CPUARMState *env, int feature)
 131 {
 132     env->features |= 1ULL << feature;
 133 }
 134
 135 static void arm_cpu_initfn(Object *obj)
 136 {
 137     CPUState *cs = CPU(obj);
 138     ARMCPU *cpu = ARM_CPU(obj);
 139     static bool inited;
 140
 141     cs->env_ptr = &cpu->env;
 142     cpu_exec_init(&cpu->env);
 143     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 144                                          g_free, g_free);
 145
 146     if (tcg_enabled() && !inited) {
 147         inited = true;
 148         arm_translate_init();
 149     }
 150 }
 151
 152 static void arm_cpu_finalizefn(Object *obj)
 153 {
 154     ARMCPU *cpu = ARM_CPU(obj);
 155     g_hash_table_destroy(cpu->cp_regs);
 156 }
 157
 158 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 159 {
 160     ARMCPU *cpu = ARM_CPU(dev);
 161     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 162     CPUARMState *env = &cpu->env;
 163
 164     /* Some features automatically imply others: */
 165     if (arm_feature(env, ARM_FEATURE_V7)) {
 166         set_feature(env, ARM_FEATURE_VAPA);
 167         set_feature(env, ARM_FEATURE_THUMB2);
 168         set_feature(env, ARM_FEATURE_MPIDR);
 169         if (!arm_feature(env, ARM_FEATURE_M)) {
 170             set_feature(env, ARM_FEATURE_V6K);
 171         } else {
 172             set_feature(env, ARM_FEATURE_V6);
 173         }
 174     }
 175     if (arm_feature(env, ARM_FEATURE_V6K)) {
 176         set_feature(env, ARM_FEATURE_V6);
 177         set_feature(env, ARM_FEATURE_MVFR);
 178     }
 179     if (arm_feature(env, ARM_FEATURE_V6)) {
 180         set_feature(env, ARM_FEATURE_V5);
 181         if (!arm_feature(env, ARM_FEATURE_M)) {
 182             set_feature(env, ARM_FEATURE_AUXCR);
 183         }
 184     }
 185     if (arm_feature(env, ARM_FEATURE_V5)) {
 186         set_feature(env, ARM_FEATURE_V4T);
 187     }
 188     if (arm_feature(env, ARM_FEATURE_M)) {
 189         set_feature(env, ARM_FEATURE_THUMB_DIV);
 190     }
 191     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 192         set_feature(env, ARM_FEATURE_THUMB_DIV);
 193     }
 194     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 195         set_feature(env, ARM_FEATURE_VFP3);
 196     }
 197     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 198         set_feature(env, ARM_FEATURE_VFP);
 199     }
 200     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 201         set_feature(env, ARM_FEATURE_PXN);
 202     }
 203
 204     register_cp_regs_for_features(cpu);
 205     arm_cpu_register_gdb_regs_for_features(cpu);
 206
 207     cpu_reset(CPU(cpu));
 208     qemu_init_vcpu(env);
 209
 210     acc->parent_realize(dev, errp);
 211 }
 212
 213 /* CPU models */
 214
 215 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 216 {
 217     ObjectClass *oc;
 218     char *typename;
 219
 220     if (!cpu_model) {
 221         return NULL;
 222     }
 223
 224     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 225     oc = object_class_by_name(typename);
 226     g_free(typename);
 227     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 228         object_class_is_abstract(oc)) {
 229         return NULL;
 230     }
 231     return oc;
 232 }
 233
 234 static void arm926_initfn(Object *obj)
 235 {
 236     ARMCPU *cpu = ARM_CPU(obj);
 237     set_feature(&cpu->env, ARM_FEATURE_V5);
 238     set_feature(&cpu->env, ARM_FEATURE_VFP);
 239     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 240     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 241     cpu->midr = 0x41069265;
 242     cpu->reset_fpsid = 0x41011090;
 243     cpu->ctr = 0x1dd20d2;
 244     cpu->reset_sctlr = 0x00090078;
 245 }
 246
 247 static void arm946_initfn(Object *obj)
 248 {
 249     ARMCPU *cpu = ARM_CPU(obj);
 250     set_feature(&cpu->env, ARM_FEATURE_V5);
 251     set_feature(&cpu->env, ARM_FEATURE_MPU);
 252     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 253     cpu->midr = 0x41059461;
 254     cpu->ctr = 0x0f004006;
 255     cpu->reset_sctlr = 0x00000078;
 256 }
 257
 258 static void arm1026_initfn(Object *obj)
 259 {
 260     ARMCPU *cpu = ARM_CPU(obj);
 261     set_feature(&cpu->env, ARM_FEATURE_V5);
 262     set_feature(&cpu->env, ARM_FEATURE_VFP);
 263     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 264     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 265     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 266     cpu->midr = 0x4106a262;
 267     cpu->reset_fpsid = 0x410110a0;
 268     cpu->ctr = 0x1dd20d2;
 269     cpu->reset_sctlr = 0x00090078;
 270     cpu->reset_auxcr = 1;
 271     {
 272         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 273         ARMCPRegInfo ifar = {
 274             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 275             .access = PL1_RW,
 276             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 277             .resetvalue = 0
 278         };
 279         define_one_arm_cp_reg(cpu, &ifar);
 280     }
 281 }
 282
 283 static void arm1136_r2_initfn(Object *obj)
 284 {
 285     ARMCPU *cpu = ARM_CPU(obj);
 286     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 287      * older core than plain "arm1136". In particular this does not
 288      * have the v6K features.
 289      * These ID register values are correct for 1136 but may be wrong
 290      * for 1136_r2 (in particular r0p2 does not actually implement most
 291      * of the ID registers).
 292      */
 293     set_feature(&cpu->env, ARM_FEATURE_V6);
 294     set_feature(&cpu->env, ARM_FEATURE_VFP);
 295     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 296     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 297     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 298     cpu->midr = 0x4107b362;
 299     cpu->reset_fpsid = 0x410120b4;
 300     cpu->mvfr0 = 0x11111111;
 301     cpu->mvfr1 = 0x00000000;
 302     cpu->ctr = 0x1dd20d2;
 303     cpu->reset_sctlr = 0x00050078;
 304     cpu->id_pfr0 = 0x111;
 305     cpu->id_pfr1 = 0x1;
 306     cpu->id_dfr0 = 0x2;
 307     cpu->id_afr0 = 0x3;
 308     cpu->id_mmfr0 = 0x01130003;
 309     cpu->id_mmfr1 = 0x10030302;
 310     cpu->id_mmfr2 = 0x01222110;
 311     cpu->id_isar0 = 0x00140011;
 312     cpu->id_isar1 = 0x12002111;
 313     cpu->id_isar2 = 0x11231111;
 314     cpu->id_isar3 = 0x01102131;
 315     cpu->id_isar4 = 0x141;
 316     cpu->reset_auxcr = 7;
 317 }
 318
 319 static void arm1136_initfn(Object *obj)
 320 {
 321     ARMCPU *cpu = ARM_CPU(obj);
 322     set_feature(&cpu->env, ARM_FEATURE_V6K);
 323     set_feature(&cpu->env, ARM_FEATURE_V6);
 324     set_feature(&cpu->env, ARM_FEATURE_VFP);
 325     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 326     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 327     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 328     cpu->midr = 0x4117b363;
 329     cpu->reset_fpsid = 0x410120b4;
 330     cpu->mvfr0 = 0x11111111;
 331     cpu->mvfr1 = 0x00000000;
 332     cpu->ctr = 0x1dd20d2;
 333     cpu->reset_sctlr = 0x00050078;
 334     cpu->id_pfr0 = 0x111;
 335     cpu->id_pfr1 = 0x1;
 336     cpu->id_dfr0 = 0x2;
 337     cpu->id_afr0 = 0x3;
 338     cpu->id_mmfr0 = 0x01130003;
 339     cpu->id_mmfr1 = 0x10030302;
 340     cpu->id_mmfr2 = 0x01222110;
 341     cpu->id_isar0 = 0x00140011;
 342     cpu->id_isar1 = 0x12002111;
 343     cpu->id_isar2 = 0x11231111;
 344     cpu->id_isar3 = 0x01102131;
 345     cpu->id_isar4 = 0x141;
 346     cpu->reset_auxcr = 7;
 347 }
 348
 349 static void arm1176_initfn(Object *obj)
 350 {
 351     ARMCPU *cpu = ARM_CPU(obj);
 352     set_feature(&cpu->env, ARM_FEATURE_V6K);
 353     set_feature(&cpu->env, ARM_FEATURE_VFP);
 354     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 355     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 356     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 357     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 358     cpu->midr = 0x410fb767;
 359     cpu->reset_fpsid = 0x410120b5;
 360     cpu->mvfr0 = 0x11111111;
 361     cpu->mvfr1 = 0x00000000;
 362     cpu->ctr = 0x1dd20d2;
 363     cpu->reset_sctlr = 0x00050078;
 364     cpu->id_pfr0 = 0x111;
 365     cpu->id_pfr1 = 0x11;
 366     cpu->id_dfr0 = 0x33;
 367     cpu->id_afr0 = 0;
 368     cpu->id_mmfr0 = 0x01130003;
 369     cpu->id_mmfr1 = 0x10030302;
 370     cpu->id_mmfr2 = 0x01222100;
 371     cpu->id_isar0 = 0x0140011;
 372     cpu->id_isar1 = 0x12002111;
 373     cpu->id_isar2 = 0x11231121;
 374     cpu->id_isar3 = 0x01102131;
 375     cpu->id_isar4 = 0x01141;
 376     cpu->reset_auxcr = 7;
 377 }
 378
 379 static void arm11mpcore_initfn(Object *obj)
 380 {
 381     ARMCPU *cpu = ARM_CPU(obj);
 382     set_feature(&cpu->env, ARM_FEATURE_V6K);
 383     set_feature(&cpu->env, ARM_FEATURE_VFP);
 384     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 385     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 386     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 387     cpu->midr = 0x410fb022;
 388     cpu->reset_fpsid = 0x410120b4;
 389     cpu->mvfr0 = 0x11111111;
 390     cpu->mvfr1 = 0x00000000;
 391     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 392     cpu->id_pfr0 = 0x111;
 393     cpu->id_pfr1 = 0x1;
 394     cpu->id_dfr0 = 0;
 395     cpu->id_afr0 = 0x2;
 396     cpu->id_mmfr0 = 0x01100103;
 397     cpu->id_mmfr1 = 0x10020302;
 398     cpu->id_mmfr2 = 0x01222000;
 399     cpu->id_isar0 = 0x00100011;
 400     cpu->id_isar1 = 0x12002111;
 401     cpu->id_isar2 = 0x11221011;
 402     cpu->id_isar3 = 0x01102131;
 403     cpu->id_isar4 = 0x141;
 404     cpu->reset_auxcr = 1;
 405 }
 406
 407 static void cortex_m3_initfn(Object *obj)
 408 {
 409     ARMCPU *cpu = ARM_CPU(obj);
 410     set_feature(&cpu->env, ARM_FEATURE_V7);
 411     set_feature(&cpu->env, ARM_FEATURE_M);
 412     cpu->midr = 0x410fc231;
 413 }
 414
 415 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 416     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 417       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 418     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 419       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 420     REGINFO_SENTINEL
 421 };
 422
 423 static void cortex_a8_initfn(Object *obj)
 424 {
 425     ARMCPU *cpu = ARM_CPU(obj);
 426     set_feature(&cpu->env, ARM_FEATURE_V7);
 427     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 428     set_feature(&cpu->env, ARM_FEATURE_NEON);
 429     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 430     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 431     cpu->midr = 0x410fc080;
 432     cpu->reset_fpsid = 0x410330c0;
 433     cpu->mvfr0 = 0x11110222;
 434     cpu->mvfr1 = 0x00011100;
 435     cpu->ctr = 0x82048004;
 436     cpu->reset_sctlr = 0x00c50078;
 437     cpu->id_pfr0 = 0x1031;
 438     cpu->id_pfr1 = 0x11;
 439     cpu->id_dfr0 = 0x400;
 440     cpu->id_afr0 = 0;
 441     cpu->id_mmfr0 = 0x31100003;
 442     cpu->id_mmfr1 = 0x20000000;
 443     cpu->id_mmfr2 = 0x01202000;
 444     cpu->id_mmfr3 = 0x11;
 445     cpu->id_isar0 = 0x00101111;
 446     cpu->id_isar1 = 0x12112111;
 447     cpu->id_isar2 = 0x21232031;
 448     cpu->id_isar3 = 0x11112131;
 449     cpu->id_isar4 = 0x00111142;
 450     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 451     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 452     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 453     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 454     cpu->reset_auxcr = 2;
 455     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 456 }
 457
 458 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 459     /* power_control should be set to maximum latency. Again,
 460      * default to 0 and set by private hook
 461      */
 462     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 463       .access = PL1_RW, .resetvalue = 0,
 464       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 465     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 466       .access = PL1_RW, .resetvalue = 0,
 467       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 468     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 469       .access = PL1_RW, .resetvalue = 0,
 470       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 471     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 472       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 473     /* TLB lockdown control */
 474     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 475       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 476     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 477       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 478     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 479       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 480     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 481       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 482     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 483       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 484     REGINFO_SENTINEL
 485 };
 486
 487 static void cortex_a9_initfn(Object *obj)
 488 {
 489     ARMCPU *cpu = ARM_CPU(obj);
 490     set_feature(&cpu->env, ARM_FEATURE_V7);
 491     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 492     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 493     set_feature(&cpu->env, ARM_FEATURE_NEON);
 494     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 495     /* Note that A9 supports the MP extensions even for
 496      * A9UP and single-core A9MP (which are both different
 497      * and valid configurations; we don't model A9UP).
 498      */
 499     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 500     cpu->midr = 0x410fc090;
 501     cpu->reset_fpsid = 0x41033090;
 502     cpu->mvfr0 = 0x11110222;
 503     cpu->mvfr1 = 0x01111111;
 504     cpu->ctr = 0x80038003;
 505     cpu->reset_sctlr = 0x00c50078;
 506     cpu->id_pfr0 = 0x1031;
 507     cpu->id_pfr1 = 0x11;
 508     cpu->id_dfr0 = 0x000;
 509     cpu->id_afr0 = 0;
 510     cpu->id_mmfr0 = 0x00100103;
 511     cpu->id_mmfr1 = 0x20000000;
 512     cpu->id_mmfr2 = 0x01230000;
 513     cpu->id_mmfr3 = 0x00002111;
 514     cpu->id_isar0 = 0x00101111;
 515     cpu->id_isar1 = 0x13112111;
 516     cpu->id_isar2 = 0x21232041;
 517     cpu->id_isar3 = 0x11112131;
 518     cpu->id_isar4 = 0x00111142;
 519     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 520     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 521     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 522     {
 523         ARMCPRegInfo cbar = {
 524             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 525             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 526             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 527         };
 528         define_one_arm_cp_reg(cpu, &cbar);
 529         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 530     }
 531 }
 532
 533 #ifndef CONFIG_USER_ONLY
 534 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 535                            uint64_t *value)
 536 {
 537     /* Linux wants the number of processors from here.
 538      * Might as well set the interrupt-controller bit too.
 539      */
 540     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 541     return 0;
 542 }
 543 #endif
 544
 545 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 546 #ifndef CONFIG_USER_ONLY
 547     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 548       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 549       .writefn = arm_cp_write_ignore, },
 550 #endif
 551     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 552       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 553     REGINFO_SENTINEL
 554 };
 555
 556 static void cortex_a15_initfn(Object *obj)
 557 {
 558     ARMCPU *cpu = ARM_CPU(obj);
 559     set_feature(&cpu->env, ARM_FEATURE_V7);
 560     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 561     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 562     set_feature(&cpu->env, ARM_FEATURE_NEON);
 563     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 564     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 565     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 566     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 567     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 568     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 569     cpu->midr = 0x412fc0f1;
 570     cpu->reset_fpsid = 0x410430f0;
 571     cpu->mvfr0 = 0x10110222;
 572     cpu->mvfr1 = 0x11111111;
 573     cpu->ctr = 0x8444c004;
 574     cpu->reset_sctlr = 0x00c50078;
 575     cpu->id_pfr0 = 0x00001131;
 576     cpu->id_pfr1 = 0x00011011;
 577     cpu->id_dfr0 = 0x02010555;
 578     cpu->id_afr0 = 0x00000000;
 579     cpu->id_mmfr0 = 0x10201105;
 580     cpu->id_mmfr1 = 0x20000000;
 581     cpu->id_mmfr2 = 0x01240000;
 582     cpu->id_mmfr3 = 0x02102211;
 583     cpu->id_isar0 = 0x02101110;
 584     cpu->id_isar1 = 0x13112111;
 585     cpu->id_isar2 = 0x21232041;
 586     cpu->id_isar3 = 0x11112131;
 587     cpu->id_isar4 = 0x10011142;
 588     cpu->clidr = 0x0a200023;
 589     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 590     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 591     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 592     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 593 }
 594
 595 static void ti925t_initfn(Object *obj)
 596 {
 597     ARMCPU *cpu = ARM_CPU(obj);
 598     set_feature(&cpu->env, ARM_FEATURE_V4T);
 599     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 600     cpu->midr = ARM_CPUID_TI925T;
 601     cpu->ctr = 0x5109149;
 602     cpu->reset_sctlr = 0x00000070;
 603 }
 604
 605 static void sa1100_initfn(Object *obj)
 606 {
 607     ARMCPU *cpu = ARM_CPU(obj);
 608     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 609     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 610     cpu->midr = 0x4401A11B;
 611     cpu->reset_sctlr = 0x00000070;
 612 }
 613
 614 static void sa1110_initfn(Object *obj)
 615 {
 616     ARMCPU *cpu = ARM_CPU(obj);
 617     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 618     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 619     cpu->midr = 0x6901B119;
 620     cpu->reset_sctlr = 0x00000070;
 621 }
 622
 623 static void pxa250_initfn(Object *obj)
 624 {
 625     ARMCPU *cpu = ARM_CPU(obj);
 626     set_feature(&cpu->env, ARM_FEATURE_V5);
 627     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 628     cpu->midr = 0x69052100;
 629     cpu->ctr = 0xd172172;
 630     cpu->reset_sctlr = 0x00000078;
 631 }
 632
 633 static void pxa255_initfn(Object *obj)
 634 {
 635     ARMCPU *cpu = ARM_CPU(obj);
 636     set_feature(&cpu->env, ARM_FEATURE_V5);
 637     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 638     cpu->midr = 0x69052d00;
 639     cpu->ctr = 0xd172172;
 640     cpu->reset_sctlr = 0x00000078;
 641 }
 642
 643 static void pxa260_initfn(Object *obj)
 644 {
 645     ARMCPU *cpu = ARM_CPU(obj);
 646     set_feature(&cpu->env, ARM_FEATURE_V5);
 647     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 648     cpu->midr = 0x69052903;
 649     cpu->ctr = 0xd172172;
 650     cpu->reset_sctlr = 0x00000078;
 651 }
 652
 653 static void pxa261_initfn(Object *obj)
 654 {
 655     ARMCPU *cpu = ARM_CPU(obj);
 656     set_feature(&cpu->env, ARM_FEATURE_V5);
 657     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 658     cpu->midr = 0x69052d05;
 659     cpu->ctr = 0xd172172;
 660     cpu->reset_sctlr = 0x00000078;
 661 }
 662
 663 static void pxa262_initfn(Object *obj)
 664 {
 665     ARMCPU *cpu = ARM_CPU(obj);
 666     set_feature(&cpu->env, ARM_FEATURE_V5);
 667     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 668     cpu->midr = 0x69052d06;
 669     cpu->ctr = 0xd172172;
 670     cpu->reset_sctlr = 0x00000078;
 671 }
 672
 673 static void pxa270a0_initfn(Object *obj)
 674 {
 675     ARMCPU *cpu = ARM_CPU(obj);
 676     set_feature(&cpu->env, ARM_FEATURE_V5);
 677     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 678     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 679     cpu->midr = 0x69054110;
 680     cpu->ctr = 0xd172172;
 681     cpu->reset_sctlr = 0x00000078;
 682 }
 683
 684 static void pxa270a1_initfn(Object *obj)
 685 {
 686     ARMCPU *cpu = ARM_CPU(obj);
 687     set_feature(&cpu->env, ARM_FEATURE_V5);
 688     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 689     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 690     cpu->midr = 0x69054111;
 691     cpu->ctr = 0xd172172;
 692     cpu->reset_sctlr = 0x00000078;
 693 }
 694
 695 static void pxa270b0_initfn(Object *obj)
 696 {
 697     ARMCPU *cpu = ARM_CPU(obj);
 698     set_feature(&cpu->env, ARM_FEATURE_V5);
 699     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 700     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 701     cpu->midr = 0x69054112;
 702     cpu->ctr = 0xd172172;
 703     cpu->reset_sctlr = 0x00000078;
 704 }
 705
 706 static void pxa270b1_initfn(Object *obj)
 707 {
 708     ARMCPU *cpu = ARM_CPU(obj);
 709     set_feature(&cpu->env, ARM_FEATURE_V5);
 710     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 711     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 712     cpu->midr = 0x69054113;
 713     cpu->ctr = 0xd172172;
 714     cpu->reset_sctlr = 0x00000078;
 715 }
 716
 717 static void pxa270c0_initfn(Object *obj)
 718 {
 719     ARMCPU *cpu = ARM_CPU(obj);
 720     set_feature(&cpu->env, ARM_FEATURE_V5);
 721     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 722     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 723     cpu->midr = 0x69054114;
 724     cpu->ctr = 0xd172172;
 725     cpu->reset_sctlr = 0x00000078;
 726 }
 727
 728 static void pxa270c5_initfn(Object *obj)
 729 {
 730     ARMCPU *cpu = ARM_CPU(obj);
 731     set_feature(&cpu->env, ARM_FEATURE_V5);
 732     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 733     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 734     cpu->midr = 0x69054117;
 735     cpu->ctr = 0xd172172;
 736     cpu->reset_sctlr = 0x00000078;
 737 }
 738
 739 static void arm_any_initfn(Object *obj)
 740 {
 741     ARMCPU *cpu = ARM_CPU(obj);
 742     set_feature(&cpu->env, ARM_FEATURE_V7);
 743     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 744     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 745     set_feature(&cpu->env, ARM_FEATURE_NEON);
 746     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 747     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 748     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 749     cpu->midr = 0xffffffff;
 750 }
 751
 752 typedef struct ARMCPUInfo {
 753     const char *name;
 754     void (*initfn)(Object *obj);
 755 } ARMCPUInfo;
 756
 757 static const ARMCPUInfo arm_cpus[] = {
 758     { .name = "arm926",      .initfn = arm926_initfn },
 759     { .name = "arm946",      .initfn = arm946_initfn },
 760     { .name = "arm1026",     .initfn = arm1026_initfn },
 761     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 762      * older core than plain "arm1136". In particular this does not
 763      * have the v6K features.
 764      */
 765     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 766     { .name = "arm1136",     .initfn = arm1136_initfn },
 767     { .name = "arm1176",     .initfn = arm1176_initfn },
 768     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 769     { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
 770     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 771     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 772     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 773     { .name = "ti925t",      .initfn = ti925t_initfn },
 774     { .name = "sa1100",      .initfn = sa1100_initfn },
 775     { .name = "sa1110",      .initfn = sa1110_initfn },
 776     { .name = "pxa250",      .initfn = pxa250_initfn },
 777     { .name = "pxa255",      .initfn = pxa255_initfn },
 778     { .name = "pxa260",      .initfn = pxa260_initfn },
 779     { .name = "pxa261",      .initfn = pxa261_initfn },
 780     { .name = "pxa262",      .initfn = pxa262_initfn },
 781     /* "pxa270" is an alias for "pxa270-a0" */
 782     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 783     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 784     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 785     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 786     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 787     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 788     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 789     { .name = "any",         .initfn = arm_any_initfn },
 790 };
 791
 792 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 793 {
 794     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 795     CPUClass *cc = CPU_CLASS(acc);
 796     DeviceClass *dc = DEVICE_CLASS(oc);
 797
 798     acc->parent_realize = dc->realize;
 799     dc->realize = arm_cpu_realizefn;
 800
 801     acc->parent_reset = cc->reset;
 802     cc->reset = arm_cpu_reset;
 803
 804     cc->class_by_name = arm_cpu_class_by_name;
 805     cc->do_interrupt = arm_cpu_do_interrupt;
 806 }
 807
 808 static void cpu_register(const ARMCPUInfo *info)
 809 {
 810     TypeInfo type_info = {
 811         .parent = TYPE_ARM_CPU,
 812         .instance_size = sizeof(ARMCPU),
 813         .instance_init = info->initfn,
 814         .class_size = sizeof(ARMCPUClass),
 815     };
 816
 817     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 818     type_register(&type_info);
 819     g_free((void *)type_info.name);
 820 }
 821
 822 static const TypeInfo arm_cpu_type_info = {
 823     .name = TYPE_ARM_CPU,
 824     .parent = TYPE_CPU,
 825     .instance_size = sizeof(ARMCPU),
 826     .instance_init = arm_cpu_initfn,
 827     .instance_finalize = arm_cpu_finalizefn,
 828     .abstract = true,
 829     .class_size = sizeof(ARMCPUClass),
 830     .class_init = arm_cpu_class_init,
 831 };
 832
 833 static void arm_cpu_register_types(void)
 834 {
 835     int i;
 836
 837     type_register_static(&arm_cpu_type_info);
 838     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 839         cpu_register(&arm_cpus[i]);
 840     }
 841 }
 842
 843 type_init(arm_cpu_register_types)