PPC: e500: Declare pci bridge as bridge
[qemu/agraf.git] / cpu-common.h
blobd2fbafac9c5a62c68ceb937c14a67cace81bdc9a
1 #ifndef CPU_COMMON_H
2 #define CPU_COMMON_H 1
4 /* CPU interfaces that are target independent. */
6 #include "hwaddr.h"
8 #ifndef NEED_CPU_H
9 #include "poison.h"
10 #endif
12 #include "bswap.h"
13 #include "qemu-queue.h"
15 #if !defined(CONFIG_USER_ONLY)
17 enum device_endian {
18 DEVICE_NATIVE_ENDIAN,
19 DEVICE_BIG_ENDIAN,
20 DEVICE_LITTLE_ENDIAN,
23 /* address in the RAM (different from a physical address) */
24 #if defined(CONFIG_XEN_BACKEND)
25 typedef uint64_t ram_addr_t;
26 # define RAM_ADDR_MAX UINT64_MAX
27 # define RAM_ADDR_FMT "%" PRIx64
28 #else
29 typedef uintptr_t ram_addr_t;
30 # define RAM_ADDR_MAX UINTPTR_MAX
31 # define RAM_ADDR_FMT "%" PRIxPTR
32 #endif
34 /* memory API */
36 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
37 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
39 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
40 /* This should only be used for ram local to a device. */
41 void *qemu_get_ram_ptr(ram_addr_t addr);
42 void qemu_put_ram_ptr(void *addr);
43 /* This should not be used by devices. */
44 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
45 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
46 void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
48 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
49 int len, int is_write);
50 static inline void cpu_physical_memory_read(hwaddr addr,
51 void *buf, int len)
53 cpu_physical_memory_rw(addr, buf, len, 0);
55 static inline void cpu_physical_memory_write(hwaddr addr,
56 const void *buf, int len)
58 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
60 void *cpu_physical_memory_map(hwaddr addr,
61 hwaddr *plen,
62 int is_write);
63 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
64 int is_write, hwaddr access_len);
65 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
67 bool cpu_physical_memory_is_io(hwaddr phys_addr);
69 /* Coalesced MMIO regions are areas where write operations can be reordered.
70 * This usually implies that write operations are side-effect free. This allows
71 * batching which can make a major impact on performance when using
72 * virtualization.
74 void qemu_flush_coalesced_mmio_buffer(void);
76 uint32_t ldub_phys(hwaddr addr);
77 uint32_t lduw_le_phys(hwaddr addr);
78 uint32_t lduw_be_phys(hwaddr addr);
79 uint32_t ldl_le_phys(hwaddr addr);
80 uint32_t ldl_be_phys(hwaddr addr);
81 uint64_t ldq_le_phys(hwaddr addr);
82 uint64_t ldq_be_phys(hwaddr addr);
83 void stb_phys(hwaddr addr, uint32_t val);
84 void stw_le_phys(hwaddr addr, uint32_t val);
85 void stw_be_phys(hwaddr addr, uint32_t val);
86 void stl_le_phys(hwaddr addr, uint32_t val);
87 void stl_be_phys(hwaddr addr, uint32_t val);
88 void stq_le_phys(hwaddr addr, uint64_t val);
89 void stq_be_phys(hwaddr addr, uint64_t val);
91 #ifdef NEED_CPU_H
92 uint32_t lduw_phys(hwaddr addr);
93 uint32_t ldl_phys(hwaddr addr);
94 uint64_t ldq_phys(hwaddr addr);
95 void stl_phys_notdirty(hwaddr addr, uint32_t val);
96 void stq_phys_notdirty(hwaddr addr, uint64_t val);
97 void stw_phys(hwaddr addr, uint32_t val);
98 void stl_phys(hwaddr addr, uint32_t val);
99 void stq_phys(hwaddr addr, uint64_t val);
100 #endif
102 void cpu_physical_memory_write_rom(hwaddr addr,
103 const uint8_t *buf, int len);
105 extern struct MemoryRegion io_mem_ram;
106 extern struct MemoryRegion io_mem_rom;
107 extern struct MemoryRegion io_mem_unassigned;
108 extern struct MemoryRegion io_mem_notdirty;
110 #endif
112 #endif /* !CPU_COMMON_H */