hw/timer/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "qemu/timer.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/timer/mc146818rtc.h"
  28 #include "qapi/visitor.h"
  29
  30 #ifdef TARGET_I386
  31 #include "hw/i386/apic.h"
  32 #endif
  33
  34 //#define DEBUG_CMOS
  35 //#define DEBUG_COALESCED
  36
  37 #ifdef DEBUG_CMOS
  38 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  39 #else
  40 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  41 #endif
  42
  43 #ifdef DEBUG_COALESCED
  44 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  45 #else
  46 # define DPRINTF_C(format, ...)      do { } while (0)
  47 #endif
  48
  49 #define NSEC_PER_SEC    1000000000LL
  50 #define SEC_PER_MIN     60
  51 #define MIN_PER_HOUR    60
  52 #define SEC_PER_HOUR    3600
  53 #define HOUR_PER_DAY    24
  54 #define SEC_PER_DAY     86400
  55
  56 #define RTC_REINJECT_ON_ACK_COUNT 20
  57 #define RTC_CLOCK_RATE            32768
  58 #define UIP_HOLD_LENGTH           (8 * NSEC_PER_SEC / 32768)
  59
  60 typedef struct RTCState {
  61     ISADevice dev;
  62     MemoryRegion io;
  63     uint8_t cmos_data[128];
  64     uint8_t cmos_index;
  65     int32_t base_year;
  66     uint64_t base_rtc;
  67     uint64_t last_update;
  68     int64_t offset;
  69     qemu_irq irq;
  70     qemu_irq sqw_irq;
  71     int it_shift;
  72     /* periodic timer */
  73     QEMUTimer *periodic_timer;
  74     int64_t next_periodic_time;
  75     /* update-ended timer */
  76     QEMUTimer *update_timer;
  77     uint64_t next_alarm_time;
  78     uint16_t irq_reinject_on_ack_count;
  79     uint32_t irq_coalesced;
  80     uint32_t period;
  81     QEMUTimer *coalesced_timer;
  82     Notifier clock_reset_notifier;
  83     LostTickPolicy lost_tick_policy;
  84     Notifier suspend_notifier;
  85 } RTCState;
  86
  87 static void rtc_set_time(RTCState *s);
  88 static void rtc_update_time(RTCState *s);
  89 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  90 static inline int rtc_from_bcd(RTCState *s, int a);
  91 static uint64_t get_next_alarm(RTCState *s);
  92
  93 static inline bool rtc_running(RTCState *s)
  94 {
  95     return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
  96             (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
  97 }
  98
  99 static uint64_t get_guest_rtc_ns(RTCState *s)
 100 {
 101     uint64_t guest_rtc;
 102     uint64_t guest_clock = qemu_get_clock_ns(rtc_clock);
 103
 104     guest_rtc = s->base_rtc * NSEC_PER_SEC
 105                  + guest_clock - s->last_update + s->offset;
 106     return guest_rtc;
 107 }
 108
 109 #ifdef TARGET_I386
 110 static void rtc_coalesced_timer_update(RTCState *s)
 111 {
 112     if (s->irq_coalesced == 0) {
 113         qemu_del_timer(s->coalesced_timer);
 114     } else {
 115         /* divide each RTC interval to 2 - 8 smaller intervals */
 116         int c = MIN(s->irq_coalesced, 7) + 1;
 117         int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
 118             muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
 119         qemu_mod_timer(s->coalesced_timer, next_clock);
 120     }
 121 }
 122
 123 static void rtc_coalesced_timer(void *opaque)
 124 {
 125     RTCState *s = opaque;
 126
 127     if (s->irq_coalesced != 0) {
 128         apic_reset_irq_delivered();
 129         s->cmos_data[RTC_REG_C] |= 0xc0;
 130         DPRINTF_C("cmos: injecting from timer\n");
 131         qemu_irq_raise(s->irq);
 132         if (apic_get_irq_delivered()) {
 133             s->irq_coalesced--;
 134             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 135                       s->irq_coalesced);
 136         }
 137     }
 138
 139     rtc_coalesced_timer_update(s);
 140 }
 141 #endif
 142
 143 /* handle periodic timer */
 144 static void periodic_timer_update(RTCState *s, int64_t current_time)
 145 {
 146     int period_code, period;
 147     int64_t cur_clock, next_irq_clock;
 148
 149     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 150     if (period_code != 0
 151         && ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
 152             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 153         if (period_code <= 2)
 154             period_code += 7;
 155         /* period in 32 Khz cycles */
 156         period = 1 << (period_code - 1);
 157 #ifdef TARGET_I386
 158         if (period != s->period) {
 159             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 160             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 161         }
 162         s->period = period;
 163 #endif
 164         /* compute 32 khz clock */
 165         cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
 166         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 167         s->next_periodic_time =
 168             muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
 169         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 170     } else {
 171 #ifdef TARGET_I386
 172         s->irq_coalesced = 0;
 173 #endif
 174         qemu_del_timer(s->periodic_timer);
 175     }
 176 }
 177
 178 static void rtc_periodic_timer(void *opaque)
 179 {
 180     RTCState *s = opaque;
 181
 182     periodic_timer_update(s, s->next_periodic_time);
 183     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 184     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 185         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 186 #ifdef TARGET_I386
 187         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 188             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 189                 s->irq_reinject_on_ack_count = 0;
 190             apic_reset_irq_delivered();
 191             qemu_irq_raise(s->irq);
 192             if (!apic_get_irq_delivered()) {
 193                 s->irq_coalesced++;
 194                 rtc_coalesced_timer_update(s);
 195                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 196                           s->irq_coalesced);
 197             }
 198         } else
 199 #endif
 200         qemu_irq_raise(s->irq);
 201     }
 202     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 203         /* Not square wave at all but we don't want 2048Hz interrupts!
 204            Must be seen as a pulse.  */
 205         qemu_irq_raise(s->sqw_irq);
 206     }
 207 }
 208
 209 /* handle update-ended timer */
 210 static void check_update_timer(RTCState *s)
 211 {
 212     uint64_t next_update_time;
 213     uint64_t guest_nsec;
 214     int next_alarm_sec;
 215
 216     /* From the data sheet: "Holding the dividers in reset prevents
 217      * interrupts from operating, while setting the SET bit allows"
 218      * them to occur.  However, it will prevent an alarm interrupt
 219      * from occurring, because the time of day is not updated.
 220      */
 221     if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
 222         qemu_del_timer(s->update_timer);
 223         return;
 224     }
 225     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 226         (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 227         qemu_del_timer(s->update_timer);
 228         return;
 229     }
 230     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 231         (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
 232         qemu_del_timer(s->update_timer);
 233         return;
 234     }
 235
 236     guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 237     /* if UF is clear, reprogram to next second */
 238     next_update_time = qemu_get_clock_ns(rtc_clock)
 239         + NSEC_PER_SEC - guest_nsec;
 240
 241     /* Compute time of next alarm.  One second is already accounted
 242      * for in next_update_time.
 243      */
 244     next_alarm_sec = get_next_alarm(s);
 245     s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
 246
 247     if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
 248         /* UF is set, but AF is clear.  Program the timer to target
 249          * the alarm time.  */
 250         next_update_time = s->next_alarm_time;
 251     }
 252     if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) {
 253         qemu_mod_timer(s->update_timer, next_update_time);
 254     }
 255 }
 256
 257 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
 258 {
 259     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 260         hour %= 12;
 261         if (s->cmos_data[RTC_HOURS] & 0x80) {
 262             hour += 12;
 263         }
 264     }
 265     return hour;
 266 }
 267
 268 static uint64_t get_next_alarm(RTCState *s)
 269 {
 270     int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
 271     int32_t hour, min, sec;
 272
 273     rtc_update_time(s);
 274
 275     alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
 276     alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
 277     alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
 278     alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
 279
 280     cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 281     cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 282     cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
 283     cur_hour = convert_hour(s, cur_hour);
 284
 285     if (alarm_hour == -1) {
 286         alarm_hour = cur_hour;
 287         if (alarm_min == -1) {
 288             alarm_min = cur_min;
 289             if (alarm_sec == -1) {
 290                 alarm_sec = cur_sec + 1;
 291             } else if (cur_sec > alarm_sec) {
 292                 alarm_min++;
 293             }
 294         } else if (cur_min == alarm_min) {
 295             if (alarm_sec == -1) {
 296                 alarm_sec = cur_sec + 1;
 297             } else {
 298                 if (cur_sec > alarm_sec) {
 299                     alarm_hour++;
 300                 }
 301             }
 302             if (alarm_sec == SEC_PER_MIN) {
 303                 /* wrap to next hour, minutes is not in don't care mode */
 304                 alarm_sec = 0;
 305                 alarm_hour++;
 306             }
 307         } else if (cur_min > alarm_min) {
 308             alarm_hour++;
 309         }
 310     } else if (cur_hour == alarm_hour) {
 311         if (alarm_min == -1) {
 312             alarm_min = cur_min;
 313             if (alarm_sec == -1) {
 314                 alarm_sec = cur_sec + 1;
 315             } else if (cur_sec > alarm_sec) {
 316                 alarm_min++;
 317             }
 318
 319             if (alarm_sec == SEC_PER_MIN) {
 320                 alarm_sec = 0;
 321                 alarm_min++;
 322             }
 323             /* wrap to next day, hour is not in don't care mode */
 324             alarm_min %= MIN_PER_HOUR;
 325         } else if (cur_min == alarm_min) {
 326             if (alarm_sec == -1) {
 327                 alarm_sec = cur_sec + 1;
 328             }
 329             /* wrap to next day, hours+minutes not in don't care mode */
 330             alarm_sec %= SEC_PER_MIN;
 331         }
 332     }
 333
 334     /* values that are still don't care fire at the next min/sec */
 335     if (alarm_min == -1) {
 336         alarm_min = 0;
 337     }
 338     if (alarm_sec == -1) {
 339         alarm_sec = 0;
 340     }
 341
 342     /* keep values in range */
 343     if (alarm_sec == SEC_PER_MIN) {
 344         alarm_sec = 0;
 345         alarm_min++;
 346     }
 347     if (alarm_min == MIN_PER_HOUR) {
 348         alarm_min = 0;
 349         alarm_hour++;
 350     }
 351     alarm_hour %= HOUR_PER_DAY;
 352
 353     hour = alarm_hour - cur_hour;
 354     min = hour * MIN_PER_HOUR + alarm_min - cur_min;
 355     sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
 356     return sec <= 0 ? sec + SEC_PER_DAY : sec;
 357 }
 358
 359 static void rtc_update_timer(void *opaque)
 360 {
 361     RTCState *s = opaque;
 362     int32_t irqs = REG_C_UF;
 363     int32_t new_irqs;
 364
 365     assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
 366
 367     /* UIP might have been latched, update time and clear it.  */
 368     rtc_update_time(s);
 369     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 370
 371     if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {
 372         irqs |= REG_C_AF;
 373         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 374             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 375         }
 376     }
 377
 378     new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
 379     s->cmos_data[RTC_REG_C] |= irqs;
 380     if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
 381         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 382         qemu_irq_raise(s->irq);
 383     }
 384     check_update_timer(s);
 385 }
 386
 387 static void cmos_ioport_write(void *opaque, hwaddr addr,
 388                               uint64_t data, unsigned size)
 389 {
 390     RTCState *s = opaque;
 391
 392     if ((addr & 1) == 0) {
 393         s->cmos_index = data & 0x7f;
 394     } else {
 395         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 396                      s->cmos_index, data);
 397         switch(s->cmos_index) {
 398         case RTC_SECONDS_ALARM:
 399         case RTC_MINUTES_ALARM:
 400         case RTC_HOURS_ALARM:
 401             s->cmos_data[s->cmos_index] = data;
 402             check_update_timer(s);
 403             break;
 404         case RTC_IBM_PS2_CENTURY_BYTE:
 405             s->cmos_index = RTC_CENTURY;
 406             /* fall through */
 407         case RTC_CENTURY:
 408         case RTC_SECONDS:
 409         case RTC_MINUTES:
 410         case RTC_HOURS:
 411         case RTC_DAY_OF_WEEK:
 412         case RTC_DAY_OF_MONTH:
 413         case RTC_MONTH:
 414         case RTC_YEAR:
 415             s->cmos_data[s->cmos_index] = data;
 416             /* if in set mode, do not update the time */
 417             if (rtc_running(s)) {
 418                 rtc_set_time(s);
 419                 check_update_timer(s);
 420             }
 421             break;
 422         case RTC_REG_A:
 423             if ((data & 0x60) == 0x60) {
 424                 if (rtc_running(s)) {
 425                     rtc_update_time(s);
 426                 }
 427                 /* What happens to UIP when divider reset is enabled is
 428                  * unclear from the datasheet.  Shouldn't matter much
 429                  * though.
 430                  */
 431                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 432             } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
 433                     (data & 0x70)  <= 0x20) {
 434                 /* when the divider reset is removed, the first update cycle
 435                  * begins one-half second later*/
 436                 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 437                     s->offset = 500000000;
 438                     rtc_set_time(s);
 439                 }
 440                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 441             }
 442             /* UIP bit is read only */
 443             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 444                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 445             periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
 446             check_update_timer(s);
 447             break;
 448         case RTC_REG_B:
 449             if (data & REG_B_SET) {
 450                 /* update cmos to when the rtc was stopping */
 451                 if (rtc_running(s)) {
 452                     rtc_update_time(s);
 453                 }
 454                 /* set mode: reset UIP mode */
 455                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 456                 data &= ~REG_B_UIE;
 457             } else {
 458                 /* if disabling set mode, update the time */
 459                 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 460                     (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
 461                     s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC;
 462                     rtc_set_time(s);
 463                 }
 464             }
 465             /* if an interrupt flag is already set when the interrupt
 466              * becomes enabled, raise an interrupt immediately.  */
 467             if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
 468                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 469                 qemu_irq_raise(s->irq);
 470             } else {
 471                 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
 472                 qemu_irq_lower(s->irq);
 473             }
 474             s->cmos_data[RTC_REG_B] = data;
 475             periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));
 476             check_update_timer(s);
 477             break;
 478         case RTC_REG_C:
 479         case RTC_REG_D:
 480             /* cannot write to them */
 481             break;
 482         default:
 483             s->cmos_data[s->cmos_index] = data;
 484             break;
 485         }
 486     }
 487 }
 488
 489 static inline int rtc_to_bcd(RTCState *s, int a)
 490 {
 491     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 492         return a;
 493     } else {
 494         return ((a / 10) << 4) | (a % 10);
 495     }
 496 }
 497
 498 static inline int rtc_from_bcd(RTCState *s, int a)
 499 {
 500     if ((a & 0xc0) == 0xc0) {
 501         return -1;
 502     }
 503     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 504         return a;
 505     } else {
 506         return ((a >> 4) * 10) + (a & 0x0f);
 507     }
 508 }
 509
 510 static void rtc_get_time(RTCState *s, struct tm *tm)
 511 {
 512     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 513     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 514     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 515     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 516         tm->tm_hour %= 12;
 517         if (s->cmos_data[RTC_HOURS] & 0x80) {
 518             tm->tm_hour += 12;
 519         }
 520     }
 521     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 522     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 523     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 524     tm->tm_year =
 525         rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
 526         rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
 527 }
 528
 529 static void rtc_set_time(RTCState *s)
 530 {
 531     struct tm tm;
 532
 533     rtc_get_time(s, &tm);
 534     s->base_rtc = mktimegm(&tm);
 535     s->last_update = qemu_get_clock_ns(rtc_clock);
 536
 537     rtc_change_mon_event(&tm);
 538 }
 539
 540 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
 541 {
 542     int year;
 543
 544     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 545     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 546     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 547         /* 24 hour format */
 548         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 549     } else {
 550         /* 12 hour format */
 551         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 552         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 553         if (tm->tm_hour >= 12)
 554             s->cmos_data[RTC_HOURS] |= 0x80;
 555     }
 556     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 557     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 558     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 559     year = tm->tm_year + 1900 - s->base_year;
 560     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
 561     s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
 562 }
 563
 564 static void rtc_update_time(RTCState *s)
 565 {
 566     struct tm ret;
 567     time_t guest_sec;
 568     int64_t guest_nsec;
 569
 570     guest_nsec = get_guest_rtc_ns(s);
 571     guest_sec = guest_nsec / NSEC_PER_SEC;
 572     gmtime_r(&guest_sec, &ret);
 573
 574     /* Is SET flag of Register B disabled? */
 575     if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
 576         rtc_set_cmos(s, &ret);
 577     }
 578 }
 579
 580 static int update_in_progress(RTCState *s)
 581 {
 582     int64_t guest_nsec;
 583
 584     if (!rtc_running(s)) {
 585         return 0;
 586     }
 587     if (qemu_timer_pending(s->update_timer)) {
 588         int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer);
 589         /* Latch UIP until the timer expires.  */
 590         if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {
 591             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 592             return 1;
 593         }
 594     }
 595
 596     guest_nsec = get_guest_rtc_ns(s);
 597     /* UIP bit will be set at last 244us of every second. */
 598     if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) {
 599         return 1;
 600     }
 601     return 0;
 602 }
 603
 604 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
 605                                  unsigned size)
 606 {
 607     RTCState *s = opaque;
 608     int ret;
 609     if ((addr & 1) == 0) {
 610         return 0xff;
 611     } else {
 612         switch(s->cmos_index) {
 613         case RTC_IBM_PS2_CENTURY_BYTE:
 614             s->cmos_index = RTC_CENTURY;
 615             /* fall through */
 616         case RTC_CENTURY:
 617         case RTC_SECONDS:
 618         case RTC_MINUTES:
 619         case RTC_HOURS:
 620         case RTC_DAY_OF_WEEK:
 621         case RTC_DAY_OF_MONTH:
 622         case RTC_MONTH:
 623         case RTC_YEAR:
 624             /* if not in set mode, calibrate cmos before
 625              * reading*/
 626             if (rtc_running(s)) {
 627                 rtc_update_time(s);
 628             }
 629             ret = s->cmos_data[s->cmos_index];
 630             break;
 631         case RTC_REG_A:
 632             if (update_in_progress(s)) {
 633                 s->cmos_data[s->cmos_index] |= REG_A_UIP;
 634             } else {
 635                 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
 636             }
 637             ret = s->cmos_data[s->cmos_index];
 638             break;
 639         case RTC_REG_C:
 640             ret = s->cmos_data[s->cmos_index];
 641             qemu_irq_lower(s->irq);
 642             s->cmos_data[RTC_REG_C] = 0x00;
 643             if (ret & (REG_C_UF | REG_C_AF)) {
 644                 check_update_timer(s);
 645             }
 646 #ifdef TARGET_I386
 647             if(s->irq_coalesced &&
 648                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 649                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 650                 s->irq_reinject_on_ack_count++;
 651                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 652                 apic_reset_irq_delivered();
 653                 DPRINTF_C("cmos: injecting on ack\n");
 654                 qemu_irq_raise(s->irq);
 655                 if (apic_get_irq_delivered()) {
 656                     s->irq_coalesced--;
 657                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 658                               s->irq_coalesced);
 659                 }
 660             }
 661 #endif
 662             break;
 663         default:
 664             ret = s->cmos_data[s->cmos_index];
 665             break;
 666         }
 667         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 668                      s->cmos_index, ret);
 669         return ret;
 670     }
 671 }
 672
 673 void rtc_set_memory(ISADevice *dev, int addr, int val)
 674 {
 675     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 676     if (addr >= 0 && addr <= 127)
 677         s->cmos_data[addr] = val;
 678 }
 679
 680 static void rtc_set_date_from_host(ISADevice *dev)
 681 {
 682     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 683     struct tm tm;
 684
 685     qemu_get_timedate(&tm, 0);
 686
 687     s->base_rtc = mktimegm(&tm);
 688     s->last_update = qemu_get_clock_ns(rtc_clock);
 689     s->offset = 0;
 690
 691     /* set the CMOS date */
 692     rtc_set_cmos(s, &tm);
 693 }
 694
 695 static int rtc_post_load(void *opaque, int version_id)
 696 {
 697     RTCState *s = opaque;
 698
 699     if (version_id <= 2) {
 700         rtc_set_time(s);
 701         s->offset = 0;
 702         check_update_timer(s);
 703     }
 704
 705 #ifdef TARGET_I386
 706     if (version_id >= 2) {
 707         if (s->lost_tick_policy == LOST_TICK_SLEW) {
 708             rtc_coalesced_timer_update(s);
 709         }
 710     }
 711 #endif
 712     return 0;
 713 }
 714
 715 static const VMStateDescription vmstate_rtc = {
 716     .name = "mc146818rtc",
 717     .version_id = 3,
 718     .minimum_version_id = 1,
 719     .minimum_version_id_old = 1,
 720     .post_load = rtc_post_load,
 721     .fields      = (VMStateField []) {
 722         VMSTATE_BUFFER(cmos_data, RTCState),
 723         VMSTATE_UINT8(cmos_index, RTCState),
 724         VMSTATE_UNUSED(7*4),
 725         VMSTATE_TIMER(periodic_timer, RTCState),
 726         VMSTATE_INT64(next_periodic_time, RTCState),
 727         VMSTATE_UNUSED(3*8),
 728         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 729         VMSTATE_UINT32_V(period, RTCState, 2),
 730         VMSTATE_UINT64_V(base_rtc, RTCState, 3),
 731         VMSTATE_UINT64_V(last_update, RTCState, 3),
 732         VMSTATE_INT64_V(offset, RTCState, 3),
 733         VMSTATE_TIMER_V(update_timer, RTCState, 3),
 734         VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
 735         VMSTATE_END_OF_LIST()
 736     }
 737 };
 738
 739 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 740 {
 741     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 742     int64_t now = *(int64_t *)data;
 743
 744     rtc_set_date_from_host(&s->dev);
 745     periodic_timer_update(s, now);
 746     check_update_timer(s);
 747 #ifdef TARGET_I386
 748     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 749         rtc_coalesced_timer_update(s);
 750     }
 751 #endif
 752 }
 753
 754 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 755    BIOS will read it and start S3 resume at POST Entry */
 756 static void rtc_notify_suspend(Notifier *notifier, void *data)
 757 {
 758     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 759     rtc_set_memory(&s->dev, 0xF, 0xFE);
 760 }
 761
 762 static void rtc_reset(void *opaque)
 763 {
 764     RTCState *s = opaque;
 765
 766     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 767     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 768     check_update_timer(s);
 769
 770     qemu_irq_lower(s->irq);
 771
 772 #ifdef TARGET_I386
 773     if (s->lost_tick_policy == LOST_TICK_SLEW) {
 774         s->irq_coalesced = 0;
 775     }
 776 #endif
 777 }
 778
 779 static const MemoryRegionOps cmos_ops = {
 780     .read = cmos_ioport_read,
 781     .write = cmos_ioport_write,
 782     .impl = {
 783         .min_access_size = 1,
 784         .max_access_size = 1,
 785     },
 786     .endianness = DEVICE_LITTLE_ENDIAN,
 787 };
 788
 789 static void rtc_get_date(Object *obj, Visitor *v, void *opaque,
 790                          const char *name, Error **errp)
 791 {
 792     ISADevice *isa = ISA_DEVICE(obj);
 793     RTCState *s = DO_UPCAST(RTCState, dev, isa);
 794     struct tm current_tm;
 795
 796     rtc_update_time(s);
 797     rtc_get_time(s, &current_tm);
 798     visit_start_struct(v, NULL, "struct tm", name, 0, errp);
 799     visit_type_int32(v, &current_tm.tm_year, "tm_year", errp);
 800     visit_type_int32(v, &current_tm.tm_mon, "tm_mon", errp);
 801     visit_type_int32(v, &current_tm.tm_mday, "tm_mday", errp);
 802     visit_type_int32(v, &current_tm.tm_hour, "tm_hour", errp);
 803     visit_type_int32(v, &current_tm.tm_min, "tm_min", errp);
 804     visit_type_int32(v, &current_tm.tm_sec, "tm_sec", errp);
 805     visit_end_struct(v, errp);
 806 }
 807
 808 static int rtc_initfn(ISADevice *dev)
 809 {
 810     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 811     int base = 0x70;
 812
 813     s->cmos_data[RTC_REG_A] = 0x26;
 814     s->cmos_data[RTC_REG_B] = 0x02;
 815     s->cmos_data[RTC_REG_C] = 0x00;
 816     s->cmos_data[RTC_REG_D] = 0x80;
 817
 818     /* This is for historical reasons.  The default base year qdev property
 819      * was set to 2000 for most machine types before the century byte was
 820      * implemented.
 821      *
 822      * This if statement means that the century byte will be always 0
 823      * (at least until 2079...) for base_year = 1980, but will be set
 824      * correctly for base_year = 2000.
 825      */
 826     if (s->base_year == 2000) {
 827         s->base_year = 0;
 828     }
 829
 830     rtc_set_date_from_host(dev);
 831
 832 #ifdef TARGET_I386
 833     switch (s->lost_tick_policy) {
 834     case LOST_TICK_SLEW:
 835         s->coalesced_timer =
 836             qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
 837         break;
 838     case LOST_TICK_DISCARD:
 839         break;
 840     default:
 841         return -EINVAL;
 842     }
 843 #endif
 844
 845     s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
 846     s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s);
 847     check_update_timer(s);
 848
 849     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 850     qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
 851
 852     s->suspend_notifier.notify = rtc_notify_suspend;
 853     qemu_register_suspend_notifier(&s->suspend_notifier);
 854
 855     memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
 856     isa_register_ioport(dev, &s->io, base);
 857
 858     qdev_set_legacy_instance_id(&dev->qdev, base, 3);
 859     qemu_register_reset(rtc_reset, s);
 860
 861     object_property_add(OBJECT(s), "date", "struct tm",
 862                         rtc_get_date, NULL, NULL, s, NULL);
 863
 864     return 0;
 865 }
 866
 867 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 868 {
 869     ISADevice *dev;
 870     RTCState *s;
 871
 872     dev = isa_create(bus, "mc146818rtc");
 873     s = DO_UPCAST(RTCState, dev, dev);
 874     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 875     qdev_init_nofail(&dev->qdev);
 876     if (intercept_irq) {
 877         s->irq = intercept_irq;
 878     } else {
 879         isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
 880     }
 881     return dev;
 882 }
 883
 884 static Property mc146818rtc_properties[] = {
 885     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 886     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 887                                lost_tick_policy, LOST_TICK_DISCARD),
 888     DEFINE_PROP_END_OF_LIST(),
 889 };
 890
 891 static void rtc_class_initfn(ObjectClass *klass, void *data)
 892 {
 893     DeviceClass *dc = DEVICE_CLASS(klass);
 894     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 895     ic->init = rtc_initfn;
 896     dc->no_user = 1;
 897     dc->vmsd = &vmstate_rtc;
 898     dc->props = mc146818rtc_properties;
 899 }
 900
 901 static const TypeInfo mc146818rtc_info = {
 902     .name          = "mc146818rtc",
 903     .parent        = TYPE_ISA_DEVICE,
 904     .instance_size = sizeof(RTCState),
 905     .class_init    = rtc_class_initfn,
 906 };
 907
 908 static void mc146818rtc_register_types(void)
 909 {
 910     type_register_static(&mc146818rtc_info);
 911 }
 912
 913 type_init(mc146818rtc_register_types)