hw/lm32_uart.c

   1 /*
   2  *  QEMU model of the LatticeMico32 UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32uart.pdf
  22  */
  23
  24
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "trace.h"
  28 #include "char/char.h"
  29 #include "qemu/error-report.h"
  30
  31 enum {
  32     R_RXTX = 0,
  33     R_IER,
  34     R_IIR,
  35     R_LCR,
  36     R_MCR,
  37     R_LSR,
  38     R_MSR,
  39     R_DIV,
  40     R_MAX
  41 };
  42
  43 enum {
  44     IER_RBRI = (1<<0),
  45     IER_THRI = (1<<1),
  46     IER_RLSI = (1<<2),
  47     IER_MSI  = (1<<3),
  48 };
  49
  50 enum {
  51     IIR_STAT = (1<<0),
  52     IIR_ID0  = (1<<1),
  53     IIR_ID1  = (1<<2),
  54 };
  55
  56 enum {
  57     LCR_WLS0 = (1<<0),
  58     LCR_WLS1 = (1<<1),
  59     LCR_STB  = (1<<2),
  60     LCR_PEN  = (1<<3),
  61     LCR_EPS  = (1<<4),
  62     LCR_SP   = (1<<5),
  63     LCR_SB   = (1<<6),
  64 };
  65
  66 enum {
  67     MCR_DTR  = (1<<0),
  68     MCR_RTS  = (1<<1),
  69 };
  70
  71 enum {
  72     LSR_DR   = (1<<0),
  73     LSR_OE   = (1<<1),
  74     LSR_PE   = (1<<2),
  75     LSR_FE   = (1<<3),
  76     LSR_BI   = (1<<4),
  77     LSR_THRE = (1<<5),
  78     LSR_TEMT = (1<<6),
  79 };
  80
  81 enum {
  82     MSR_DCTS = (1<<0),
  83     MSR_DDSR = (1<<1),
  84     MSR_TERI = (1<<2),
  85     MSR_DDCD = (1<<3),
  86     MSR_CTS  = (1<<4),
  87     MSR_DSR  = (1<<5),
  88     MSR_RI   = (1<<6),
  89     MSR_DCD  = (1<<7),
  90 };
  91
  92 struct LM32UartState {
  93     SysBusDevice busdev;
  94     MemoryRegion iomem;
  95     CharDriverState *chr;
  96     qemu_irq irq;
  97
  98     uint32_t regs[R_MAX];
  99 };
 100 typedef struct LM32UartState LM32UartState;
 101
 102 static void uart_update_irq(LM32UartState *s)
 103 {
 104     unsigned int irq;
 105
 106     if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 107             && (s->regs[R_IER] & IER_RLSI)) {
 108         irq = 1;
 109         s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 110     } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 111         irq = 1;
 112         s->regs[R_IIR] = IIR_ID1;
 113     } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 114         irq = 1;
 115         s->regs[R_IIR] = IIR_ID0;
 116     } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 117         irq = 1;
 118         s->regs[R_IIR] = 0;
 119     } else {
 120         irq = 0;
 121         s->regs[R_IIR] = IIR_STAT;
 122     }
 123
 124     trace_lm32_uart_irq_state(irq);
 125     qemu_set_irq(s->irq, irq);
 126 }
 127
 128 static uint64_t uart_read(void *opaque, hwaddr addr,
 129                           unsigned size)
 130 {
 131     LM32UartState *s = opaque;
 132     uint32_t r = 0;
 133
 134     addr >>= 2;
 135     switch (addr) {
 136     case R_RXTX:
 137         r = s->regs[R_RXTX];
 138         s->regs[R_LSR] &= ~LSR_DR;
 139         uart_update_irq(s);
 140         break;
 141     case R_IIR:
 142     case R_LSR:
 143     case R_MSR:
 144         r = s->regs[addr];
 145         break;
 146     case R_IER:
 147     case R_LCR:
 148     case R_MCR:
 149     case R_DIV:
 150         error_report("lm32_uart: read access to write only register 0x"
 151                 TARGET_FMT_plx, addr << 2);
 152         break;
 153     default:
 154         error_report("lm32_uart: read access to unknown register 0x"
 155                 TARGET_FMT_plx, addr << 2);
 156         break;
 157     }
 158
 159     trace_lm32_uart_memory_read(addr << 2, r);
 160     return r;
 161 }
 162
 163 static void uart_write(void *opaque, hwaddr addr,
 164                        uint64_t value, unsigned size)
 165 {
 166     LM32UartState *s = opaque;
 167     unsigned char ch = value;
 168
 169     trace_lm32_uart_memory_write(addr, value);
 170
 171     addr >>= 2;
 172     switch (addr) {
 173     case R_RXTX:
 174         if (s->chr) {
 175             qemu_chr_fe_write(s->chr, &ch, 1);
 176         }
 177         break;
 178     case R_IER:
 179     case R_LCR:
 180     case R_MCR:
 181     case R_DIV:
 182         s->regs[addr] = value;
 183         break;
 184     case R_IIR:
 185     case R_LSR:
 186     case R_MSR:
 187         error_report("lm32_uart: write access to read only register 0x"
 188                 TARGET_FMT_plx, addr << 2);
 189         break;
 190     default:
 191         error_report("lm32_uart: write access to unknown register 0x"
 192                 TARGET_FMT_plx, addr << 2);
 193         break;
 194     }
 195     uart_update_irq(s);
 196 }
 197
 198 static const MemoryRegionOps uart_ops = {
 199     .read = uart_read,
 200     .write = uart_write,
 201     .endianness = DEVICE_NATIVE_ENDIAN,
 202     .valid = {
 203         .min_access_size = 4,
 204         .max_access_size = 4,
 205     },
 206 };
 207
 208 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 209 {
 210     LM32UartState *s = opaque;
 211
 212     if (s->regs[R_LSR] & LSR_DR) {
 213         s->regs[R_LSR] |= LSR_OE;
 214     }
 215
 216     s->regs[R_LSR] |= LSR_DR;
 217     s->regs[R_RXTX] = *buf;
 218
 219     uart_update_irq(s);
 220 }
 221
 222 static int uart_can_rx(void *opaque)
 223 {
 224     LM32UartState *s = opaque;
 225
 226     return !(s->regs[R_LSR] & LSR_DR);
 227 }
 228
 229 static void uart_event(void *opaque, int event)
 230 {
 231 }
 232
 233 static void uart_reset(DeviceState *d)
 234 {
 235     LM32UartState *s = container_of(d, LM32UartState, busdev.qdev);
 236     int i;
 237
 238     for (i = 0; i < R_MAX; i++) {
 239         s->regs[i] = 0;
 240     }
 241
 242     /* defaults */
 243     s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 244 }
 245
 246 static int lm32_uart_init(SysBusDevice *dev)
 247 {
 248     LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
 249
 250     sysbus_init_irq(dev, &s->irq);
 251
 252     memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
 253     sysbus_init_mmio(dev, &s->iomem);
 254
 255     s->chr = qemu_char_get_next_serial();
 256     if (s->chr) {
 257         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 258     }
 259
 260     return 0;
 261 }
 262
 263 static const VMStateDescription vmstate_lm32_uart = {
 264     .name = "lm32-uart",
 265     .version_id = 1,
 266     .minimum_version_id = 1,
 267     .minimum_version_id_old = 1,
 268     .fields      = (VMStateField[]) {
 269         VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 270         VMSTATE_END_OF_LIST()
 271     }
 272 };
 273
 274 static void lm32_uart_class_init(ObjectClass *klass, void *data)
 275 {
 276     DeviceClass *dc = DEVICE_CLASS(klass);
 277     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 278
 279     k->init = lm32_uart_init;
 280     dc->reset = uart_reset;
 281     dc->vmsd = &vmstate_lm32_uart;
 282 }
 283
 284 static const TypeInfo lm32_uart_info = {
 285     .name          = "lm32-uart",
 286     .parent        = TYPE_SYS_BUS_DEVICE,
 287     .instance_size = sizeof(LM32UartState),
 288     .class_init    = lm32_uart_class_init,
 289 };
 290
 291 static void lm32_uart_register_types(void)
 292 {
 293     type_register_static(&lm32_uart_info);
 294 }
 295
 296 type_init(lm32_uart_register_types)