stubs: Add a vmstate_dummy struct for CONFIG_USER_ONLY
[qemu/agraf.git] / hw / omap_lcdc.c
blobc426f3a13af0ca7ff87067dfd7ab45e9dd5e7c5a
1 /*
2 * OMAP LCD controller.
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "hw/hw.h"
20 #include "ui/console.h"
21 #include "hw/omap.h"
22 #include "hw/framebuffer.h"
23 #include "ui/pixel_ops.h"
25 struct omap_lcd_panel_s {
26 MemoryRegion *sysmem;
27 MemoryRegion iomem;
28 qemu_irq irq;
29 DisplayState *state;
31 int plm;
32 int tft;
33 int mono;
34 int enable;
35 int width;
36 int height;
37 int interrupts;
38 uint32_t timing[3];
39 uint32_t subpanel;
40 uint32_t ctrl;
42 struct omap_dma_lcd_channel_s *dma;
43 uint16_t palette[256];
44 int palette_done;
45 int frame_done;
46 int invalidate;
47 int sync_error;
50 static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
52 if (s->frame_done && (s->interrupts & 1)) {
53 qemu_irq_raise(s->irq);
54 return;
57 if (s->palette_done && (s->interrupts & 2)) {
58 qemu_irq_raise(s->irq);
59 return;
62 if (s->sync_error) {
63 qemu_irq_raise(s->irq);
64 return;
67 qemu_irq_lower(s->irq);
70 #define draw_line_func drawfn
72 #define DEPTH 8
73 #include "hw/omap_lcd_template.h"
74 #define DEPTH 15
75 #include "hw/omap_lcd_template.h"
76 #define DEPTH 16
77 #include "hw/omap_lcd_template.h"
78 #define DEPTH 32
79 #include "hw/omap_lcd_template.h"
81 static draw_line_func draw_line_table2[33] = {
82 [0 ... 32] = NULL,
83 [8] = draw_line2_8,
84 [15] = draw_line2_15,
85 [16] = draw_line2_16,
86 [32] = draw_line2_32,
87 }, draw_line_table4[33] = {
88 [0 ... 32] = NULL,
89 [8] = draw_line4_8,
90 [15] = draw_line4_15,
91 [16] = draw_line4_16,
92 [32] = draw_line4_32,
93 }, draw_line_table8[33] = {
94 [0 ... 32] = NULL,
95 [8] = draw_line8_8,
96 [15] = draw_line8_15,
97 [16] = draw_line8_16,
98 [32] = draw_line8_32,
99 }, draw_line_table12[33] = {
100 [0 ... 32] = NULL,
101 [8] = draw_line12_8,
102 [15] = draw_line12_15,
103 [16] = draw_line12_16,
104 [32] = draw_line12_32,
105 }, draw_line_table16[33] = {
106 [0 ... 32] = NULL,
107 [8] = draw_line16_8,
108 [15] = draw_line16_15,
109 [16] = draw_line16_16,
110 [32] = draw_line16_32,
113 static void omap_update_display(void *opaque)
115 struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
116 draw_line_func draw_line;
117 int size, height, first, last;
118 int width, linesize, step, bpp, frame_offset;
119 hwaddr frame_base;
121 if (!omap_lcd || omap_lcd->plm == 1 ||
122 !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
123 return;
125 frame_offset = 0;
126 if (omap_lcd->plm != 2) {
127 cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[
128 omap_lcd->dma->current_frame],
129 (void *)omap_lcd->palette, 0x200);
130 switch (omap_lcd->palette[0] >> 12 & 7) {
131 case 3 ... 7:
132 frame_offset += 0x200;
133 break;
134 default:
135 frame_offset += 0x20;
139 /* Colour depth */
140 switch ((omap_lcd->palette[0] >> 12) & 7) {
141 case 1:
142 draw_line = draw_line_table2[ds_get_bits_per_pixel(omap_lcd->state)];
143 bpp = 2;
144 break;
146 case 2:
147 draw_line = draw_line_table4[ds_get_bits_per_pixel(omap_lcd->state)];
148 bpp = 4;
149 break;
151 case 3:
152 draw_line = draw_line_table8[ds_get_bits_per_pixel(omap_lcd->state)];
153 bpp = 8;
154 break;
156 case 4 ... 7:
157 if (!omap_lcd->tft)
158 draw_line = draw_line_table12[ds_get_bits_per_pixel(omap_lcd->state)];
159 else
160 draw_line = draw_line_table16[ds_get_bits_per_pixel(omap_lcd->state)];
161 bpp = 16;
162 break;
164 default:
165 /* Unsupported at the moment. */
166 return;
169 /* Resolution */
170 width = omap_lcd->width;
171 if (width != ds_get_width(omap_lcd->state) ||
172 omap_lcd->height != ds_get_height(omap_lcd->state)) {
173 qemu_console_resize(omap_lcd->state,
174 omap_lcd->width, omap_lcd->height);
175 omap_lcd->invalidate = 1;
178 if (omap_lcd->dma->current_frame == 0)
179 size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top;
180 else
181 size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top;
183 if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) {
184 omap_lcd->sync_error = 1;
185 omap_lcd_interrupts(omap_lcd);
186 omap_lcd->enable = 0;
187 return;
190 /* Content */
191 frame_base = omap_lcd->dma->phys_framebuffer[
192 omap_lcd->dma->current_frame] + frame_offset;
193 omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
194 if (omap_lcd->dma->interrupts & 1)
195 qemu_irq_raise(omap_lcd->dma->irq);
196 if (omap_lcd->dma->dual)
197 omap_lcd->dma->current_frame ^= 1;
199 if (!ds_get_bits_per_pixel(omap_lcd->state))
200 return;
202 first = 0;
203 height = omap_lcd->height;
204 if (omap_lcd->subpanel & (1 << 31)) {
205 if (omap_lcd->subpanel & (1 << 29))
206 first = (omap_lcd->subpanel >> 16) & 0x3ff;
207 else
208 height = (omap_lcd->subpanel >> 16) & 0x3ff;
209 /* TODO: fill the rest of the panel with DPD */
212 step = width * bpp >> 3;
213 linesize = ds_get_linesize(omap_lcd->state);
214 framebuffer_update_display(omap_lcd->state, omap_lcd->sysmem,
215 frame_base, width, height,
216 step, linesize, 0,
217 omap_lcd->invalidate,
218 draw_line, omap_lcd->palette,
219 &first, &last);
220 if (first >= 0) {
221 dpy_gfx_update(omap_lcd->state, 0, first, width, last - first + 1);
223 omap_lcd->invalidate = 0;
226 static void omap_ppm_save(const char *filename, uint8_t *data,
227 int w, int h, int linesize, Error **errp)
229 FILE *f;
230 uint8_t *d, *d1;
231 unsigned int v;
232 int ret, y, x, bpp;
234 f = fopen(filename, "wb");
235 if (!f) {
236 error_setg(errp, "failed to open file '%s': %s", filename,
237 strerror(errno));
238 return;
240 ret = fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
241 if (ret < 0) {
242 goto write_err;
244 d1 = data;
245 bpp = linesize / w;
246 for (y = 0; y < h; y ++) {
247 d = d1;
248 for (x = 0; x < w; x ++) {
249 v = *(uint32_t *) d;
250 switch (bpp) {
251 case 2:
252 ret = fputc((v >> 8) & 0xf8, f);
253 if (ret == EOF) {
254 goto write_err;
256 ret = fputc((v >> 3) & 0xfc, f);
257 if (ret == EOF) {
258 goto write_err;
260 ret = fputc((v << 3) & 0xf8, f);
261 if (ret == EOF) {
262 goto write_err;
264 break;
265 case 3:
266 case 4:
267 default:
268 ret = fputc((v >> 16) & 0xff, f);
269 if (ret == EOF) {
270 goto write_err;
272 ret = fputc((v >> 8) & 0xff, f);
273 if (ret == EOF) {
274 goto write_err;
276 ret = fputc((v) & 0xff, f);
277 if (ret == EOF) {
278 goto write_err;
280 break;
282 d += bpp;
284 d1 += linesize;
286 out:
287 fclose(f);
288 return;
290 write_err:
291 error_setg(errp, "failed to write to file '%s': %s", filename,
292 strerror(errno));
293 unlink(filename);
294 goto out;
297 static void omap_screen_dump(void *opaque, const char *filename, bool cswitch,
298 Error **errp)
300 struct omap_lcd_panel_s *omap_lcd = opaque;
302 omap_update_display(opaque);
303 if (omap_lcd && ds_get_data(omap_lcd->state))
304 omap_ppm_save(filename, ds_get_data(omap_lcd->state),
305 omap_lcd->width, omap_lcd->height,
306 ds_get_linesize(omap_lcd->state), errp);
309 static void omap_invalidate_display(void *opaque) {
310 struct omap_lcd_panel_s *omap_lcd = opaque;
311 omap_lcd->invalidate = 1;
314 static void omap_lcd_update(struct omap_lcd_panel_s *s) {
315 if (!s->enable) {
316 s->dma->current_frame = -1;
317 s->sync_error = 0;
318 if (s->plm != 1)
319 s->frame_done = 1;
320 omap_lcd_interrupts(s);
321 return;
324 if (s->dma->current_frame == -1) {
325 s->frame_done = 0;
326 s->palette_done = 0;
327 s->dma->current_frame = 0;
330 if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
331 s->dma->src_f1_top) ||
332 !s->dma->mpu->port[
333 s->dma->src].addr_valid(s->dma->mpu,
334 s->dma->src_f1_bottom) ||
335 (s->dma->dual &&
336 (!s->dma->mpu->port[
337 s->dma->src].addr_valid(s->dma->mpu,
338 s->dma->src_f2_top) ||
339 !s->dma->mpu->port[
340 s->dma->src].addr_valid(s->dma->mpu,
341 s->dma->src_f2_bottom)))) {
342 s->dma->condition |= 1 << 2;
343 if (s->dma->interrupts & (1 << 1))
344 qemu_irq_raise(s->dma->irq);
345 s->enable = 0;
346 return;
349 s->dma->phys_framebuffer[0] = s->dma->src_f1_top;
350 s->dma->phys_framebuffer[1] = s->dma->src_f2_top;
352 if (s->plm != 2 && !s->palette_done) {
353 cpu_physical_memory_read(
354 s->dma->phys_framebuffer[s->dma->current_frame],
355 (void *)s->palette, 0x200);
356 s->palette_done = 1;
357 omap_lcd_interrupts(s);
361 static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
362 unsigned size)
364 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
366 switch (addr) {
367 case 0x00: /* LCD_CONTROL */
368 return (s->tft << 23) | (s->plm << 20) |
369 (s->tft << 7) | (s->interrupts << 3) |
370 (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34;
372 case 0x04: /* LCD_TIMING0 */
373 return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f;
375 case 0x08: /* LCD_TIMING1 */
376 return (s->timing[1] << 10) | (s->height - 1);
378 case 0x0c: /* LCD_TIMING2 */
379 return s->timing[2] | 0xfc000000;
381 case 0x10: /* LCD_STATUS */
382 return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done;
384 case 0x14: /* LCD_SUBPANEL */
385 return s->subpanel;
387 default:
388 break;
390 OMAP_BAD_REG(addr);
391 return 0;
394 static void omap_lcdc_write(void *opaque, hwaddr addr,
395 uint64_t value, unsigned size)
397 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
399 switch (addr) {
400 case 0x00: /* LCD_CONTROL */
401 s->plm = (value >> 20) & 3;
402 s->tft = (value >> 7) & 1;
403 s->interrupts = (value >> 3) & 3;
404 s->mono = (value >> 1) & 1;
405 s->ctrl = value & 0x01cff300;
406 if (s->enable != (value & 1)) {
407 s->enable = value & 1;
408 omap_lcd_update(s);
410 break;
412 case 0x04: /* LCD_TIMING0 */
413 s->timing[0] = value >> 10;
414 s->width = (value & 0x3ff) + 1;
415 break;
417 case 0x08: /* LCD_TIMING1 */
418 s->timing[1] = value >> 10;
419 s->height = (value & 0x3ff) + 1;
420 break;
422 case 0x0c: /* LCD_TIMING2 */
423 s->timing[2] = value;
424 break;
426 case 0x10: /* LCD_STATUS */
427 break;
429 case 0x14: /* LCD_SUBPANEL */
430 s->subpanel = value & 0xa1ffffff;
431 break;
433 default:
434 OMAP_BAD_REG(addr);
438 static const MemoryRegionOps omap_lcdc_ops = {
439 .read = omap_lcdc_read,
440 .write = omap_lcdc_write,
441 .endianness = DEVICE_NATIVE_ENDIAN,
444 void omap_lcdc_reset(struct omap_lcd_panel_s *s)
446 s->dma->current_frame = -1;
447 s->plm = 0;
448 s->tft = 0;
449 s->mono = 0;
450 s->enable = 0;
451 s->width = 0;
452 s->height = 0;
453 s->interrupts = 0;
454 s->timing[0] = 0;
455 s->timing[1] = 0;
456 s->timing[2] = 0;
457 s->subpanel = 0;
458 s->palette_done = 0;
459 s->frame_done = 0;
460 s->sync_error = 0;
461 s->invalidate = 1;
462 s->subpanel = 0;
463 s->ctrl = 0;
466 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
467 hwaddr base,
468 qemu_irq irq,
469 struct omap_dma_lcd_channel_s *dma,
470 omap_clk clk)
472 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
473 g_malloc0(sizeof(struct omap_lcd_panel_s));
475 s->irq = irq;
476 s->dma = dma;
477 s->sysmem = sysmem;
478 omap_lcdc_reset(s);
480 memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
481 memory_region_add_subregion(sysmem, base, &s->iomem);
483 s->state = graphic_console_init(omap_update_display,
484 omap_invalidate_display,
485 omap_screen_dump, NULL, s);
487 return s;