hw/xilinx_spi.c

   1 /*
   2  * QEMU model of the Xilinx SPI Controller
   3  *
   4  * Copyright (C) 2010 Edgar E. Iglesias.
   5  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
   6  * Copyright (C) 2012 PetaLogix
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "hw/sysbus.h"
  28 #include "sysemu/sysemu.h"
  29 #include "qemu/log.h"
  30 #include "qemu/fifo8.h"
  31
  32 #include "hw/ssi.h"
  33
  34 #ifdef XILINX_SPI_ERR_DEBUG
  35 #define DB_PRINT(...) do { \
  36     fprintf(stderr,  ": %s: ", __func__); \
  37     fprintf(stderr, ## __VA_ARGS__); \
  38     } while (0);
  39 #else
  40     #define DB_PRINT(...)
  41 #endif
  42
  43 #define R_DGIER     (0x1c / 4)
  44 #define R_DGIER_IE  (1 << 31)
  45
  46 #define R_IPISR     (0x20 / 4)
  47 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
  48 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
  49 #define IRQ_DRR_FULL         (1 << (31 - 27))
  50 #define IRQ_TX_FF_HALF_EMPTY (1 << 6)
  51 #define IRQ_DTR_UNDERRUN     (1 << 3)
  52 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
  53
  54 #define R_IPIER     (0x28 / 4)
  55 #define R_SRR       (0x40 / 4)
  56 #define R_SPICR     (0x60 / 4)
  57 #define R_SPICR_TXFF_RST     (1 << 5)
  58 #define R_SPICR_RXFF_RST     (1 << 6)
  59 #define R_SPICR_MTI          (1 << 8)
  60
  61 #define R_SPISR     (0x64 / 4)
  62 #define SR_TX_FULL    (1 << 3)
  63 #define SR_TX_EMPTY   (1 << 2)
  64 #define SR_RX_FULL    (1 << 1)
  65 #define SR_RX_EMPTY   (1 << 0)
  66
  67 #define R_SPIDTR    (0x68 / 4)
  68 #define R_SPIDRR    (0x6C / 4)
  69 #define R_SPISSR    (0x70 / 4)
  70 #define R_TX_FF_OCY (0x74 / 4)
  71 #define R_RX_FF_OCY (0x78 / 4)
  72 #define R_MAX       (0x7C / 4)
  73
  74 #define FIFO_CAPACITY 256
  75
  76 typedef struct XilinxSPI {
  77     SysBusDevice busdev;
  78     MemoryRegion mmio;
  79
  80     qemu_irq irq;
  81     int irqline;
  82
  83     uint8_t num_cs;
  84     qemu_irq *cs_lines;
  85
  86     SSIBus *spi;
  87
  88     Fifo8 rx_fifo;
  89     Fifo8 tx_fifo;
  90
  91     uint32_t regs[R_MAX];
  92 } XilinxSPI;
  93
  94 static void txfifo_reset(XilinxSPI *s)
  95 {
  96     fifo8_reset(&s->tx_fifo);
  97
  98     s->regs[R_SPISR] &= ~SR_TX_FULL;
  99     s->regs[R_SPISR] |= SR_TX_EMPTY;
 100 }
 101
 102 static void rxfifo_reset(XilinxSPI *s)
 103 {
 104     fifo8_reset(&s->rx_fifo);
 105
 106     s->regs[R_SPISR] |= SR_RX_EMPTY;
 107     s->regs[R_SPISR] &= ~SR_RX_FULL;
 108 }
 109
 110 static void xlx_spi_update_cs(XilinxSPI *s)
 111 {
 112    int i;
 113
 114     for (i = 0; i < s->num_cs; ++i) {
 115         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
 116     }
 117 }
 118
 119 static void xlx_spi_update_irq(XilinxSPI *s)
 120 {
 121     uint32_t pending;
 122
 123     s->regs[R_IPISR] |=
 124             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
 125             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
 126
 127     pending = s->regs[R_IPISR] & s->regs[R_IPIER];
 128
 129     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
 130     pending = !!pending;
 131
 132     /* This call lies right in the data paths so don't call the
 133        irq chain unless things really changed.  */
 134     if (pending != s->irqline) {
 135         s->irqline = pending;
 136         DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
 137                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);
 138         qemu_set_irq(s->irq, pending);
 139     }
 140
 141 }
 142
 143 static void xlx_spi_do_reset(XilinxSPI *s)
 144 {
 145     memset(s->regs, 0, sizeof s->regs);
 146
 147     rxfifo_reset(s);
 148     txfifo_reset(s);
 149
 150     s->regs[R_SPISSR] = ~0;
 151     xlx_spi_update_irq(s);
 152     xlx_spi_update_cs(s);
 153 }
 154
 155 static void xlx_spi_reset(DeviceState *d)
 156 {
 157     xlx_spi_do_reset(DO_UPCAST(XilinxSPI, busdev.qdev, d));
 158 }
 159
 160 static inline int spi_master_enabled(XilinxSPI *s)
 161 {
 162     return !(s->regs[R_SPICR] & R_SPICR_MTI);
 163 }
 164
 165 static void spi_flush_txfifo(XilinxSPI *s)
 166 {
 167     uint32_t tx;
 168     uint32_t rx;
 169
 170     while (!fifo8_is_empty(&s->tx_fifo)) {
 171         tx = (uint32_t)fifo8_pop(&s->tx_fifo);
 172         DB_PRINT("data tx:%x\n", tx);
 173         rx = ssi_transfer(s->spi, tx);
 174         DB_PRINT("data rx:%x\n", rx);
 175         if (fifo8_is_full(&s->rx_fifo)) {
 176             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
 177         } else {
 178             fifo8_push(&s->rx_fifo, (uint8_t)rx);
 179             if (fifo8_is_full(&s->rx_fifo)) {
 180                 s->regs[R_SPISR] |= SR_RX_FULL;
 181                 s->regs[R_IPISR] |= IRQ_DRR_FULL;
 182             }
 183         }
 184
 185         s->regs[R_SPISR] &= ~SR_RX_EMPTY;
 186         s->regs[R_SPISR] &= ~SR_TX_FULL;
 187         s->regs[R_SPISR] |= SR_TX_EMPTY;
 188
 189         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
 190         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
 191     }
 192
 193 }
 194
 195 static uint64_t
 196 spi_read(void *opaque, hwaddr addr, unsigned int size)
 197 {
 198     XilinxSPI *s = opaque;
 199     uint32_t r = 0;
 200
 201     addr >>= 2;
 202     switch (addr) {
 203     case R_SPIDRR:
 204         if (fifo8_is_empty(&s->rx_fifo)) {
 205             DB_PRINT("Read from empty FIFO!\n");
 206             return 0xdeadbeef;
 207         }
 208
 209         s->regs[R_SPISR] &= ~SR_RX_FULL;
 210         r = fifo8_pop(&s->rx_fifo);
 211         if (fifo8_is_empty(&s->rx_fifo)) {
 212             s->regs[R_SPISR] |= SR_RX_EMPTY;
 213         }
 214         break;
 215
 216     case R_SPISR:
 217         r = s->regs[addr];
 218         break;
 219
 220     default:
 221         if (addr < ARRAY_SIZE(s->regs)) {
 222             r = s->regs[addr];
 223         }
 224         break;
 225
 226     }
 227     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
 228     xlx_spi_update_irq(s);
 229     return r;
 230 }
 231
 232 static void
 233 spi_write(void *opaque, hwaddr addr,
 234             uint64_t val64, unsigned int size)
 235 {
 236     XilinxSPI *s = opaque;
 237     uint32_t value = val64;
 238
 239     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
 240     addr >>= 2;
 241     switch (addr) {
 242     case R_SRR:
 243         if (value != 0xa) {
 244             DB_PRINT("Invalid write to SRR %x\n", value);
 245         } else {
 246             xlx_spi_do_reset(s);
 247         }
 248         break;
 249
 250     case R_SPIDTR:
 251         s->regs[R_SPISR] &= ~SR_TX_EMPTY;
 252         fifo8_push(&s->tx_fifo, (uint8_t)value);
 253         if (fifo8_is_full(&s->tx_fifo)) {
 254             s->regs[R_SPISR] |= SR_TX_FULL;
 255         }
 256         if (!spi_master_enabled(s)) {
 257             goto done;
 258         } else {
 259             DB_PRINT("DTR and master enabled\n");
 260         }
 261         spi_flush_txfifo(s);
 262         break;
 263
 264     case R_SPISR:
 265         DB_PRINT("Invalid write to SPISR %x\n", value);
 266         break;
 267
 268     case R_IPISR:
 269         /* Toggle the bits.  */
 270         s->regs[addr] ^= value;
 271         break;
 272
 273     /* Slave Select Register.  */
 274     case R_SPISSR:
 275         s->regs[addr] = value;
 276         xlx_spi_update_cs(s);
 277         break;
 278
 279     case R_SPICR:
 280         /* FIXME: reset irq and sr state to empty queues.  */
 281         if (value & R_SPICR_RXFF_RST) {
 282             rxfifo_reset(s);
 283         }
 284
 285         if (value & R_SPICR_TXFF_RST) {
 286             txfifo_reset(s);
 287         }
 288         value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
 289         s->regs[addr] = value;
 290
 291         if (!(value & R_SPICR_MTI)) {
 292             spi_flush_txfifo(s);
 293         }
 294         break;
 295
 296     default:
 297         if (addr < ARRAY_SIZE(s->regs)) {
 298             s->regs[addr] = value;
 299         }
 300         break;
 301     }
 302
 303 done:
 304     xlx_spi_update_irq(s);
 305 }
 306
 307 static const MemoryRegionOps spi_ops = {
 308     .read = spi_read,
 309     .write = spi_write,
 310     .endianness = DEVICE_NATIVE_ENDIAN,
 311     .valid = {
 312         .min_access_size = 4,
 313         .max_access_size = 4
 314     }
 315 };
 316
 317 static int xilinx_spi_init(SysBusDevice *dev)
 318 {
 319     int i;
 320     XilinxSPI *s = FROM_SYSBUS(typeof(*s), dev);
 321
 322     DB_PRINT("\n");
 323
 324     s->spi = ssi_create_bus(&dev->qdev, "spi");
 325
 326     sysbus_init_irq(dev, &s->irq);
 327     s->cs_lines = g_new(qemu_irq, s->num_cs);
 328     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi);
 329     for (i = 0; i < s->num_cs; ++i) {
 330         sysbus_init_irq(dev, &s->cs_lines[i]);
 331     }
 332
 333     memory_region_init_io(&s->mmio, &spi_ops, s, "xilinx-spi", R_MAX * 4);
 334     sysbus_init_mmio(dev, &s->mmio);
 335
 336     s->irqline = -1;
 337
 338     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
 339     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
 340
 341     return 0;
 342 }
 343
 344 static const VMStateDescription vmstate_xilinx_spi = {
 345     .name = "xilinx_spi",
 346     .version_id = 1,
 347     .minimum_version_id = 1,
 348     .minimum_version_id_old = 1,
 349     .fields = (VMStateField[]) {
 350         VMSTATE_FIFO8(tx_fifo, XilinxSPI),
 351         VMSTATE_FIFO8(rx_fifo, XilinxSPI),
 352         VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
 353         VMSTATE_END_OF_LIST()
 354     }
 355 };
 356
 357 static Property xilinx_spi_properties[] = {
 358     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
 359     DEFINE_PROP_END_OF_LIST(),
 360 };
 361
 362 static void xilinx_spi_class_init(ObjectClass *klass, void *data)
 363 {
 364     DeviceClass *dc = DEVICE_CLASS(klass);
 365     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 366
 367     k->init = xilinx_spi_init;
 368     dc->reset = xlx_spi_reset;
 369     dc->props = xilinx_spi_properties;
 370     dc->vmsd = &vmstate_xilinx_spi;
 371 }
 372
 373 static const TypeInfo xilinx_spi_info = {
 374     .name           = "xlnx.xps-spi",
 375     .parent         = TYPE_SYS_BUS_DEVICE,
 376     .instance_size  = sizeof(XilinxSPI),
 377     .class_init     = xilinx_spi_class_init,
 378 };
 379
 380 static void xilinx_spi_register_types(void)
 381 {
 382     type_register_static(&xilinx_spi_info);
 383 }
 384
 385 type_init(xilinx_spi_register_types)