hw/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GNU LGPL
   8  */
   9
  10 #include "sysbus.h"
  11 #include "console.h"
  12 #include "framebuffer.h"
  13
  14 #define PL110_CR_EN   0x001
  15 #define PL110_CR_BGR  0x100
  16 #define PL110_CR_BEBO 0x200
  17 #define PL110_CR_BEPO 0x400
  18 #define PL110_CR_PWR  0x800
  19
  20 enum pl110_bppmode
  21 {
  22     BPP_1,
  23     BPP_2,
  24     BPP_4,
  25     BPP_8,
  26     BPP_16,
  27     BPP_32
  28 };
  29
  30 typedef struct {
  31     SysBusDevice busdev;
  32     DisplayState *ds;
  33
  34     /* The Versatile/PB uses a slightly modified PL110 controller.  */
  35     int versatile;
  36     uint32_t timing[4];
  37     uint32_t cr;
  38     uint32_t upbase;
  39     uint32_t lpbase;
  40     uint32_t int_status;
  41     uint32_t int_mask;
  42     int cols;
  43     int rows;
  44     enum pl110_bppmode bpp;
  45     int invalidate;
  46     uint32_t pallette[256];
  47     uint32_t raw_pallette[128];
  48     qemu_irq irq;
  49 } pl110_state;
  50
  51 static const unsigned char pl110_id[] =
  52 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  53
  54 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
  55    has a different ID.  However Linux only looks for the normal ID.  */
  56 #if 0
  57 static const unsigned char pl110_versatile_id[] =
  58 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  59 #else
  60 #define pl110_versatile_id pl110_id
  61 #endif
  62
  63 #include "pixel_ops.h"
  64
  65 #define BITS 8
  66 #include "pl110_template.h"
  67 #define BITS 15
  68 #include "pl110_template.h"
  69 #define BITS 16
  70 #include "pl110_template.h"
  71 #define BITS 24
  72 #include "pl110_template.h"
  73 #define BITS 32
  74 #include "pl110_template.h"
  75
  76 static int pl110_enabled(pl110_state *s)
  77 {
  78   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
  79 }
  80
  81 static void pl110_update_display(void *opaque)
  82 {
  83     pl110_state *s = (pl110_state *)opaque;
  84     drawfn* fntable;
  85     drawfn fn;
  86     int dest_width;
  87     int src_width;
  88     int bpp_offset;
  89     int first;
  90     int last;
  91
  92     if (!pl110_enabled(s))
  93         return;
  94
  95     switch (ds_get_bits_per_pixel(s->ds)) {
  96     case 0:
  97         return;
  98     case 8:
  99         fntable = pl110_draw_fn_8;
 100         dest_width = 1;
 101         break;
 102     case 15:
 103         fntable = pl110_draw_fn_15;
 104         dest_width = 2;
 105         break;
 106     case 16:
 107         fntable = pl110_draw_fn_16;
 108         dest_width = 2;
 109         break;
 110     case 24:
 111         fntable = pl110_draw_fn_24;
 112         dest_width = 3;
 113         break;
 114     case 32:
 115         fntable = pl110_draw_fn_32;
 116         dest_width = 4;
 117         break;
 118     default:
 119         fprintf(stderr, "pl110: Bad color depth\n");
 120         exit(1);
 121     }
 122     if (s->cr & PL110_CR_BGR)
 123         bpp_offset = 0;
 124     else
 125         bpp_offset = 18;
 126
 127     if (s->cr & PL110_CR_BEBO)
 128         fn = fntable[s->bpp + 6 + bpp_offset];
 129     else if (s->cr & PL110_CR_BEPO)
 130         fn = fntable[s->bpp + 12 + bpp_offset];
 131     else
 132         fn = fntable[s->bpp + bpp_offset];
 133
 134     src_width = s->cols;
 135     switch (s->bpp) {
 136     case BPP_1:
 137         src_width >>= 3;
 138         break;
 139     case BPP_2:
 140         src_width >>= 2;
 141         break;
 142     case BPP_4:
 143         src_width >>= 1;
 144         break;
 145     case BPP_8:
 146         break;
 147     case BPP_16:
 148         src_width <<= 1;
 149         break;
 150     case BPP_32:
 151         src_width <<= 2;
 152         break;
 153     }
 154     dest_width *= s->cols;
 155     first = 0;
 156     framebuffer_update_display(s->ds,
 157                                s->upbase, s->cols, s->rows,
 158                                src_width, dest_width, 0,
 159                                s->invalidate,
 160                                fn, s->pallette,
 161                                &first, &last);
 162     if (first >= 0) {
 163         dpy_update(s->ds, 0, first, s->cols, last - first + 1);
 164     }
 165     s->invalidate = 0;
 166 }
 167
 168 static void pl110_invalidate_display(void * opaque)
 169 {
 170     pl110_state *s = (pl110_state *)opaque;
 171     s->invalidate = 1;
 172     if (pl110_enabled(s)) {
 173         qemu_console_resize(s->ds, s->cols, s->rows);
 174     }
 175 }
 176
 177 static void pl110_update_pallette(pl110_state *s, int n)
 178 {
 179     int i;
 180     uint32_t raw;
 181     unsigned int r, g, b;
 182
 183     raw = s->raw_pallette[n];
 184     n <<= 1;
 185     for (i = 0; i < 2; i++) {
 186         r = (raw & 0x1f) << 3;
 187         raw >>= 5;
 188         g = (raw & 0x1f) << 3;
 189         raw >>= 5;
 190         b = (raw & 0x1f) << 3;
 191         /* The I bit is ignored.  */
 192         raw >>= 6;
 193         switch (ds_get_bits_per_pixel(s->ds)) {
 194         case 8:
 195             s->pallette[n] = rgb_to_pixel8(r, g, b);
 196             break;
 197         case 15:
 198             s->pallette[n] = rgb_to_pixel15(r, g, b);
 199             break;
 200         case 16:
 201             s->pallette[n] = rgb_to_pixel16(r, g, b);
 202             break;
 203         case 24:
 204         case 32:
 205             s->pallette[n] = rgb_to_pixel32(r, g, b);
 206             break;
 207         }
 208         n++;
 209     }
 210 }
 211
 212 static void pl110_resize(pl110_state *s, int width, int height)
 213 {
 214     if (width != s->cols || height != s->rows) {
 215         if (pl110_enabled(s)) {
 216             qemu_console_resize(s->ds, width, height);
 217         }
 218     }
 219     s->cols = width;
 220     s->rows = height;
 221 }
 222
 223 /* Update interrupts.  */
 224 static void pl110_update(pl110_state *s)
 225 {
 226   /* TODO: Implement interrupts.  */
 227 }
 228
 229 static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
 230 {
 231     pl110_state *s = (pl110_state *)opaque;
 232
 233     if (offset >= 0xfe0 && offset < 0x1000) {
 234         if (s->versatile)
 235             return pl110_versatile_id[(offset - 0xfe0) >> 2];
 236         else
 237             return pl110_id[(offset - 0xfe0) >> 2];
 238     }
 239     if (offset >= 0x200 && offset < 0x400) {
 240         return s->raw_pallette[(offset - 0x200) >> 2];
 241     }
 242     switch (offset >> 2) {
 243     case 0: /* LCDTiming0 */
 244         return s->timing[0];
 245     case 1: /* LCDTiming1 */
 246         return s->timing[1];
 247     case 2: /* LCDTiming2 */
 248         return s->timing[2];
 249     case 3: /* LCDTiming3 */
 250         return s->timing[3];
 251     case 4: /* LCDUPBASE */
 252         return s->upbase;
 253     case 5: /* LCDLPBASE */
 254         return s->lpbase;
 255     case 6: /* LCDIMSC */
 256         if (s->versatile)
 257           return s->cr;
 258         return s->int_mask;
 259     case 7: /* LCDControl */
 260         if (s->versatile)
 261           return s->int_mask;
 262         return s->cr;
 263     case 8: /* LCDRIS */
 264         return s->int_status;
 265     case 9: /* LCDMIS */
 266         return s->int_status & s->int_mask;
 267     case 11: /* LCDUPCURR */
 268         /* TODO: Implement vertical refresh.  */
 269         return s->upbase;
 270     case 12: /* LCDLPCURR */
 271         return s->lpbase;
 272     default:
 273         hw_error("pl110_read: Bad offset %x\n", (int)offset);
 274         return 0;
 275     }
 276 }
 277
 278 static void pl110_write(void *opaque, target_phys_addr_t offset,
 279                         uint32_t val)
 280 {
 281     pl110_state *s = (pl110_state *)opaque;
 282     int n;
 283
 284     /* For simplicity invalidate the display whenever a control register
 285        is writen to.  */
 286     s->invalidate = 1;
 287     if (offset >= 0x200 && offset < 0x400) {
 288         /* Pallette.  */
 289         n = (offset - 0x200) >> 2;
 290         s->raw_pallette[(offset - 0x200) >> 2] = val;
 291         pl110_update_pallette(s, n);
 292         return;
 293     }
 294     switch (offset >> 2) {
 295     case 0: /* LCDTiming0 */
 296         s->timing[0] = val;
 297         n = ((val & 0xfc) + 4) * 4;
 298         pl110_resize(s, n, s->rows);
 299         break;
 300     case 1: /* LCDTiming1 */
 301         s->timing[1] = val;
 302         n = (val & 0x3ff) + 1;
 303         pl110_resize(s, s->cols, n);
 304         break;
 305     case 2: /* LCDTiming2 */
 306         s->timing[2] = val;
 307         break;
 308     case 3: /* LCDTiming3 */
 309         s->timing[3] = val;
 310         break;
 311     case 4: /* LCDUPBASE */
 312         s->upbase = val;
 313         break;
 314     case 5: /* LCDLPBASE */
 315         s->lpbase = val;
 316         break;
 317     case 6: /* LCDIMSC */
 318         if (s->versatile)
 319             goto control;
 320     imsc:
 321         s->int_mask = val;
 322         pl110_update(s);
 323         break;
 324     case 7: /* LCDControl */
 325         if (s->versatile)
 326             goto imsc;
 327     control:
 328         s->cr = val;
 329         s->bpp = (val >> 1) & 7;
 330         if (pl110_enabled(s)) {
 331             qemu_console_resize(s->ds, s->cols, s->rows);
 332         }
 333         break;
 334     case 10: /* LCDICR */
 335         s->int_status &= ~val;
 336         pl110_update(s);
 337         break;
 338     default:
 339         hw_error("pl110_write: Bad offset %x\n", (int)offset);
 340     }
 341 }
 342
 343 static CPUReadMemoryFunc * const pl110_readfn[] = {
 344    pl110_read,
 345    pl110_read,
 346    pl110_read
 347 };
 348
 349 static CPUWriteMemoryFunc * const pl110_writefn[] = {
 350    pl110_write,
 351    pl110_write,
 352    pl110_write
 353 };
 354
 355 static int pl110_init(SysBusDevice *dev)
 356 {
 357     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 358     int iomemtype;
 359
 360     iomemtype = cpu_register_io_memory(pl110_readfn,
 361                                        pl110_writefn, s,
 362                                        DEVICE_NATIVE_ENDIAN);
 363     sysbus_init_mmio(dev, 0x1000, iomemtype);
 364     sysbus_init_irq(dev, &s->irq);
 365     s->ds = graphic_console_init(pl110_update_display,
 366                                  pl110_invalidate_display,
 367                                  NULL, NULL, s);
 368     /* ??? Save/restore.  */
 369     return 0;
 370 }
 371
 372 static int pl110_versatile_init(SysBusDevice *dev)
 373 {
 374     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 375     s->versatile = 1;
 376     return pl110_init(dev);
 377 }
 378
 379 static void pl110_register_devices(void)
 380 {
 381     sysbus_register_dev("pl110", sizeof(pl110_state), pl110_init);
 382     sysbus_register_dev("pl110_versatile", sizeof(pl110_state),
 383                         pl110_versatile_init);
 384 }
 385
 386 device_init(pl110_register_devices)