exec: Pass CPUState to cpu_reset_interrupt()
[qemu/agraf.git] / hw / openrisc / pic_cpu.c
blob7e4f9e015e1a88985e254f941bea820bfb1501b6
1 /*
2 * OpenRISC Programmable Interrupt Controller support.
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "hw/hw.h"
22 #include "cpu.h"
24 /* OpenRISC pic handler */
25 static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
27 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
28 CPUState *cs = CPU(cpu);
29 int i;
30 uint32_t irq_bit = 1 << irq;
32 if (irq > 31 || irq < 0) {
33 return;
36 if (level) {
37 cpu->env.picsr |= irq_bit;
38 } else {
39 cpu->env.picsr &= ~irq_bit;
42 for (i = 0; i < 32; i++) {
43 if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
44 cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
45 } else {
46 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
47 cpu->env.picsr &= ~(1 << i);
52 void cpu_openrisc_pic_init(OpenRISCCPU *cpu)
54 int i;
55 qemu_irq *qi;
56 qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS);
58 for (i = 0; i < NR_IRQS; i++) {
59 cpu->env.irq[i] = qi[i];