microblaze: Dont segfault when singlestepping first insn.
[qemu/agraf.git] / hw / mac_nvram.c
blobf28db6bb25bdd660ddcf04c9425eed527f9c23ba
1 /*
2 * PowerMac NVRAM emulation
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
25 #include "hw.h"
26 #include "firmware_abi.h"
27 #include "sysemu.h"
28 #include "ppc_mac.h"
30 /* debug NVR */
31 //#define DEBUG_NVR
33 #ifdef DEBUG_NVR
34 #define NVR_DPRINTF(fmt, ...) \
35 do { printf("NVR: " fmt , ## __VA_ARGS__); } while (0)
36 #else
37 #define NVR_DPRINTF(fmt, ...)
38 #endif
40 struct MacIONVRAMState {
41 target_phys_addr_t size;
42 int mem_index;
43 unsigned int it_shift;
44 uint8_t *data;
47 #define DEF_SYSTEM_SIZE 0xc10
49 /* Direct access to NVRAM */
50 uint32_t macio_nvram_read (void *opaque, uint32_t addr)
52 MacIONVRAMState *s = opaque;
53 uint32_t ret;
55 if (addr < s->size)
56 ret = s->data[addr];
57 else
58 ret = -1;
59 NVR_DPRINTF("read addr %04x val %x\n", addr, ret);
61 return ret;
64 void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
66 MacIONVRAMState *s = opaque;
68 NVR_DPRINTF("write addr %04x val %x\n", addr, val);
69 if (addr < s->size)
70 s->data[addr] = val;
73 /* macio style NVRAM device */
74 static void macio_nvram_writeb (void *opaque,
75 target_phys_addr_t addr, uint32_t value)
77 MacIONVRAMState *s = opaque;
79 addr = (addr >> s->it_shift) & (s->size - 1);
80 s->data[addr] = value;
81 NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
84 static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
86 MacIONVRAMState *s = opaque;
87 uint32_t value;
89 addr = (addr >> s->it_shift) & (s->size - 1);
90 value = s->data[addr];
91 NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
93 return value;
96 static CPUWriteMemoryFunc * const nvram_write[] = {
97 &macio_nvram_writeb,
98 &macio_nvram_writeb,
99 &macio_nvram_writeb,
102 static CPUReadMemoryFunc * const nvram_read[] = {
103 &macio_nvram_readb,
104 &macio_nvram_readb,
105 &macio_nvram_readb,
108 static void macio_nvram_save(QEMUFile *f, void *opaque)
110 MacIONVRAMState *s = (MacIONVRAMState *)opaque;
112 qemu_put_buffer(f, s->data, s->size);
115 static int macio_nvram_load(QEMUFile *f, void *opaque, int version_id)
117 MacIONVRAMState *s = (MacIONVRAMState *)opaque;
119 if (version_id != 1)
120 return -EINVAL;
122 qemu_get_buffer(f, s->data, s->size);
124 return 0;
127 static void macio_nvram_reset(void *opaque)
131 MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
132 unsigned int it_shift)
134 MacIONVRAMState *s;
136 s = qemu_mallocz(sizeof(MacIONVRAMState));
137 s->data = qemu_mallocz(size);
138 s->size = size;
139 s->it_shift = it_shift;
141 s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
142 *mem_index = s->mem_index;
143 register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
145 qemu_register_reset(macio_nvram_reset, s);
147 return s;
150 void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
152 MacIONVRAMState *s;
154 s = opaque;
155 cpu_register_physical_memory(mem_base, s->size << s->it_shift,
156 s->mem_index);
159 /* Set up a system OpenBIOS NVRAM partition */
160 void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len)
162 unsigned int i;
163 uint32_t start = 0, end;
164 struct OpenBIOS_nvpart_v1 *part_header;
166 // OpenBIOS nvram variables
167 // Variable partition
168 part_header = (struct OpenBIOS_nvpart_v1 *)nvr->data;
169 part_header->signature = OPENBIOS_PART_SYSTEM;
170 pstrcpy(part_header->name, sizeof(part_header->name), "system");
172 end = start + sizeof(struct OpenBIOS_nvpart_v1);
173 for (i = 0; i < nb_prom_envs; i++)
174 end = OpenBIOS_set_var(nvr->data, end, prom_envs[i]);
176 // End marker
177 nvr->data[end++] = '\0';
179 end = start + ((end - start + 15) & ~15);
180 /* XXX: OpenBIOS is not able to grow up a partition. Leave some space for
181 new variables. */
182 if (end < DEF_SYSTEM_SIZE)
183 end = DEF_SYSTEM_SIZE;
184 OpenBIOS_finish_partition(part_header, end - start);
186 // free partition
187 start = end;
188 part_header = (struct OpenBIOS_nvpart_v1 *)&nvr->data[start];
189 part_header->signature = OPENBIOS_PART_FREE;
190 pstrcpy(part_header->name, sizeof(part_header->name), "free");
192 end = len;
193 OpenBIOS_finish_partition(part_header, end - start);