hw/exynos4210.c

   1 /*
   2  *  Samsung exynos4210 SoC emulation
   3  *
   4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5  *    Maksim Kozlov <m.kozlov@samsung.com>
   6  *    Evgeny Voevodin <e.voevodin@samsung.com>
   7  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License as published by the
  11  *  Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include "boards.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysbus.h"
  27 #include "arm-misc.h"
  28 #include "loader.h"
  29 #include "exynos4210.h"
  30 #include "usb/hcd-ehci.h"
  31
  32 #define EXYNOS4210_CHIPID_ADDR         0x10000000
  33
  34 /* PWM */
  35 #define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  36
  37 /* RTC */
  38 #define EXYNOS4210_RTC_BASE_ADDR       0x10070000
  39
  40 /* MCT */
  41 #define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  42
  43 /* I2C */
  44 #define EXYNOS4210_I2C_SHIFT           0x00010000
  45 #define EXYNOS4210_I2C_BASE_ADDR       0x13860000
  46 /* Interrupt Group of External Interrupt Combiner for I2C */
  47 #define EXYNOS4210_I2C_INTG            27
  48 #define EXYNOS4210_HDMI_INTG           16
  49
  50 /* UART's definitions */
  51 #define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  52 #define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  53 #define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  54 #define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  55 #define EXYNOS4210_UART0_FIFO_SIZE     256
  56 #define EXYNOS4210_UART1_FIFO_SIZE     64
  57 #define EXYNOS4210_UART2_FIFO_SIZE     16
  58 #define EXYNOS4210_UART3_FIFO_SIZE     16
  59 /* Interrupt Group of External Interrupt Combiner for UART */
  60 #define EXYNOS4210_UART_INT_GRP        26
  61
  62 /* External GIC */
  63 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  64 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  65
  66 /* Combiner */
  67 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  68 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  69
  70 /* PMU SFR base address */
  71 #define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  72
  73 /* Display controllers (FIMD) */
  74 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  75
  76 /* EHCI */
  77 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
  78
  79 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
  80                                     0x09, 0x00, 0x00, 0x00 };
  81
  82 void exynos4210_write_secondary(ARMCPU *cpu,
  83         const struct arm_boot_info *info)
  84 {
  85     int n;
  86     uint32_t smpboot[] = {
  87         0xe59f3034, /* ldr r3, External gic_cpu_if */
  88         0xe59f2034, /* ldr r2, Internal gic_cpu_if */
  89         0xe59f0034, /* ldr r0, startaddr */
  90         0xe3a01001, /* mov r1, #1 */
  91         0xe5821000, /* str r1, [r2] */
  92         0xe5831000, /* str r1, [r3] */
  93         0xe3a010ff, /* mov r1, #0xff */
  94         0xe5821004, /* str r1, [r2, #4] */
  95         0xe5831004, /* str r1, [r3, #4] */
  96         0xf57ff04f, /* dsb */
  97         0xe320f003, /* wfi */
  98         0xe5901000, /* ldr     r1, [r0] */
  99         0xe1110001, /* tst     r1, r1 */
 100         0x0afffffb, /* beq     <wfi> */
 101         0xe12fff11, /* bx      r1 */
 102         EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
 103         0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
 104         0           /* bootreg: Boot register address is held here */
 105     };
 106     smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
 107     smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
 108     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
 109         smpboot[n] = tswap32(smpboot[n]);
 110     }
 111     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
 112                        info->smp_loader_start);
 113 }
 114
 115 Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
 116         unsigned long ram_size)
 117 {
 118     qemu_irq cpu_irq[EXYNOS4210_NCPUS];
 119     int i, n;
 120     Exynos4210State *s = g_new(Exynos4210State, 1);
 121     qemu_irq *irqp;
 122     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
 123     unsigned long mem_size;
 124     DeviceState *dev;
 125     SysBusDevice *busdev;
 126
 127     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 128         s->cpu[n] = cpu_arm_init("cortex-a9");
 129         if (!s->cpu[n]) {
 130             fprintf(stderr, "Unable to find CPU %d definition\n", n);
 131             exit(1);
 132         }
 133
 134         /* Create PIC controller for each processor instance */
 135         irqp = arm_pic_init_cpu(s->cpu[n]);
 136
 137         /*
 138          * Get GICs gpio_in cpu_irq to connect a combiner to them later.
 139          * Use only IRQ for a while.
 140          */
 141         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 142     }
 143
 144     /*** IRQs ***/
 145
 146     s->irq_table = exynos4210_init_irq(&s->irqs);
 147
 148     /* IRQ Gate */
 149     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
 150         dev = qdev_create(NULL, "exynos4210.irq_gate");
 151         qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
 152         qdev_init_nofail(dev);
 153         /* Get IRQ Gate input in gate_irq */
 154         for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
 155             gate_irq[i][n] = qdev_get_gpio_in(dev, n);
 156         }
 157         busdev = sysbus_from_qdev(dev);
 158
 159         /* Connect IRQ Gate output to cpu_irq */
 160         sysbus_connect_irq(busdev, 0, cpu_irq[i]);
 161     }
 162
 163     /* Private memory region and Internal GIC */
 164     dev = qdev_create(NULL, "a9mpcore_priv");
 165     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 166     qdev_init_nofail(dev);
 167     busdev = sysbus_from_qdev(dev);
 168     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 169     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 170         sysbus_connect_irq(busdev, n, gate_irq[n][0]);
 171     }
 172     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 173         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 174     }
 175
 176     /* Cache controller */
 177     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 178
 179     /* External GIC */
 180     dev = qdev_create(NULL, "exynos4210.gic");
 181     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 182     qdev_init_nofail(dev);
 183     busdev = sysbus_from_qdev(dev);
 184     /* Map CPU interface */
 185     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 186     /* Map Distributer interface */
 187     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 188     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 189         sysbus_connect_irq(busdev, n, gate_irq[n][1]);
 190     }
 191     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 192         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 193     }
 194
 195     /* Internal Interrupt Combiner */
 196     dev = qdev_create(NULL, "exynos4210.combiner");
 197     qdev_init_nofail(dev);
 198     busdev = sysbus_from_qdev(dev);
 199     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 200         sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
 201     }
 202     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 203     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 204
 205     /* External Interrupt Combiner */
 206     dev = qdev_create(NULL, "exynos4210.combiner");
 207     qdev_prop_set_uint32(dev, "external", 1);
 208     qdev_init_nofail(dev);
 209     busdev = sysbus_from_qdev(dev);
 210     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 211         sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 212     }
 213     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 214     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 215
 216     /* Initialize board IRQs. */
 217     exynos4210_init_board_irqs(&s->irqs);
 218
 219     /*** Memory ***/
 220
 221     /* Chip-ID and OMR */
 222     memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
 223             sizeof(chipid_and_omr), chipid_and_omr);
 224     memory_region_set_readonly(&s->chipid_mem, true);
 225     memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 226                                 &s->chipid_mem);
 227
 228     /* Internal ROM */
 229     memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
 230                            EXYNOS4210_IROM_SIZE);
 231     memory_region_set_readonly(&s->irom_mem, true);
 232     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 233                                 &s->irom_mem);
 234     /* mirror of iROM */
 235     memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
 236                              &s->irom_mem,
 237                              0,
 238                              EXYNOS4210_IROM_SIZE);
 239     memory_region_set_readonly(&s->irom_alias_mem, true);
 240     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 241                                 &s->irom_alias_mem);
 242
 243     /* Internal RAM */
 244     memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
 245                            EXYNOS4210_IRAM_SIZE);
 246     vmstate_register_ram_global(&s->iram_mem);
 247     memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 248                                 &s->iram_mem);
 249
 250     /* DRAM */
 251     mem_size = ram_size;
 252     if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
 253         memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
 254                 mem_size - EXYNOS4210_DRAM_MAX_SIZE);
 255         vmstate_register_ram_global(&s->dram1_mem);
 256         memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
 257                 &s->dram1_mem);
 258         mem_size = EXYNOS4210_DRAM_MAX_SIZE;
 259     }
 260     memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
 261     vmstate_register_ram_global(&s->dram0_mem);
 262     memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
 263             &s->dram0_mem);
 264
 265    /* PMU.
 266     * The only reason of existence at the moment is that secondary CPU boot
 267     * loader uses PMU INFORM5 register as a holding pen.
 268     */
 269     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 270
 271     /* PWM */
 272     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 273                           s->irq_table[exynos4210_get_irq(22, 0)],
 274                           s->irq_table[exynos4210_get_irq(22, 1)],
 275                           s->irq_table[exynos4210_get_irq(22, 2)],
 276                           s->irq_table[exynos4210_get_irq(22, 3)],
 277                           s->irq_table[exynos4210_get_irq(22, 4)],
 278                           NULL);
 279     /* RTC */
 280     sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
 281                           s->irq_table[exynos4210_get_irq(23, 0)],
 282                           s->irq_table[exynos4210_get_irq(23, 1)],
 283                           NULL);
 284
 285     /* Multi Core Timer */
 286     dev = qdev_create(NULL, "exynos4210.mct");
 287     qdev_init_nofail(dev);
 288     busdev = sysbus_from_qdev(dev);
 289     for (n = 0; n < 4; n++) {
 290         /* Connect global timer interrupts to Combiner gpio_in */
 291         sysbus_connect_irq(busdev, n,
 292                 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 293     }
 294     /* Connect local timer interrupts to Combiner gpio_in */
 295     sysbus_connect_irq(busdev, 4,
 296             s->irq_table[exynos4210_get_irq(51, 0)]);
 297     sysbus_connect_irq(busdev, 5,
 298             s->irq_table[exynos4210_get_irq(35, 3)]);
 299     sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 300
 301     /*** I2C ***/
 302     for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
 303         uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
 304         qemu_irq i2c_irq;
 305
 306         if (n < 8) {
 307             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
 308         } else {
 309             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
 310         }
 311
 312         dev = qdev_create(NULL, "exynos4210.i2c");
 313         qdev_init_nofail(dev);
 314         busdev = sysbus_from_qdev(dev);
 315         sysbus_connect_irq(busdev, 0, i2c_irq);
 316         sysbus_mmio_map(busdev, 0, addr);
 317         s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
 318     }
 319
 320
 321     /*** UARTs ***/
 322     exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 323                            EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
 324                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 325
 326     exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 327                            EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
 328                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 329
 330     exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 331                            EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
 332                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 333
 334     exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 335                            EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
 336                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 337
 338     /*** Display controller (FIMD) ***/
 339     sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 340             s->irq_table[exynos4210_get_irq(11, 0)],
 341             s->irq_table[exynos4210_get_irq(11, 1)],
 342             s->irq_table[exynos4210_get_irq(11, 2)],
 343             NULL);
 344
 345     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
 346             s->irq_table[exynos4210_get_irq(28, 3)]);
 347
 348     return s;
 349 }