?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
openpic: export e500 epr enable into a ppc.c function
[qemu/agraf.git] / hw / ppc.c
blob1fce604c73f97a7396dd5bf88d06d98a463936c5
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
28 #include "nvram.h"
29 #include "qemu/log.h"
30 #include "loader.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33
34 //#define PPC_DEBUG_IRQ
35 //#define PPC_DEBUG_TB
36
37 #ifdef PPC_DEBUG_IRQ
38 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
39 #else
40 # define LOG_IRQ(...) do { } while (0)
41 #endif
42
43
44 #ifdef PPC_DEBUG_TB
45 # define LOG_TB(...) qemu_log(__VA_ARGS__)
46 #else
47 # define LOG_TB(...) do { } while (0)
48 #endif
49
50 static void cpu_ppc_tb_stop (CPUPPCState *env);
51 static void cpu_ppc_tb_start (CPUPPCState *env);
52
53 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
54 {
55 CPUPPCState *env = &cpu->env;
56 unsigned int old_pending = env->pending_interrupts;
57
58 if (level) {
59 env->pending_interrupts |= 1 << n_IRQ;
60 cpu_interrupt(env, CPU_INTERRUPT_HARD);
61 } else {
62 env->pending_interrupts &= ~(1 << n_IRQ);
63 if (env->pending_interrupts == 0)
64 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
65 }
66
67 if (old_pending != env->pending_interrupts) {
68 #ifdef CONFIG_KVM
69 kvmppc_set_interrupt(cpu, n_IRQ, level);
70 #endif
71 }
72
73 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
74 "req %08x\n", __func__, env, n_IRQ, level,
75 env->pending_interrupts, env->interrupt_request);
76 }
77
78 /* PowerPC 6xx / 7xx internal IRQ controller */
79 static void ppc6xx_set_irq(void *opaque, int pin, int level)
80 {
81 PowerPCCPU *cpu = opaque;
82 CPUPPCState *env = &cpu->env;
83 int cur_level;
84
85 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
86 env, pin, level);
87 cur_level = (env->irq_input_state >> pin) & 1;
88 /* Don't generate spurious events */
89 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
90 switch (pin) {
91 case PPC6xx_INPUT_TBEN:
92 /* Level sensitive - active high */
93 LOG_IRQ("%s: %s the time base\n",
94 __func__, level ? "start" : "stop");
95 if (level) {
96 cpu_ppc_tb_start(env);
97 } else {
98 cpu_ppc_tb_stop(env);
99 }
100 case PPC6xx_INPUT_INT:
101 /* Level sensitive - active high */
102 LOG_IRQ("%s: set the external IRQ state to %d\n",
103 __func__, level);
104 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
105 break;
106 case PPC6xx_INPUT_SMI:
107 /* Level sensitive - active high */
108 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
109 __func__, level);
110 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
111 break;
112 case PPC6xx_INPUT_MCP:
113 /* Negative edge sensitive */
114 /* XXX: TODO: actual reaction may depends on HID0 status
115 * 603/604/740/750: check HID0[EMCP]
116 */
117 if (cur_level == 1 && level == 0) {
118 LOG_IRQ("%s: raise machine check state\n",
119 __func__);
120 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
121 }
122 break;
123 case PPC6xx_INPUT_CKSTP_IN:
124 /* Level sensitive - active low */
125 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
126 /* XXX: Note that the only way to restart the CPU is to reset it */
127 if (level) {
128 LOG_IRQ("%s: stop the CPU\n", __func__);
129 env->halted = 1;
130 }
131 break;
132 case PPC6xx_INPUT_HRESET:
133 /* Level sensitive - active low */
134 if (level) {
135 LOG_IRQ("%s: reset the CPU\n", __func__);
136 cpu_interrupt(env, CPU_INTERRUPT_RESET);
137 }
138 break;
139 case PPC6xx_INPUT_SRESET:
140 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
141 __func__, level);
142 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
143 break;
144 default:
145 /* Unknown pin - do nothing */
146 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
147 return;
148 }
149 if (level)
150 env->irq_input_state |= 1 << pin;
151 else
152 env->irq_input_state &= ~(1 << pin);
153 }
154 }
155
156 void ppc6xx_irq_init(CPUPPCState *env)
157 {
158 PowerPCCPU *cpu = ppc_env_get_cpu(env);
159
160 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
161 PPC6xx_INPUT_NB);
162 }
163
164 #if defined(TARGET_PPC64)
165 /* PowerPC 970 internal IRQ controller */
166 static void ppc970_set_irq(void *opaque, int pin, int level)
167 {
168 PowerPCCPU *cpu = opaque;
169 CPUPPCState *env = &cpu->env;
170 int cur_level;
171
172 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
173 env, pin, level);
174 cur_level = (env->irq_input_state >> pin) & 1;
175 /* Don't generate spurious events */
176 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
177 switch (pin) {
178 case PPC970_INPUT_INT:
179 /* Level sensitive - active high */
180 LOG_IRQ("%s: set the external IRQ state to %d\n",
181 __func__, level);
182 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
183 break;
184 case PPC970_INPUT_THINT:
185 /* Level sensitive - active high */
186 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
187 level);
188 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
189 break;
190 case PPC970_INPUT_MCP:
191 /* Negative edge sensitive */
192 /* XXX: TODO: actual reaction may depends on HID0 status
193 * 603/604/740/750: check HID0[EMCP]
194 */
195 if (cur_level == 1 && level == 0) {
196 LOG_IRQ("%s: raise machine check state\n",
197 __func__);
198 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
199 }
200 break;
201 case PPC970_INPUT_CKSTP:
202 /* Level sensitive - active low */
203 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
204 if (level) {
205 LOG_IRQ("%s: stop the CPU\n", __func__);
206 env->halted = 1;
207 } else {
208 LOG_IRQ("%s: restart the CPU\n", __func__);
209 env->halted = 0;
210 qemu_cpu_kick(CPU(cpu));
211 }
212 break;
213 case PPC970_INPUT_HRESET:
214 /* Level sensitive - active low */
215 if (level) {
216 cpu_interrupt(env, CPU_INTERRUPT_RESET);
217 }
218 break;
219 case PPC970_INPUT_SRESET:
220 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
221 __func__, level);
222 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
223 break;
224 case PPC970_INPUT_TBEN:
225 LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
226 level);
227 /* XXX: TODO */
228 break;
229 default:
230 /* Unknown pin - do nothing */
231 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
232 return;
233 }
234 if (level)
235 env->irq_input_state |= 1 << pin;
236 else
237 env->irq_input_state &= ~(1 << pin);
238 }
239 }
240
241 void ppc970_irq_init(CPUPPCState *env)
242 {
243 PowerPCCPU *cpu = ppc_env_get_cpu(env);
244
245 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
246 PPC970_INPUT_NB);
247 }
248
249 /* POWER7 internal IRQ controller */
250 static void power7_set_irq(void *opaque, int pin, int level)
251 {
252 PowerPCCPU *cpu = opaque;
253 CPUPPCState *env = &cpu->env;
254
255 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
256 env, pin, level);
257
258 switch (pin) {
259 case POWER7_INPUT_INT:
260 /* Level sensitive - active high */
261 LOG_IRQ("%s: set the external IRQ state to %d\n",
262 __func__, level);
263 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
264 break;
265 default:
266 /* Unknown pin - do nothing */
267 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
268 return;
269 }
270 if (level) {
271 env->irq_input_state |= 1 << pin;
272 } else {
273 env->irq_input_state &= ~(1 << pin);
274 }
275 }
276
277 void ppcPOWER7_irq_init(CPUPPCState *env)
278 {
279 PowerPCCPU *cpu = ppc_env_get_cpu(env);
280
281 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
282 POWER7_INPUT_NB);
283 }
284 #endif /* defined(TARGET_PPC64) */
285
286 /* PowerPC 40x internal IRQ controller */
287 static void ppc40x_set_irq(void *opaque, int pin, int level)
288 {
289 PowerPCCPU *cpu = opaque;
290 CPUPPCState *env = &cpu->env;
291 int cur_level;
292
293 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
294 env, pin, level);
295 cur_level = (env->irq_input_state >> pin) & 1;
296 /* Don't generate spurious events */
297 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
298 switch (pin) {
299 case PPC40x_INPUT_RESET_SYS:
300 if (level) {
301 LOG_IRQ("%s: reset the PowerPC system\n",
302 __func__);
303 ppc40x_system_reset(env);
304 }
305 break;
306 case PPC40x_INPUT_RESET_CHIP:
307 if (level) {
308 LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
309 ppc40x_chip_reset(env);
310 }
311 break;
312 case PPC40x_INPUT_RESET_CORE:
313 /* XXX: TODO: update DBSR[MRR] */
314 if (level) {
315 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
316 ppc40x_core_reset(env);
317 }
318 break;
319 case PPC40x_INPUT_CINT:
320 /* Level sensitive - active high */
321 LOG_IRQ("%s: set the critical IRQ state to %d\n",
322 __func__, level);
323 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
324 break;
325 case PPC40x_INPUT_INT:
326 /* Level sensitive - active high */
327 LOG_IRQ("%s: set the external IRQ state to %d\n",
328 __func__, level);
329 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
330 break;
331 case PPC40x_INPUT_HALT:
332 /* Level sensitive - active low */
333 if (level) {
334 LOG_IRQ("%s: stop the CPU\n", __func__);
335 env->halted = 1;
336 } else {
337 LOG_IRQ("%s: restart the CPU\n", __func__);
338 env->halted = 0;
339 qemu_cpu_kick(CPU(cpu));
340 }
341 break;
342 case PPC40x_INPUT_DEBUG:
343 /* Level sensitive - active high */
344 LOG_IRQ("%s: set the debug pin state to %d\n",
345 __func__, level);
346 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
347 break;
348 default:
349 /* Unknown pin - do nothing */
350 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
351 return;
352 }
353 if (level)
354 env->irq_input_state |= 1 << pin;
355 else
356 env->irq_input_state &= ~(1 << pin);
357 }
358 }
359
360 void ppc40x_irq_init(CPUPPCState *env)
361 {
362 PowerPCCPU *cpu = ppc_env_get_cpu(env);
363
364 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
365 cpu, PPC40x_INPUT_NB);
366 }
367
368 /* PowerPC E500 internal IRQ controller */
369 static void ppce500_set_irq(void *opaque, int pin, int level)
370 {
371 PowerPCCPU *cpu = opaque;
372 CPUPPCState *env = &cpu->env;
373 int cur_level;
374
375 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
376 env, pin, level);
377 cur_level = (env->irq_input_state >> pin) & 1;
378 /* Don't generate spurious events */
379 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
380 switch (pin) {
381 case PPCE500_INPUT_MCK:
382 if (level) {
383 LOG_IRQ("%s: reset the PowerPC system\n",
384 __func__);
385 qemu_system_reset_request();
386 }
387 break;
388 case PPCE500_INPUT_RESET_CORE:
389 if (level) {
390 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
391 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
392 }
393 break;
394 case PPCE500_INPUT_CINT:
395 /* Level sensitive - active high */
396 LOG_IRQ("%s: set the critical IRQ state to %d\n",
397 __func__, level);
398 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
399 break;
400 case PPCE500_INPUT_INT:
401 /* Level sensitive - active high */
402 LOG_IRQ("%s: set the core IRQ state to %d\n",
403 __func__, level);
404 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
405 break;
406 case PPCE500_INPUT_DEBUG:
407 /* Level sensitive - active high */
408 LOG_IRQ("%s: set the debug pin state to %d\n",
409 __func__, level);
410 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
411 break;
412 default:
413 /* Unknown pin - do nothing */
414 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
415 return;
416 }
417 if (level)
418 env->irq_input_state |= 1 << pin;
419 else
420 env->irq_input_state &= ~(1 << pin);
421 }
422 }
423
424 void ppce500_irq_init(CPUPPCState *env)
425 {
426 PowerPCCPU *cpu = ppc_env_get_cpu(env);
427
428 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
429 cpu, PPCE500_INPUT_NB);
430 }
431
432 /* Enable or Disable the E500 EPR capability */
433 void ppce500_set_mpic_proxy(bool enabled)
434 {
435 CPUPPCState *env;
436
437 for (env = first_cpu; env != NULL; env = env->next_cpu) {
438 env->mpic_proxy = enabled;
439 }
440 }
441
442 /*****************************************************************************/
443 /* PowerPC time base and decrementer emulation */
444
445 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
446 {
447 /* TB time in tb periods */
448 return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
449 }
450
451 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
452 {
453 ppc_tb_t *tb_env = env->tb_env;
454 uint64_t tb;
455
456 if (kvm_enabled()) {
457 return env->spr[SPR_TBL];
458 }
459
460 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
461 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
462
463 return tb;
464 }
465
466 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
467 {
468 ppc_tb_t *tb_env = env->tb_env;
469 uint64_t tb;
470
471 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
472 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
473
474 return tb >> 32;
475 }
476
477 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
478 {
479 if (kvm_enabled()) {
480 return env->spr[SPR_TBU];
481 }
482
483 return _cpu_ppc_load_tbu(env);
484 }
485
486 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
487 int64_t *tb_offsetp, uint64_t value)
488 {
489 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec());
490 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
491 __func__, value, *tb_offsetp);
492 }
493
494 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
495 {
496 ppc_tb_t *tb_env = env->tb_env;
497 uint64_t tb;
498
499 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
500 tb &= 0xFFFFFFFF00000000ULL;
501 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
502 &tb_env->tb_offset, tb | (uint64_t)value);
503 }
504
505 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
506 {
507 ppc_tb_t *tb_env = env->tb_env;
508 uint64_t tb;
509
510 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
511 tb &= 0x00000000FFFFFFFFULL;
512 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
513 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
514 }
515
516 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
517 {
518 _cpu_ppc_store_tbu(env, value);
519 }
520
521 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
522 {
523 ppc_tb_t *tb_env = env->tb_env;
524 uint64_t tb;
525
526 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
527 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
528
529 return tb;
530 }
531
532 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
533 {
534 ppc_tb_t *tb_env = env->tb_env;
535 uint64_t tb;
536
537 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
538 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
539
540 return tb >> 32;
541 }
542
543 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
544 {
545 ppc_tb_t *tb_env = env->tb_env;
546 uint64_t tb;
547
548 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
549 tb &= 0xFFFFFFFF00000000ULL;
550 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
551 &tb_env->atb_offset, tb | (uint64_t)value);
552 }
553
554 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
555 {
556 ppc_tb_t *tb_env = env->tb_env;
557 uint64_t tb;
558
559 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
560 tb &= 0x00000000FFFFFFFFULL;
561 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
562 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
563 }
564
565 static void cpu_ppc_tb_stop (CPUPPCState *env)
566 {
567 ppc_tb_t *tb_env = env->tb_env;
568 uint64_t tb, atb, vmclk;
569
570 /* If the time base is already frozen, do nothing */
571 if (tb_env->tb_freq != 0) {
572 vmclk = qemu_get_clock_ns(vm_clock);
573 /* Get the time base */
574 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
575 /* Get the alternate time base */
576 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
577 /* Store the time base value (ie compute the current offset) */
578 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
579 /* Store the alternate time base value (compute the current offset) */
580 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
581 /* Set the time base frequency to zero */
582 tb_env->tb_freq = 0;
583 /* Now, the time bases are frozen to tb_offset / atb_offset value */
584 }
585 }
586
587 static void cpu_ppc_tb_start (CPUPPCState *env)
588 {
589 ppc_tb_t *tb_env = env->tb_env;
590 uint64_t tb, atb, vmclk;
591
592 /* If the time base is not frozen, do nothing */
593 if (tb_env->tb_freq == 0) {
594 vmclk = qemu_get_clock_ns(vm_clock);
595 /* Get the time base from tb_offset */
596 tb = tb_env->tb_offset;
597 /* Get the alternate time base from atb_offset */
598 atb = tb_env->atb_offset;
599 /* Restore the tb frequency from the decrementer frequency */
600 tb_env->tb_freq = tb_env->decr_freq;
601 /* Store the time base value */
602 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
603 /* Store the alternate time base value */
604 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
605 }
606 }
607
608 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
609 {
610 ppc_tb_t *tb_env = env->tb_env;
611 uint32_t decr;
612 int64_t diff;
613
614 diff = next - qemu_get_clock_ns(vm_clock);
615 if (diff >= 0) {
616 decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec());
617 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
618 decr = 0;
619 } else {
620 decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec());
621 }
622 LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
623
624 return decr;
625 }
626
627 uint32_t cpu_ppc_load_decr (CPUPPCState *env)
628 {
629 ppc_tb_t *tb_env = env->tb_env;
630
631 if (kvm_enabled()) {
632 return env->spr[SPR_DECR];
633 }
634
635 return _cpu_ppc_load_decr(env, tb_env->decr_next);
636 }
637
638 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
639 {
640 ppc_tb_t *tb_env = env->tb_env;
641
642 return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
643 }
644
645 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
646 {
647 ppc_tb_t *tb_env = env->tb_env;
648 uint64_t diff;
649
650 diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start;
651
652 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
653 }
654
655 /* When decrementer expires,
656 * all we need to do is generate or queue a CPU exception
657 */
658 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
659 {
660 /* Raise it */
661 LOG_TB("raise decrementer exception\n");
662 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
663 }
664
665 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
666 {
667 /* Raise it */
668 LOG_TB("raise decrementer exception\n");
669 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
670 }
671
672 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
673 struct QEMUTimer *timer,
674 void (*raise_excp)(PowerPCCPU *),
675 uint32_t decr, uint32_t value,
676 int is_excp)
677 {
678 CPUPPCState *env = &cpu->env;
679 ppc_tb_t *tb_env = env->tb_env;
680 uint64_t now, next;
681
682 LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
683 decr, value);
684
685 if (kvm_enabled()) {
686 /* KVM handles decrementer exceptions, we don't need our own timer */
687 return;
688 }
689
690 now = qemu_get_clock_ns(vm_clock);
691 next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq);
692 if (is_excp) {
693 next += *nextp - now;
694 }
695 if (next == now) {
696 next++;
697 }
698 *nextp = next;
699 /* Adjust timer */
700 qemu_mod_timer(timer, next);
701
702 /* If we set a negative value and the decrementer was positive, raise an
703 * exception.
704 */
705 if ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED)
706 && (value & 0x80000000)
707 && !(decr & 0x80000000)) {
708 (*raise_excp)(cpu);
709 }
710 }
711
712 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr,
713 uint32_t value, int is_excp)
714 {
715 ppc_tb_t *tb_env = cpu->env.tb_env;
716
717 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
718 &cpu_ppc_decr_excp, decr, value, is_excp);
719 }
720
721 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
722 {
723 PowerPCCPU *cpu = ppc_env_get_cpu(env);
724
725 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, 0);
726 }
727
728 static void cpu_ppc_decr_cb(void *opaque)
729 {
730 PowerPCCPU *cpu = opaque;
731
732 _cpu_ppc_store_decr(cpu, 0x00000000, 0xFFFFFFFF, 1);
733 }
734
735 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr,
736 uint32_t value, int is_excp)
737 {
738 ppc_tb_t *tb_env = cpu->env.tb_env;
739
740 if (tb_env->hdecr_timer != NULL) {
741 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
742 &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
743 }
744 }
745
746 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
747 {
748 PowerPCCPU *cpu = ppc_env_get_cpu(env);
749
750 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 0);
751 }
752
753 static void cpu_ppc_hdecr_cb(void *opaque)
754 {
755 PowerPCCPU *cpu = opaque;
756
757 _cpu_ppc_store_hdecr(cpu, 0x00000000, 0xFFFFFFFF, 1);
758 }
759
760 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
761 {
762 ppc_tb_t *tb_env = cpu->env.tb_env;
763
764 tb_env->purr_load = value;
765 tb_env->purr_start = qemu_get_clock_ns(vm_clock);
766 }
767
768 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
769 {
770 CPUPPCState *env = opaque;
771 PowerPCCPU *cpu = ppc_env_get_cpu(env);
772 ppc_tb_t *tb_env = env->tb_env;
773
774 tb_env->tb_freq = freq;
775 tb_env->decr_freq = freq;
776 /* There is a bug in Linux 2.4 kernels:
777 * if a decrementer exception is pending when it enables msr_ee at startup,
778 * it's not ready to handle it...
779 */
780 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
781 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
782 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
783 }
784
785 /* Set up (once) timebase frequency (in Hz) */
786 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
787 {
788 PowerPCCPU *cpu = ppc_env_get_cpu(env);
789 ppc_tb_t *tb_env;
790
791 tb_env = g_malloc0(sizeof(ppc_tb_t));
792 env->tb_env = tb_env;
793 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
794 /* Create new timer */
795 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, cpu);
796 if (0) {
797 /* XXX: find a suitable condition to enable the hypervisor decrementer
798 */
799 tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb,
800 cpu);
801 } else {
802 tb_env->hdecr_timer = NULL;
803 }
804 cpu_ppc_set_tb_clk(env, freq);
805
806 return &cpu_ppc_set_tb_clk;
807 }
808
809 /* Specific helpers for POWER & PowerPC 601 RTC */
810 #if 0
811 static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)
812 {
813 return cpu_ppc_tb_init(env, 7812500);
814 }
815 #endif
816
817 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
818 {
819 _cpu_ppc_store_tbu(env, value);
820 }
821
822 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
823 {
824 return _cpu_ppc_load_tbu(env);
825 }
826
827 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
828 {
829 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
830 }
831
832 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
833 {
834 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
835 }
836
837 /*****************************************************************************/
838 /* PowerPC 40x timers */
839
840 /* PIT, FIT & WDT */
841 typedef struct ppc40x_timer_t ppc40x_timer_t;
842 struct ppc40x_timer_t {
843 uint64_t pit_reload; /* PIT auto-reload value */
844 uint64_t fit_next; /* Tick for next FIT interrupt */
845 struct QEMUTimer *fit_timer;
846 uint64_t wdt_next; /* Tick for next WDT interrupt */
847 struct QEMUTimer *wdt_timer;
848
849 /* 405 have the PIT, 440 have a DECR. */
850 unsigned int decr_excp;
851 };
852
853 /* Fixed interval timer */
854 static void cpu_4xx_fit_cb (void *opaque)
855 {
856 PowerPCCPU *cpu;
857 CPUPPCState *env;
858 ppc_tb_t *tb_env;
859 ppc40x_timer_t *ppc40x_timer;
860 uint64_t now, next;
861
862 env = opaque;
863 cpu = ppc_env_get_cpu(env);
864 tb_env = env->tb_env;
865 ppc40x_timer = tb_env->opaque;
866 now = qemu_get_clock_ns(vm_clock);
867 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
868 case 0:
869 next = 1 << 9;
870 break;
871 case 1:
872 next = 1 << 13;
873 break;
874 case 2:
875 next = 1 << 17;
876 break;
877 case 3:
878 next = 1 << 21;
879 break;
880 default:
881 /* Cannot occur, but makes gcc happy */
882 return;
883 }
884 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq);
885 if (next == now)
886 next++;
887 qemu_mod_timer(ppc40x_timer->fit_timer, next);
888 env->spr[SPR_40x_TSR] |= 1 << 26;
889 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
890 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
891 }
892 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
893 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
894 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
895 }
896
897 /* Programmable interval timer */
898 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
899 {
900 ppc40x_timer_t *ppc40x_timer;
901 uint64_t now, next;
902
903 ppc40x_timer = tb_env->opaque;
904 if (ppc40x_timer->pit_reload <= 1 ||
905 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
906 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
907 /* Stop PIT */
908 LOG_TB("%s: stop PIT\n", __func__);
909 qemu_del_timer(tb_env->decr_timer);
910 } else {
911 LOG_TB("%s: start PIT %016" PRIx64 "\n",
912 __func__, ppc40x_timer->pit_reload);
913 now = qemu_get_clock_ns(vm_clock);
914 next = now + muldiv64(ppc40x_timer->pit_reload,
915 get_ticks_per_sec(), tb_env->decr_freq);
916 if (is_excp)
917 next += tb_env->decr_next - now;
918 if (next == now)
919 next++;
920 qemu_mod_timer(tb_env->decr_timer, next);
921 tb_env->decr_next = next;
922 }
923 }
924
925 static void cpu_4xx_pit_cb (void *opaque)
926 {
927 PowerPCCPU *cpu;
928 CPUPPCState *env;
929 ppc_tb_t *tb_env;
930 ppc40x_timer_t *ppc40x_timer;
931
932 env = opaque;
933 cpu = ppc_env_get_cpu(env);
934 tb_env = env->tb_env;
935 ppc40x_timer = tb_env->opaque;
936 env->spr[SPR_40x_TSR] |= 1 << 27;
937 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
938 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
939 }
940 start_stop_pit(env, tb_env, 1);
941 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
942 "%016" PRIx64 "\n", __func__,
943 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
944 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
945 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
946 ppc40x_timer->pit_reload);
947 }
948
949 /* Watchdog timer */
950 static void cpu_4xx_wdt_cb (void *opaque)
951 {
952 PowerPCCPU *cpu;
953 CPUPPCState *env;
954 ppc_tb_t *tb_env;
955 ppc40x_timer_t *ppc40x_timer;
956 uint64_t now, next;
957
958 env = opaque;
959 cpu = ppc_env_get_cpu(env);
960 tb_env = env->tb_env;
961 ppc40x_timer = tb_env->opaque;
962 now = qemu_get_clock_ns(vm_clock);
963 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
964 case 0:
965 next = 1 << 17;
966 break;
967 case 1:
968 next = 1 << 21;
969 break;
970 case 2:
971 next = 1 << 25;
972 break;
973 case 3:
974 next = 1 << 29;
975 break;
976 default:
977 /* Cannot occur, but makes gcc happy */
978 return;
979 }
980 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq);
981 if (next == now)
982 next++;
983 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
984 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
985 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
986 case 0x0:
987 case 0x1:
988 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
989 ppc40x_timer->wdt_next = next;
990 env->spr[SPR_40x_TSR] |= 1 << 31;
991 break;
992 case 0x2:
993 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
994 ppc40x_timer->wdt_next = next;
995 env->spr[SPR_40x_TSR] |= 1 << 30;
996 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
997 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
998 }
999 break;
1000 case 0x3:
1001 env->spr[SPR_40x_TSR] &= ~0x30000000;
1002 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1003 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1004 case 0x0:
1005 /* No reset */
1006 break;
1007 case 0x1: /* Core reset */
1008 ppc40x_core_reset(env);
1009 break;
1010 case 0x2: /* Chip reset */
1011 ppc40x_chip_reset(env);
1012 break;
1013 case 0x3: /* System reset */
1014 ppc40x_system_reset(env);
1015 break;
1016 }
1017 }
1018 }
1019
1020 void store_40x_pit (CPUPPCState *env, target_ulong val)
1021 {
1022 ppc_tb_t *tb_env;
1023 ppc40x_timer_t *ppc40x_timer;
1024
1025 tb_env = env->tb_env;
1026 ppc40x_timer = tb_env->opaque;
1027 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
1028 ppc40x_timer->pit_reload = val;
1029 start_stop_pit(env, tb_env, 0);
1030 }
1031
1032 target_ulong load_40x_pit (CPUPPCState *env)
1033 {
1034 return cpu_ppc_load_decr(env);
1035 }
1036
1037 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1038 {
1039 CPUPPCState *env = opaque;
1040 ppc_tb_t *tb_env = env->tb_env;
1041
1042 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1043 freq);
1044 tb_env->tb_freq = freq;
1045 tb_env->decr_freq = freq;
1046 /* XXX: we should also update all timers */
1047 }
1048
1049 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1050 unsigned int decr_excp)
1051 {
1052 ppc_tb_t *tb_env;
1053 ppc40x_timer_t *ppc40x_timer;
1054
1055 tb_env = g_malloc0(sizeof(ppc_tb_t));
1056 env->tb_env = tb_env;
1057 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1058 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1059 tb_env->tb_freq = freq;
1060 tb_env->decr_freq = freq;
1061 tb_env->opaque = ppc40x_timer;
1062 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1063 if (ppc40x_timer != NULL) {
1064 /* We use decr timer for PIT */
1065 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env);
1066 ppc40x_timer->fit_timer =
1067 qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env);
1068 ppc40x_timer->wdt_timer =
1069 qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env);
1070 ppc40x_timer->decr_excp = decr_excp;
1071 }
1072
1073 return &ppc_40x_set_tb_clk;
1074 }
1075
1076 /*****************************************************************************/
1077 /* Embedded PowerPC Device Control Registers */
1078 typedef struct ppc_dcrn_t ppc_dcrn_t;
1079 struct ppc_dcrn_t {
1080 dcr_read_cb dcr_read;
1081 dcr_write_cb dcr_write;
1082 void *opaque;
1083 };
1084
1085 /* XXX: on 460, DCR addresses are 32 bits wide,
1086 * using DCRIPR to get the 22 upper bits of the DCR address
1087 */
1088 #define DCRN_NB 1024
1089 struct ppc_dcr_t {
1090 ppc_dcrn_t dcrn[DCRN_NB];
1091 int (*read_error)(int dcrn);
1092 int (*write_error)(int dcrn);
1093 };
1094
1095 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1096 {
1097 ppc_dcrn_t *dcr;
1098
1099 if (dcrn < 0 || dcrn >= DCRN_NB)
1100 goto error;
1101 dcr = &dcr_env->dcrn[dcrn];
1102 if (dcr->dcr_read == NULL)
1103 goto error;
1104 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1105
1106 return 0;
1107
1108 error:
1109 if (dcr_env->read_error != NULL)
1110 return (*dcr_env->read_error)(dcrn);
1111
1112 return -1;
1113 }
1114
1115 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1116 {
1117 ppc_dcrn_t *dcr;
1118
1119 if (dcrn < 0 || dcrn >= DCRN_NB)
1120 goto error;
1121 dcr = &dcr_env->dcrn[dcrn];
1122 if (dcr->dcr_write == NULL)
1123 goto error;
1124 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1125
1126 return 0;
1127
1128 error:
1129 if (dcr_env->write_error != NULL)
1130 return (*dcr_env->write_error)(dcrn);
1131
1132 return -1;
1133 }
1134
1135 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1136 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1137 {
1138 ppc_dcr_t *dcr_env;
1139 ppc_dcrn_t *dcr;
1140
1141 dcr_env = env->dcr_env;
1142 if (dcr_env == NULL)
1143 return -1;
1144 if (dcrn < 0 || dcrn >= DCRN_NB)
1145 return -1;
1146 dcr = &dcr_env->dcrn[dcrn];
1147 if (dcr->opaque != NULL ||
1148 dcr->dcr_read != NULL ||
1149 dcr->dcr_write != NULL)
1150 return -1;
1151 dcr->opaque = opaque;
1152 dcr->dcr_read = dcr_read;
1153 dcr->dcr_write = dcr_write;
1154
1155 return 0;
1156 }
1157
1158 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1159 int (*write_error)(int dcrn))
1160 {
1161 ppc_dcr_t *dcr_env;
1162
1163 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1164 dcr_env->read_error = read_error;
1165 dcr_env->write_error = write_error;
1166 env->dcr_env = dcr_env;
1167
1168 return 0;
1169 }
1170
1171 /*****************************************************************************/
1172 /* Debug port */
1173 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1174 {
1175 addr &= 0xF;
1176 switch (addr) {
1177 case 0:
1178 printf("%c", val);
1179 break;
1180 case 1:
1181 printf("\n");
1182 fflush(stdout);
1183 break;
1184 case 2:
1185 printf("Set loglevel to %04" PRIx32 "\n", val);
1186 cpu_set_log(val | 0x100);
1187 break;
1188 }
1189 }
1190
1191 /*****************************************************************************/
1192 /* NVRAM helpers */
1193 static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
1194 {
1195 return (*nvram->read_fn)(nvram->opaque, addr);
1196 }
1197
1198 static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
1199 {
1200 (*nvram->write_fn)(nvram->opaque, addr, val);
1201 }
1202
1203 static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value)
1204 {
1205 nvram_write(nvram, addr, value);
1206 }
1207
1208 static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr)
1209 {
1210 return nvram_read(nvram, addr);
1211 }
1212
1213 static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value)
1214 {
1215 nvram_write(nvram, addr, value >> 8);
1216 nvram_write(nvram, addr + 1, value & 0xFF);
1217 }
1218
1219 static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr)
1220 {
1221 uint16_t tmp;
1222
1223 tmp = nvram_read(nvram, addr) << 8;
1224 tmp |= nvram_read(nvram, addr + 1);
1225
1226 return tmp;
1227 }
1228
1229 static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value)
1230 {
1231 nvram_write(nvram, addr, value >> 24);
1232 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
1233 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
1234 nvram_write(nvram, addr + 3, value & 0xFF);
1235 }
1236
1237 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
1238 {
1239 uint32_t tmp;
1240
1241 tmp = nvram_read(nvram, addr) << 24;
1242 tmp |= nvram_read(nvram, addr + 1) << 16;
1243 tmp |= nvram_read(nvram, addr + 2) << 8;
1244 tmp |= nvram_read(nvram, addr + 3);
1245
1246 return tmp;
1247 }
1248
1249 static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str,
1250 uint32_t max)
1251 {
1252 int i;
1253
1254 for (i = 0; i < max && str[i] != '\0'; i++) {
1255 nvram_write(nvram, addr + i, str[i]);
1256 }
1257 nvram_write(nvram, addr + i, str[i]);
1258 nvram_write(nvram, addr + max - 1, '\0');
1259 }
1260
1261 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
1262 {
1263 int i;
1264
1265 memset(dst, 0, max);
1266 for (i = 0; i < max; i++) {
1267 dst[i] = NVRAM_get_byte(nvram, addr + i);
1268 if (dst[i] == '\0')
1269 break;
1270 }
1271
1272 return i;
1273 }
1274
1275 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1276 {
1277 uint16_t tmp;
1278 uint16_t pd, pd1, pd2;
1279
1280 tmp = prev >> 8;
1281 pd = prev ^ value;
1282 pd1 = pd & 0x000F;
1283 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1284 tmp ^= (pd1 << 3) | (pd1 << 8);
1285 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1286
1287 return tmp;
1288 }
1289
1290 static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
1291 {
1292 uint32_t i;
1293 uint16_t crc = 0xFFFF;
1294 int odd;
1295
1296 odd = count & 1;
1297 count &= ~1;
1298 for (i = 0; i != count; i++) {
1299 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1300 }
1301 if (odd) {
1302 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1303 }
1304
1305 return crc;
1306 }
1307
1308 #define CMDLINE_ADDR 0x017ff000
1309
1310 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1311 const char *arch,
1312 uint32_t RAM_size, int boot_device,
1313 uint32_t kernel_image, uint32_t kernel_size,
1314 const char *cmdline,
1315 uint32_t initrd_image, uint32_t initrd_size,
1316 uint32_t NVRAM_image,
1317 int width, int height, int depth)
1318 {
1319 uint16_t crc;
1320
1321 /* Set parameters for Open Hack'Ware BIOS */
1322 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1323 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1324 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1325 NVRAM_set_string(nvram, 0x20, arch, 16);
1326 NVRAM_set_lword(nvram, 0x30, RAM_size);
1327 NVRAM_set_byte(nvram, 0x34, boot_device);
1328 NVRAM_set_lword(nvram, 0x38, kernel_image);
1329 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1330 if (cmdline) {
1331 /* XXX: put the cmdline in NVRAM too ? */
1332 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
1333 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1334 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1335 } else {
1336 NVRAM_set_lword(nvram, 0x40, 0);
1337 NVRAM_set_lword(nvram, 0x44, 0);
1338 }
1339 NVRAM_set_lword(nvram, 0x48, initrd_image);
1340 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1341 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1342
1343 NVRAM_set_word(nvram, 0x54, width);
1344 NVRAM_set_word(nvram, 0x56, height);
1345 NVRAM_set_word(nvram, 0x58, depth);
1346 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1347 NVRAM_set_word(nvram, 0xFC, crc);
1348
1349 return 0;
1350 }
Qemu with PowerPC KVM improvements