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openpic: export e500 epr enable into a ppc.c function
[qemu/agraf.git] / hw / sun4m.c
blob95c505821ba3f2d5a3e5b03ce9e7d2bc37872435
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu/timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu/sysemu.h"
31 #include "net/net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "sysemu/blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
92 hwaddr serial_base, fd_base;
93 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
94 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 hwaddr bpp_base, dbri_base, sx_base;
96 struct {
97 hwaddr reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 hwaddr ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
112 hwaddr counter_base, nvram_base, ms_kb_base;
113 hwaddr serial_base;
114 hwaddr espdma_base, esp_base;
115 hwaddr ledma_base, le_base;
116 hwaddr tcx_base;
117 hwaddr sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 hwaddr iommu_base, slavio_base;
127 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
128 hwaddr serial_base, fd_base;
129 hwaddr idreg_base, dma_base, esp_base, le_base;
130 hwaddr tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUSPARCState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_kick_irq(SPARCCPU *cpu)
257 {
258 CPUSPARCState *env = &cpu->env;
259
260 env->halted = 0;
261 cpu_check_irqs(env);
262 qemu_cpu_kick(CPU(cpu));
263 }
264
265 static void cpu_set_irq(void *opaque, int irq, int level)
266 {
267 SPARCCPU *cpu = opaque;
268 CPUSPARCState *env = &cpu->env;
269
270 if (level) {
271 trace_sun4m_cpu_set_irq_raise(irq);
272 env->pil_in |= 1 << irq;
273 cpu_kick_irq(cpu);
274 } else {
275 trace_sun4m_cpu_set_irq_lower(irq);
276 env->pil_in &= ~(1 << irq);
277 cpu_check_irqs(env);
278 }
279 }
280
281 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
282 {
283 }
284
285 static void main_cpu_reset(void *opaque)
286 {
287 SPARCCPU *cpu = opaque;
288 CPUSPARCState *env = &cpu->env;
289
290 cpu_reset(CPU(cpu));
291 env->halted = 0;
292 }
293
294 static void secondary_cpu_reset(void *opaque)
295 {
296 SPARCCPU *cpu = opaque;
297 CPUSPARCState *env = &cpu->env;
298
299 cpu_reset(CPU(cpu));
300 env->halted = 1;
301 }
302
303 static void cpu_halt_signal(void *opaque, int irq, int level)
304 {
305 if (level && cpu_single_env)
306 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
307 }
308
309 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
310 {
311 return addr - 0xf0000000ULL;
312 }
313
314 static unsigned long sun4m_load_kernel(const char *kernel_filename,
315 const char *initrd_filename,
316 ram_addr_t RAM_size)
317 {
318 int linux_boot;
319 unsigned int i;
320 long initrd_size, kernel_size;
321 uint8_t *ptr;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 int bswap_needed;
328
329 #ifdef BSWAP_NEEDED
330 bswap_needed = 1;
331 #else
332 bswap_needed = 0;
333 #endif
334 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
335 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
336 if (kernel_size < 0)
337 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
339 TARGET_PAGE_SIZE);
340 if (kernel_size < 0)
341 kernel_size = load_image_targphys(kernel_filename,
342 KERNEL_LOAD_ADDR,
343 RAM_size - KERNEL_LOAD_ADDR);
344 if (kernel_size < 0) {
345 fprintf(stderr, "qemu: could not load kernel '%s'\n",
346 kernel_filename);
347 exit(1);
348 }
349
350 /* load initrd */
351 initrd_size = 0;
352 if (initrd_filename) {
353 initrd_size = load_image_targphys(initrd_filename,
354 INITRD_LOAD_ADDR,
355 RAM_size - INITRD_LOAD_ADDR);
356 if (initrd_size < 0) {
357 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
358 initrd_filename);
359 exit(1);
360 }
361 }
362 if (initrd_size > 0) {
363 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
364 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
365 if (ldl_p(ptr) == 0x48647253) { // HdrS
366 stl_p(ptr + 16, INITRD_LOAD_ADDR);
367 stl_p(ptr + 20, initrd_size);
368 break;
369 }
370 }
371 }
372 }
373 return kernel_size;
374 }
375
376 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
377 {
378 DeviceState *dev;
379 SysBusDevice *s;
380
381 dev = qdev_create(NULL, "iommu");
382 qdev_prop_set_uint32(dev, "version", version);
383 qdev_init_nofail(dev);
384 s = sysbus_from_qdev(dev);
385 sysbus_connect_irq(s, 0, irq);
386 sysbus_mmio_map(s, 0, addr);
387
388 return s;
389 }
390
391 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
392 void *iommu, qemu_irq *dev_irq, int is_ledma)
393 {
394 DeviceState *dev;
395 SysBusDevice *s;
396
397 dev = qdev_create(NULL, "sparc32_dma");
398 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
399 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
400 qdev_init_nofail(dev);
401 s = sysbus_from_qdev(dev);
402 sysbus_connect_irq(s, 0, parent_irq);
403 *dev_irq = qdev_get_gpio_in(dev, 0);
404 sysbus_mmio_map(s, 0, daddr);
405
406 return s;
407 }
408
409 static void lance_init(NICInfo *nd, hwaddr leaddr,
410 void *dma_opaque, qemu_irq irq)
411 {
412 DeviceState *dev;
413 SysBusDevice *s;
414 qemu_irq reset;
415
416 qemu_check_nic_model(&nd_table[0], "lance");
417
418 dev = qdev_create(NULL, "lance");
419 qdev_set_nic_properties(dev, nd);
420 qdev_prop_set_ptr(dev, "dma", dma_opaque);
421 qdev_init_nofail(dev);
422 s = sysbus_from_qdev(dev);
423 sysbus_mmio_map(s, 0, leaddr);
424 sysbus_connect_irq(s, 0, irq);
425 reset = qdev_get_gpio_in(dev, 0);
426 qdev_connect_gpio_out(dma_opaque, 0, reset);
427 }
428
429 static DeviceState *slavio_intctl_init(hwaddr addr,
430 hwaddr addrg,
431 qemu_irq **parent_irq)
432 {
433 DeviceState *dev;
434 SysBusDevice *s;
435 unsigned int i, j;
436
437 dev = qdev_create(NULL, "slavio_intctl");
438 qdev_init_nofail(dev);
439
440 s = sysbus_from_qdev(dev);
441
442 for (i = 0; i < MAX_CPUS; i++) {
443 for (j = 0; j < MAX_PILS; j++) {
444 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
445 }
446 }
447 sysbus_mmio_map(s, 0, addrg);
448 for (i = 0; i < MAX_CPUS; i++) {
449 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
450 }
451
452 return dev;
453 }
454
455 #define SYS_TIMER_OFFSET 0x10000ULL
456 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
457
458 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
459 qemu_irq *cpu_irqs, unsigned int num_cpus)
460 {
461 DeviceState *dev;
462 SysBusDevice *s;
463 unsigned int i;
464
465 dev = qdev_create(NULL, "slavio_timer");
466 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
467 qdev_init_nofail(dev);
468 s = sysbus_from_qdev(dev);
469 sysbus_connect_irq(s, 0, master_irq);
470 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
471
472 for (i = 0; i < MAX_CPUS; i++) {
473 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
474 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
475 }
476 }
477
478 static qemu_irq slavio_system_powerdown;
479
480 static void slavio_powerdown_req(Notifier *n, void *opaque)
481 {
482 qemu_irq_raise(slavio_system_powerdown);
483 }
484
485 static Notifier slavio_system_powerdown_notifier = {
486 .notify = slavio_powerdown_req
487 };
488
489 #define MISC_LEDS 0x01600000
490 #define MISC_CFG 0x01800000
491 #define MISC_DIAG 0x01a00000
492 #define MISC_MDM 0x01b00000
493 #define MISC_SYS 0x01f00000
494
495 static void slavio_misc_init(hwaddr base,
496 hwaddr aux1_base,
497 hwaddr aux2_base, qemu_irq irq,
498 qemu_irq fdc_tc)
499 {
500 DeviceState *dev;
501 SysBusDevice *s;
502
503 dev = qdev_create(NULL, "slavio_misc");
504 qdev_init_nofail(dev);
505 s = sysbus_from_qdev(dev);
506 if (base) {
507 /* 8 bit registers */
508 /* Slavio control */
509 sysbus_mmio_map(s, 0, base + MISC_CFG);
510 /* Diagnostics */
511 sysbus_mmio_map(s, 1, base + MISC_DIAG);
512 /* Modem control */
513 sysbus_mmio_map(s, 2, base + MISC_MDM);
514 /* 16 bit registers */
515 /* ss600mp diag LEDs */
516 sysbus_mmio_map(s, 3, base + MISC_LEDS);
517 /* 32 bit registers */
518 /* System control */
519 sysbus_mmio_map(s, 4, base + MISC_SYS);
520 }
521 if (aux1_base) {
522 /* AUX 1 (Misc System Functions) */
523 sysbus_mmio_map(s, 5, aux1_base);
524 }
525 if (aux2_base) {
526 /* AUX 2 (Software Powerdown Control) */
527 sysbus_mmio_map(s, 6, aux2_base);
528 }
529 sysbus_connect_irq(s, 0, irq);
530 sysbus_connect_irq(s, 1, fdc_tc);
531 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
532 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
533 }
534
535 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
536 {
537 DeviceState *dev;
538 SysBusDevice *s;
539
540 dev = qdev_create(NULL, "eccmemctl");
541 qdev_prop_set_uint32(dev, "version", version);
542 qdev_init_nofail(dev);
543 s = sysbus_from_qdev(dev);
544 sysbus_connect_irq(s, 0, irq);
545 sysbus_mmio_map(s, 0, base);
546 if (version == 0) { // SS-600MP only
547 sysbus_mmio_map(s, 1, base + 0x1000);
548 }
549 }
550
551 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
552 {
553 DeviceState *dev;
554 SysBusDevice *s;
555
556 dev = qdev_create(NULL, "apc");
557 qdev_init_nofail(dev);
558 s = sysbus_from_qdev(dev);
559 /* Power management (APC) XXX: not a Slavio device */
560 sysbus_mmio_map(s, 0, power_base);
561 sysbus_connect_irq(s, 0, cpu_halt);
562 }
563
564 static void tcx_init(hwaddr addr, int vram_size, int width,
565 int height, int depth)
566 {
567 DeviceState *dev;
568 SysBusDevice *s;
569
570 dev = qdev_create(NULL, "SUNW,tcx");
571 qdev_prop_set_taddr(dev, "addr", addr);
572 qdev_prop_set_uint32(dev, "vram_size", vram_size);
573 qdev_prop_set_uint16(dev, "width", width);
574 qdev_prop_set_uint16(dev, "height", height);
575 qdev_prop_set_uint16(dev, "depth", depth);
576 qdev_init_nofail(dev);
577 s = sysbus_from_qdev(dev);
578 /* 8-bit plane */
579 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
580 /* DAC */
581 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
582 /* TEC (dummy) */
583 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
584 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
585 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
586 if (depth == 24) {
587 /* 24-bit plane */
588 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
589 /* Control plane */
590 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
591 } else {
592 /* THC 8 bit (dummy) */
593 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
594 }
595 }
596
597 /* NCR89C100/MACIO Internal ID register */
598 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
599
600 static void idreg_init(hwaddr addr)
601 {
602 DeviceState *dev;
603 SysBusDevice *s;
604
605 dev = qdev_create(NULL, "macio_idreg");
606 qdev_init_nofail(dev);
607 s = sysbus_from_qdev(dev);
608
609 sysbus_mmio_map(s, 0, addr);
610 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
611 }
612
613 typedef struct IDRegState {
614 SysBusDevice busdev;
615 MemoryRegion mem;
616 } IDRegState;
617
618 static int idreg_init1(SysBusDevice *dev)
619 {
620 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
621
622 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
623 vmstate_register_ram_global(&s->mem);
624 memory_region_set_readonly(&s->mem, true);
625 sysbus_init_mmio(dev, &s->mem);
626 return 0;
627 }
628
629 static void idreg_class_init(ObjectClass *klass, void *data)
630 {
631 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
632
633 k->init = idreg_init1;
634 }
635
636 static const TypeInfo idreg_info = {
637 .name = "macio_idreg",
638 .parent = TYPE_SYS_BUS_DEVICE,
639 .instance_size = sizeof(IDRegState),
640 .class_init = idreg_class_init,
641 };
642
643 typedef struct AFXState {
644 SysBusDevice busdev;
645 MemoryRegion mem;
646 } AFXState;
647
648 /* SS-5 TCX AFX register */
649 static void afx_init(hwaddr addr)
650 {
651 DeviceState *dev;
652 SysBusDevice *s;
653
654 dev = qdev_create(NULL, "tcx_afx");
655 qdev_init_nofail(dev);
656 s = sysbus_from_qdev(dev);
657
658 sysbus_mmio_map(s, 0, addr);
659 }
660
661 static int afx_init1(SysBusDevice *dev)
662 {
663 AFXState *s = FROM_SYSBUS(AFXState, dev);
664
665 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
666 vmstate_register_ram_global(&s->mem);
667 sysbus_init_mmio(dev, &s->mem);
668 return 0;
669 }
670
671 static void afx_class_init(ObjectClass *klass, void *data)
672 {
673 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
674
675 k->init = afx_init1;
676 }
677
678 static const TypeInfo afx_info = {
679 .name = "tcx_afx",
680 .parent = TYPE_SYS_BUS_DEVICE,
681 .instance_size = sizeof(AFXState),
682 .class_init = afx_class_init,
683 };
684
685 typedef struct PROMState {
686 SysBusDevice busdev;
687 MemoryRegion prom;
688 } PROMState;
689
690 /* Boot PROM (OpenBIOS) */
691 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
692 {
693 hwaddr *base_addr = (hwaddr *)opaque;
694 return addr + *base_addr - PROM_VADDR;
695 }
696
697 static void prom_init(hwaddr addr, const char *bios_name)
698 {
699 DeviceState *dev;
700 SysBusDevice *s;
701 char *filename;
702 int ret;
703
704 dev = qdev_create(NULL, "openprom");
705 qdev_init_nofail(dev);
706 s = sysbus_from_qdev(dev);
707
708 sysbus_mmio_map(s, 0, addr);
709
710 /* load boot prom */
711 if (bios_name == NULL) {
712 bios_name = PROM_FILENAME;
713 }
714 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
715 if (filename) {
716 ret = load_elf(filename, translate_prom_address, &addr, NULL,
717 NULL, NULL, 1, ELF_MACHINE, 0);
718 if (ret < 0 || ret > PROM_SIZE_MAX) {
719 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
720 }
721 g_free(filename);
722 } else {
723 ret = -1;
724 }
725 if (ret < 0 || ret > PROM_SIZE_MAX) {
726 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
727 exit(1);
728 }
729 }
730
731 static int prom_init1(SysBusDevice *dev)
732 {
733 PROMState *s = FROM_SYSBUS(PROMState, dev);
734
735 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
736 vmstate_register_ram_global(&s->prom);
737 memory_region_set_readonly(&s->prom, true);
738 sysbus_init_mmio(dev, &s->prom);
739 return 0;
740 }
741
742 static Property prom_properties[] = {
743 {/* end of property list */},
744 };
745
746 static void prom_class_init(ObjectClass *klass, void *data)
747 {
748 DeviceClass *dc = DEVICE_CLASS(klass);
749 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
750
751 k->init = prom_init1;
752 dc->props = prom_properties;
753 }
754
755 static const TypeInfo prom_info = {
756 .name = "openprom",
757 .parent = TYPE_SYS_BUS_DEVICE,
758 .instance_size = sizeof(PROMState),
759 .class_init = prom_class_init,
760 };
761
762 typedef struct RamDevice
763 {
764 SysBusDevice busdev;
765 MemoryRegion ram;
766 uint64_t size;
767 } RamDevice;
768
769 /* System RAM */
770 static int ram_init1(SysBusDevice *dev)
771 {
772 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
773
774 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
775 vmstate_register_ram_global(&d->ram);
776 sysbus_init_mmio(dev, &d->ram);
777 return 0;
778 }
779
780 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
781 uint64_t max_mem)
782 {
783 DeviceState *dev;
784 SysBusDevice *s;
785 RamDevice *d;
786
787 /* allocate RAM */
788 if ((uint64_t)RAM_size > max_mem) {
789 fprintf(stderr,
790 "qemu: Too much memory for this machine: %d, maximum %d\n",
791 (unsigned int)(RAM_size / (1024 * 1024)),
792 (unsigned int)(max_mem / (1024 * 1024)));
793 exit(1);
794 }
795 dev = qdev_create(NULL, "memory");
796 s = sysbus_from_qdev(dev);
797
798 d = FROM_SYSBUS(RamDevice, s);
799 d->size = RAM_size;
800 qdev_init_nofail(dev);
801
802 sysbus_mmio_map(s, 0, addr);
803 }
804
805 static Property ram_properties[] = {
806 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
807 DEFINE_PROP_END_OF_LIST(),
808 };
809
810 static void ram_class_init(ObjectClass *klass, void *data)
811 {
812 DeviceClass *dc = DEVICE_CLASS(klass);
813 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
814
815 k->init = ram_init1;
816 dc->props = ram_properties;
817 }
818
819 static const TypeInfo ram_info = {
820 .name = "memory",
821 .parent = TYPE_SYS_BUS_DEVICE,
822 .instance_size = sizeof(RamDevice),
823 .class_init = ram_class_init,
824 };
825
826 static void cpu_devinit(const char *cpu_model, unsigned int id,
827 uint64_t prom_addr, qemu_irq **cpu_irqs)
828 {
829 SPARCCPU *cpu;
830 CPUSPARCState *env;
831
832 cpu = cpu_sparc_init(cpu_model);
833 if (cpu == NULL) {
834 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
835 exit(1);
836 }
837 env = &cpu->env;
838
839 cpu_sparc_set_id(env, id);
840 if (id == 0) {
841 qemu_register_reset(main_cpu_reset, cpu);
842 } else {
843 qemu_register_reset(secondary_cpu_reset, cpu);
844 env->halted = 1;
845 }
846 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
847 env->prom_addr = prom_addr;
848 }
849
850 static void dummy_fdc_tc(void *opaque, int irq, int level)
851 {
852 }
853
854 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
855 const char *boot_device,
856 const char *kernel_filename,
857 const char *kernel_cmdline,
858 const char *initrd_filename, const char *cpu_model)
859 {
860 unsigned int i;
861 void *iommu, *espdma, *ledma, *nvram;
862 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
863 espdma_irq, ledma_irq;
864 qemu_irq esp_reset, dma_enable;
865 qemu_irq fdc_tc;
866 qemu_irq *cpu_halt;
867 unsigned long kernel_size;
868 DriveInfo *fd[MAX_FD];
869 void *fw_cfg;
870 unsigned int num_vsimms;
871
872 /* init CPUs */
873 if (!cpu_model)
874 cpu_model = hwdef->default_cpu_model;
875
876 for(i = 0; i < smp_cpus; i++) {
877 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
878 }
879
880 for (i = smp_cpus; i < MAX_CPUS; i++)
881 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
882
883
884 /* set up devices */
885 ram_init(0, RAM_size, hwdef->max_mem);
886 /* models without ECC don't trap when missing ram is accessed */
887 if (!hwdef->ecc_base) {
888 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
889 }
890
891 prom_init(hwdef->slavio_base, bios_name);
892
893 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
894 hwdef->intctl_base + 0x10000ULL,
895 cpu_irqs);
896
897 for (i = 0; i < 32; i++) {
898 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
899 }
900 for (i = 0; i < MAX_CPUS; i++) {
901 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
902 }
903
904 if (hwdef->idreg_base) {
905 idreg_init(hwdef->idreg_base);
906 }
907
908 if (hwdef->afx_base) {
909 afx_init(hwdef->afx_base);
910 }
911
912 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
913 slavio_irq[30]);
914
915 if (hwdef->iommu_pad_base) {
916 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
917 Software shouldn't use aliased addresses, neither should it crash
918 when does. Using empty_slot instead of aliasing can help with
919 debugging such accesses */
920 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
921 }
922
923 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
924 iommu, &espdma_irq, 0);
925
926 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
927 slavio_irq[16], iommu, &ledma_irq, 1);
928
929 if (graphic_depth != 8 && graphic_depth != 24) {
930 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
931 exit (1);
932 }
933 num_vsimms = 0;
934 if (num_vsimms == 0) {
935 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
936 graphic_depth);
937 }
938
939 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
940 /* vsimm registers probed by OBP */
941 if (hwdef->vsimm[i].reg_base) {
942 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
943 }
944 }
945
946 if (hwdef->sx_base) {
947 empty_slot_init(hwdef->sx_base, 0x2000);
948 }
949
950 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
951
952 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
953
954 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
955
956 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
957 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
958 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
959 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
960 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
961 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
962
963 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
964 if (hwdef->apc_base) {
965 apc_init(hwdef->apc_base, cpu_halt[0]);
966 }
967
968 if (hwdef->fd_base) {
969 /* there is zero or one floppy drive */
970 memset(fd, 0, sizeof(fd));
971 fd[0] = drive_get(IF_FLOPPY, 0, 0);
972 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
973 &fdc_tc);
974 } else {
975 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
976 }
977
978 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
979 slavio_irq[30], fdc_tc);
980
981 if (drive_get_max_bus(IF_SCSI) > 0) {
982 fprintf(stderr, "qemu: too many SCSI bus\n");
983 exit(1);
984 }
985
986 esp_init(hwdef->esp_base, 2,
987 espdma_memory_read, espdma_memory_write,
988 espdma, espdma_irq, &esp_reset, &dma_enable);
989
990 qdev_connect_gpio_out(espdma, 0, esp_reset);
991 qdev_connect_gpio_out(espdma, 1, dma_enable);
992
993 if (hwdef->cs_base) {
994 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
995 slavio_irq[5]);
996 }
997
998 if (hwdef->dbri_base) {
999 /* ISDN chip with attached CS4215 audio codec */
1000 /* prom space */
1001 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1002 /* reg space */
1003 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1004 }
1005
1006 if (hwdef->bpp_base) {
1007 /* parallel port */
1008 empty_slot_init(hwdef->bpp_base, 0x20);
1009 }
1010
1011 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1012 RAM_size);
1013
1014 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1015 boot_device, RAM_size, kernel_size, graphic_width,
1016 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1017 "Sun4m");
1018
1019 if (hwdef->ecc_base)
1020 ecc_init(hwdef->ecc_base, slavio_irq[28],
1021 hwdef->ecc_version);
1022
1023 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1024 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1025 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1026 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1027 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1028 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1029 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1030 if (kernel_cmdline) {
1031 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1032 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1033 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1034 (uint8_t*)strdup(kernel_cmdline),
1035 strlen(kernel_cmdline) + 1);
1036 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1037 strlen(kernel_cmdline) + 1);
1038 } else {
1039 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1040 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1041 }
1042 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1043 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1044 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1045 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1046 }
1047
1048 enum {
1049 ss2_id = 0,
1050 ss5_id = 32,
1051 vger_id,
1052 lx_id,
1053 ss4_id,
1054 scls_id,
1055 sbook_id,
1056 ss10_id = 64,
1057 ss20_id,
1058 ss600mp_id,
1059 ss1000_id = 96,
1060 ss2000_id,
1061 };
1062
1063 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1064 /* SS-5 */
1065 {
1066 .iommu_base = 0x10000000,
1067 .iommu_pad_base = 0x10004000,
1068 .iommu_pad_len = 0x0fffb000,
1069 .tcx_base = 0x50000000,
1070 .cs_base = 0x6c000000,
1071 .slavio_base = 0x70000000,
1072 .ms_kb_base = 0x71000000,
1073 .serial_base = 0x71100000,
1074 .nvram_base = 0x71200000,
1075 .fd_base = 0x71400000,
1076 .counter_base = 0x71d00000,
1077 .intctl_base = 0x71e00000,
1078 .idreg_base = 0x78000000,
1079 .dma_base = 0x78400000,
1080 .esp_base = 0x78800000,
1081 .le_base = 0x78c00000,
1082 .apc_base = 0x6a000000,
1083 .afx_base = 0x6e000000,
1084 .aux1_base = 0x71900000,
1085 .aux2_base = 0x71910000,
1086 .nvram_machine_id = 0x80,
1087 .machine_id = ss5_id,
1088 .iommu_version = 0x05000000,
1089 .max_mem = 0x10000000,
1090 .default_cpu_model = "Fujitsu MB86904",
1091 },
1092 /* SS-10 */
1093 {
1094 .iommu_base = 0xfe0000000ULL,
1095 .tcx_base = 0xe20000000ULL,
1096 .slavio_base = 0xff0000000ULL,
1097 .ms_kb_base = 0xff1000000ULL,
1098 .serial_base = 0xff1100000ULL,
1099 .nvram_base = 0xff1200000ULL,
1100 .fd_base = 0xff1700000ULL,
1101 .counter_base = 0xff1300000ULL,
1102 .intctl_base = 0xff1400000ULL,
1103 .idreg_base = 0xef0000000ULL,
1104 .dma_base = 0xef0400000ULL,
1105 .esp_base = 0xef0800000ULL,
1106 .le_base = 0xef0c00000ULL,
1107 .apc_base = 0xefa000000ULL, // XXX should not exist
1108 .aux1_base = 0xff1800000ULL,
1109 .aux2_base = 0xff1a01000ULL,
1110 .ecc_base = 0xf00000000ULL,
1111 .ecc_version = 0x10000000, // version 0, implementation 1
1112 .nvram_machine_id = 0x72,
1113 .machine_id = ss10_id,
1114 .iommu_version = 0x03000000,
1115 .max_mem = 0xf00000000ULL,
1116 .default_cpu_model = "TI SuperSparc II",
1117 },
1118 /* SS-600MP */
1119 {
1120 .iommu_base = 0xfe0000000ULL,
1121 .tcx_base = 0xe20000000ULL,
1122 .slavio_base = 0xff0000000ULL,
1123 .ms_kb_base = 0xff1000000ULL,
1124 .serial_base = 0xff1100000ULL,
1125 .nvram_base = 0xff1200000ULL,
1126 .counter_base = 0xff1300000ULL,
1127 .intctl_base = 0xff1400000ULL,
1128 .dma_base = 0xef0081000ULL,
1129 .esp_base = 0xef0080000ULL,
1130 .le_base = 0xef0060000ULL,
1131 .apc_base = 0xefa000000ULL, // XXX should not exist
1132 .aux1_base = 0xff1800000ULL,
1133 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1134 .ecc_base = 0xf00000000ULL,
1135 .ecc_version = 0x00000000, // version 0, implementation 0
1136 .nvram_machine_id = 0x71,
1137 .machine_id = ss600mp_id,
1138 .iommu_version = 0x01000000,
1139 .max_mem = 0xf00000000ULL,
1140 .default_cpu_model = "TI SuperSparc II",
1141 },
1142 /* SS-20 */
1143 {
1144 .iommu_base = 0xfe0000000ULL,
1145 .tcx_base = 0xe20000000ULL,
1146 .slavio_base = 0xff0000000ULL,
1147 .ms_kb_base = 0xff1000000ULL,
1148 .serial_base = 0xff1100000ULL,
1149 .nvram_base = 0xff1200000ULL,
1150 .fd_base = 0xff1700000ULL,
1151 .counter_base = 0xff1300000ULL,
1152 .intctl_base = 0xff1400000ULL,
1153 .idreg_base = 0xef0000000ULL,
1154 .dma_base = 0xef0400000ULL,
1155 .esp_base = 0xef0800000ULL,
1156 .le_base = 0xef0c00000ULL,
1157 .bpp_base = 0xef4800000ULL,
1158 .apc_base = 0xefa000000ULL, // XXX should not exist
1159 .aux1_base = 0xff1800000ULL,
1160 .aux2_base = 0xff1a01000ULL,
1161 .dbri_base = 0xee0000000ULL,
1162 .sx_base = 0xf80000000ULL,
1163 .vsimm = {
1164 {
1165 .reg_base = 0x9c000000ULL,
1166 .vram_base = 0xfc000000ULL
1167 }, {
1168 .reg_base = 0x90000000ULL,
1169 .vram_base = 0xf0000000ULL
1170 }, {
1171 .reg_base = 0x94000000ULL
1172 }, {
1173 .reg_base = 0x98000000ULL
1174 }
1175 },
1176 .ecc_base = 0xf00000000ULL,
1177 .ecc_version = 0x20000000, // version 0, implementation 2
1178 .nvram_machine_id = 0x72,
1179 .machine_id = ss20_id,
1180 .iommu_version = 0x13000000,
1181 .max_mem = 0xf00000000ULL,
1182 .default_cpu_model = "TI SuperSparc II",
1183 },
1184 /* Voyager */
1185 {
1186 .iommu_base = 0x10000000,
1187 .tcx_base = 0x50000000,
1188 .slavio_base = 0x70000000,
1189 .ms_kb_base = 0x71000000,
1190 .serial_base = 0x71100000,
1191 .nvram_base = 0x71200000,
1192 .fd_base = 0x71400000,
1193 .counter_base = 0x71d00000,
1194 .intctl_base = 0x71e00000,
1195 .idreg_base = 0x78000000,
1196 .dma_base = 0x78400000,
1197 .esp_base = 0x78800000,
1198 .le_base = 0x78c00000,
1199 .apc_base = 0x71300000, // pmc
1200 .aux1_base = 0x71900000,
1201 .aux2_base = 0x71910000,
1202 .nvram_machine_id = 0x80,
1203 .machine_id = vger_id,
1204 .iommu_version = 0x05000000,
1205 .max_mem = 0x10000000,
1206 .default_cpu_model = "Fujitsu MB86904",
1207 },
1208 /* LX */
1209 {
1210 .iommu_base = 0x10000000,
1211 .iommu_pad_base = 0x10004000,
1212 .iommu_pad_len = 0x0fffb000,
1213 .tcx_base = 0x50000000,
1214 .slavio_base = 0x70000000,
1215 .ms_kb_base = 0x71000000,
1216 .serial_base = 0x71100000,
1217 .nvram_base = 0x71200000,
1218 .fd_base = 0x71400000,
1219 .counter_base = 0x71d00000,
1220 .intctl_base = 0x71e00000,
1221 .idreg_base = 0x78000000,
1222 .dma_base = 0x78400000,
1223 .esp_base = 0x78800000,
1224 .le_base = 0x78c00000,
1225 .aux1_base = 0x71900000,
1226 .aux2_base = 0x71910000,
1227 .nvram_machine_id = 0x80,
1228 .machine_id = lx_id,
1229 .iommu_version = 0x04000000,
1230 .max_mem = 0x10000000,
1231 .default_cpu_model = "TI MicroSparc I",
1232 },
1233 /* SS-4 */
1234 {
1235 .iommu_base = 0x10000000,
1236 .tcx_base = 0x50000000,
1237 .cs_base = 0x6c000000,
1238 .slavio_base = 0x70000000,
1239 .ms_kb_base = 0x71000000,
1240 .serial_base = 0x71100000,
1241 .nvram_base = 0x71200000,
1242 .fd_base = 0x71400000,
1243 .counter_base = 0x71d00000,
1244 .intctl_base = 0x71e00000,
1245 .idreg_base = 0x78000000,
1246 .dma_base = 0x78400000,
1247 .esp_base = 0x78800000,
1248 .le_base = 0x78c00000,
1249 .apc_base = 0x6a000000,
1250 .aux1_base = 0x71900000,
1251 .aux2_base = 0x71910000,
1252 .nvram_machine_id = 0x80,
1253 .machine_id = ss4_id,
1254 .iommu_version = 0x05000000,
1255 .max_mem = 0x10000000,
1256 .default_cpu_model = "Fujitsu MB86904",
1257 },
1258 /* SPARCClassic */
1259 {
1260 .iommu_base = 0x10000000,
1261 .tcx_base = 0x50000000,
1262 .slavio_base = 0x70000000,
1263 .ms_kb_base = 0x71000000,
1264 .serial_base = 0x71100000,
1265 .nvram_base = 0x71200000,
1266 .fd_base = 0x71400000,
1267 .counter_base = 0x71d00000,
1268 .intctl_base = 0x71e00000,
1269 .idreg_base = 0x78000000,
1270 .dma_base = 0x78400000,
1271 .esp_base = 0x78800000,
1272 .le_base = 0x78c00000,
1273 .apc_base = 0x6a000000,
1274 .aux1_base = 0x71900000,
1275 .aux2_base = 0x71910000,
1276 .nvram_machine_id = 0x80,
1277 .machine_id = scls_id,
1278 .iommu_version = 0x05000000,
1279 .max_mem = 0x10000000,
1280 .default_cpu_model = "TI MicroSparc I",
1281 },
1282 /* SPARCbook */
1283 {
1284 .iommu_base = 0x10000000,
1285 .tcx_base = 0x50000000, // XXX
1286 .slavio_base = 0x70000000,
1287 .ms_kb_base = 0x71000000,
1288 .serial_base = 0x71100000,
1289 .nvram_base = 0x71200000,
1290 .fd_base = 0x71400000,
1291 .counter_base = 0x71d00000,
1292 .intctl_base = 0x71e00000,
1293 .idreg_base = 0x78000000,
1294 .dma_base = 0x78400000,
1295 .esp_base = 0x78800000,
1296 .le_base = 0x78c00000,
1297 .apc_base = 0x6a000000,
1298 .aux1_base = 0x71900000,
1299 .aux2_base = 0x71910000,
1300 .nvram_machine_id = 0x80,
1301 .machine_id = sbook_id,
1302 .iommu_version = 0x05000000,
1303 .max_mem = 0x10000000,
1304 .default_cpu_model = "TI MicroSparc I",
1305 },
1306 };
1307
1308 /* SPARCstation 5 hardware initialisation */
1309 static void ss5_init(QEMUMachineInitArgs *args)
1310 {
1311 ram_addr_t RAM_size = args->ram_size;
1312 const char *cpu_model = args->cpu_model;
1313 const char *kernel_filename = args->kernel_filename;
1314 const char *kernel_cmdline = args->kernel_cmdline;
1315 const char *initrd_filename = args->initrd_filename;
1316 const char *boot_device = args->boot_device;
1317 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1318 kernel_cmdline, initrd_filename, cpu_model);
1319 }
1320
1321 /* SPARCstation 10 hardware initialisation */
1322 static void ss10_init(QEMUMachineInitArgs *args)
1323 {
1324 ram_addr_t RAM_size = args->ram_size;
1325 const char *cpu_model = args->cpu_model;
1326 const char *kernel_filename = args->kernel_filename;
1327 const char *kernel_cmdline = args->kernel_cmdline;
1328 const char *initrd_filename = args->initrd_filename;
1329 const char *boot_device = args->boot_device;
1330 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1331 kernel_cmdline, initrd_filename, cpu_model);
1332 }
1333
1334 /* SPARCserver 600MP hardware initialisation */
1335 static void ss600mp_init(QEMUMachineInitArgs *args)
1336 {
1337 ram_addr_t RAM_size = args->ram_size;
1338 const char *cpu_model = args->cpu_model;
1339 const char *kernel_filename = args->kernel_filename;
1340 const char *kernel_cmdline = args->kernel_cmdline;
1341 const char *initrd_filename = args->initrd_filename;
1342 const char *boot_device = args->boot_device;
1343 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1344 kernel_cmdline, initrd_filename, cpu_model);
1345 }
1346
1347 /* SPARCstation 20 hardware initialisation */
1348 static void ss20_init(QEMUMachineInitArgs *args)
1349 {
1350 ram_addr_t RAM_size = args->ram_size;
1351 const char *cpu_model = args->cpu_model;
1352 const char *kernel_filename = args->kernel_filename;
1353 const char *kernel_cmdline = args->kernel_cmdline;
1354 const char *initrd_filename = args->initrd_filename;
1355 const char *boot_device = args->boot_device;
1356 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1357 kernel_cmdline, initrd_filename, cpu_model);
1358 }
1359
1360 /* SPARCstation Voyager hardware initialisation */
1361 static void vger_init(QEMUMachineInitArgs *args)
1362 {
1363 ram_addr_t RAM_size = args->ram_size;
1364 const char *cpu_model = args->cpu_model;
1365 const char *kernel_filename = args->kernel_filename;
1366 const char *kernel_cmdline = args->kernel_cmdline;
1367 const char *initrd_filename = args->initrd_filename;
1368 const char *boot_device = args->boot_device;
1369 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1370 kernel_cmdline, initrd_filename, cpu_model);
1371 }
1372
1373 /* SPARCstation LX hardware initialisation */
1374 static void ss_lx_init(QEMUMachineInitArgs *args)
1375 {
1376 ram_addr_t RAM_size = args->ram_size;
1377 const char *cpu_model = args->cpu_model;
1378 const char *kernel_filename = args->kernel_filename;
1379 const char *kernel_cmdline = args->kernel_cmdline;
1380 const char *initrd_filename = args->initrd_filename;
1381 const char *boot_device = args->boot_device;
1382 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1383 kernel_cmdline, initrd_filename, cpu_model);
1384 }
1385
1386 /* SPARCstation 4 hardware initialisation */
1387 static void ss4_init(QEMUMachineInitArgs *args)
1388 {
1389 ram_addr_t RAM_size = args->ram_size;
1390 const char *cpu_model = args->cpu_model;
1391 const char *kernel_filename = args->kernel_filename;
1392 const char *kernel_cmdline = args->kernel_cmdline;
1393 const char *initrd_filename = args->initrd_filename;
1394 const char *boot_device = args->boot_device;
1395 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1396 kernel_cmdline, initrd_filename, cpu_model);
1397 }
1398
1399 /* SPARCClassic hardware initialisation */
1400 static void scls_init(QEMUMachineInitArgs *args)
1401 {
1402 ram_addr_t RAM_size = args->ram_size;
1403 const char *cpu_model = args->cpu_model;
1404 const char *kernel_filename = args->kernel_filename;
1405 const char *kernel_cmdline = args->kernel_cmdline;
1406 const char *initrd_filename = args->initrd_filename;
1407 const char *boot_device = args->boot_device;
1408 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1409 kernel_cmdline, initrd_filename, cpu_model);
1410 }
1411
1412 /* SPARCbook hardware initialisation */
1413 static void sbook_init(QEMUMachineInitArgs *args)
1414 {
1415 ram_addr_t RAM_size = args->ram_size;
1416 const char *cpu_model = args->cpu_model;
1417 const char *kernel_filename = args->kernel_filename;
1418 const char *kernel_cmdline = args->kernel_cmdline;
1419 const char *initrd_filename = args->initrd_filename;
1420 const char *boot_device = args->boot_device;
1421 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1422 kernel_cmdline, initrd_filename, cpu_model);
1423 }
1424
1425 static QEMUMachine ss5_machine = {
1426 .name = "SS-5",
1427 .desc = "Sun4m platform, SPARCstation 5",
1428 .init = ss5_init,
1429 .block_default_type = IF_SCSI,
1430 .is_default = 1,
1431 DEFAULT_MACHINE_OPTIONS,
1432 };
1433
1434 static QEMUMachine ss10_machine = {
1435 .name = "SS-10",
1436 .desc = "Sun4m platform, SPARCstation 10",
1437 .init = ss10_init,
1438 .block_default_type = IF_SCSI,
1439 .max_cpus = 4,
1440 DEFAULT_MACHINE_OPTIONS,
1441 };
1442
1443 static QEMUMachine ss600mp_machine = {
1444 .name = "SS-600MP",
1445 .desc = "Sun4m platform, SPARCserver 600MP",
1446 .init = ss600mp_init,
1447 .block_default_type = IF_SCSI,
1448 .max_cpus = 4,
1449 DEFAULT_MACHINE_OPTIONS,
1450 };
1451
1452 static QEMUMachine ss20_machine = {
1453 .name = "SS-20",
1454 .desc = "Sun4m platform, SPARCstation 20",
1455 .init = ss20_init,
1456 .block_default_type = IF_SCSI,
1457 .max_cpus = 4,
1458 DEFAULT_MACHINE_OPTIONS,
1459 };
1460
1461 static QEMUMachine voyager_machine = {
1462 .name = "Voyager",
1463 .desc = "Sun4m platform, SPARCstation Voyager",
1464 .init = vger_init,
1465 .block_default_type = IF_SCSI,
1466 DEFAULT_MACHINE_OPTIONS,
1467 };
1468
1469 static QEMUMachine ss_lx_machine = {
1470 .name = "LX",
1471 .desc = "Sun4m platform, SPARCstation LX",
1472 .init = ss_lx_init,
1473 .block_default_type = IF_SCSI,
1474 DEFAULT_MACHINE_OPTIONS,
1475 };
1476
1477 static QEMUMachine ss4_machine = {
1478 .name = "SS-4",
1479 .desc = "Sun4m platform, SPARCstation 4",
1480 .init = ss4_init,
1481 .block_default_type = IF_SCSI,
1482 DEFAULT_MACHINE_OPTIONS,
1483 };
1484
1485 static QEMUMachine scls_machine = {
1486 .name = "SPARCClassic",
1487 .desc = "Sun4m platform, SPARCClassic",
1488 .init = scls_init,
1489 .block_default_type = IF_SCSI,
1490 DEFAULT_MACHINE_OPTIONS,
1491 };
1492
1493 static QEMUMachine sbook_machine = {
1494 .name = "SPARCbook",
1495 .desc = "Sun4m platform, SPARCbook",
1496 .init = sbook_init,
1497 .block_default_type = IF_SCSI,
1498 DEFAULT_MACHINE_OPTIONS,
1499 };
1500
1501 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1502 /* SS-1000 */
1503 {
1504 .iounit_bases = {
1505 0xfe0200000ULL,
1506 0xfe1200000ULL,
1507 0xfe2200000ULL,
1508 0xfe3200000ULL,
1509 -1,
1510 },
1511 .tcx_base = 0x820000000ULL,
1512 .slavio_base = 0xf00000000ULL,
1513 .ms_kb_base = 0xf00240000ULL,
1514 .serial_base = 0xf00200000ULL,
1515 .nvram_base = 0xf00280000ULL,
1516 .counter_base = 0xf00300000ULL,
1517 .espdma_base = 0x800081000ULL,
1518 .esp_base = 0x800080000ULL,
1519 .ledma_base = 0x800040000ULL,
1520 .le_base = 0x800060000ULL,
1521 .sbi_base = 0xf02800000ULL,
1522 .nvram_machine_id = 0x80,
1523 .machine_id = ss1000_id,
1524 .iounit_version = 0x03000000,
1525 .max_mem = 0xf00000000ULL,
1526 .default_cpu_model = "TI SuperSparc II",
1527 },
1528 /* SS-2000 */
1529 {
1530 .iounit_bases = {
1531 0xfe0200000ULL,
1532 0xfe1200000ULL,
1533 0xfe2200000ULL,
1534 0xfe3200000ULL,
1535 0xfe4200000ULL,
1536 },
1537 .tcx_base = 0x820000000ULL,
1538 .slavio_base = 0xf00000000ULL,
1539 .ms_kb_base = 0xf00240000ULL,
1540 .serial_base = 0xf00200000ULL,
1541 .nvram_base = 0xf00280000ULL,
1542 .counter_base = 0xf00300000ULL,
1543 .espdma_base = 0x800081000ULL,
1544 .esp_base = 0x800080000ULL,
1545 .ledma_base = 0x800040000ULL,
1546 .le_base = 0x800060000ULL,
1547 .sbi_base = 0xf02800000ULL,
1548 .nvram_machine_id = 0x80,
1549 .machine_id = ss2000_id,
1550 .iounit_version = 0x03000000,
1551 .max_mem = 0xf00000000ULL,
1552 .default_cpu_model = "TI SuperSparc II",
1553 },
1554 };
1555
1556 static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
1557 {
1558 DeviceState *dev;
1559 SysBusDevice *s;
1560 unsigned int i;
1561
1562 dev = qdev_create(NULL, "sbi");
1563 qdev_init_nofail(dev);
1564
1565 s = sysbus_from_qdev(dev);
1566
1567 for (i = 0; i < MAX_CPUS; i++) {
1568 sysbus_connect_irq(s, i, *parent_irq[i]);
1569 }
1570
1571 sysbus_mmio_map(s, 0, addr);
1572
1573 return dev;
1574 }
1575
1576 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1577 const char *boot_device,
1578 const char *kernel_filename,
1579 const char *kernel_cmdline,
1580 const char *initrd_filename, const char *cpu_model)
1581 {
1582 unsigned int i;
1583 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1584 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1585 espdma_irq, ledma_irq;
1586 qemu_irq esp_reset, dma_enable;
1587 unsigned long kernel_size;
1588 void *fw_cfg;
1589 DeviceState *dev;
1590
1591 /* init CPUs */
1592 if (!cpu_model)
1593 cpu_model = hwdef->default_cpu_model;
1594
1595 for(i = 0; i < smp_cpus; i++) {
1596 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1597 }
1598
1599 for (i = smp_cpus; i < MAX_CPUS; i++)
1600 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1601
1602 /* set up devices */
1603 ram_init(0, RAM_size, hwdef->max_mem);
1604
1605 prom_init(hwdef->slavio_base, bios_name);
1606
1607 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1608
1609 for (i = 0; i < 32; i++) {
1610 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1611 }
1612 for (i = 0; i < MAX_CPUS; i++) {
1613 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1614 }
1615
1616 for (i = 0; i < MAX_IOUNITS; i++)
1617 if (hwdef->iounit_bases[i] != (hwaddr)-1)
1618 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1619 hwdef->iounit_version,
1620 sbi_irq[0]);
1621
1622 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1623 iounits[0], &espdma_irq, 0);
1624
1625 /* should be lebuffer instead */
1626 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1627 iounits[0], &ledma_irq, 0);
1628
1629 if (graphic_depth != 8 && graphic_depth != 24) {
1630 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1631 exit (1);
1632 }
1633 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1634 graphic_depth);
1635
1636 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1637
1638 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1639
1640 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1641
1642 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1643 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1644 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1645 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1646 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1647 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1648
1649 if (drive_get_max_bus(IF_SCSI) > 0) {
1650 fprintf(stderr, "qemu: too many SCSI bus\n");
1651 exit(1);
1652 }
1653
1654 esp_init(hwdef->esp_base, 2,
1655 espdma_memory_read, espdma_memory_write,
1656 espdma, espdma_irq, &esp_reset, &dma_enable);
1657
1658 qdev_connect_gpio_out(espdma, 0, esp_reset);
1659 qdev_connect_gpio_out(espdma, 1, dma_enable);
1660
1661 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1662 RAM_size);
1663
1664 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1665 boot_device, RAM_size, kernel_size, graphic_width,
1666 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1667 "Sun4d");
1668
1669 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1670 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1671 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1672 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1673 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1674 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1675 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1676 if (kernel_cmdline) {
1677 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1678 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1679 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1680 (uint8_t*)strdup(kernel_cmdline),
1681 strlen(kernel_cmdline) + 1);
1682 } else {
1683 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1684 }
1685 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1686 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1687 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1688 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1689 }
1690
1691 /* SPARCserver 1000 hardware initialisation */
1692 static void ss1000_init(QEMUMachineInitArgs *args)
1693 {
1694 ram_addr_t RAM_size = args->ram_size;
1695 const char *cpu_model = args->cpu_model;
1696 const char *kernel_filename = args->kernel_filename;
1697 const char *kernel_cmdline = args->kernel_cmdline;
1698 const char *initrd_filename = args->initrd_filename;
1699 const char *boot_device = args->boot_device;
1700 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1701 kernel_cmdline, initrd_filename, cpu_model);
1702 }
1703
1704 /* SPARCcenter 2000 hardware initialisation */
1705 static void ss2000_init(QEMUMachineInitArgs *args)
1706 {
1707 ram_addr_t RAM_size = args->ram_size;
1708 const char *cpu_model = args->cpu_model;
1709 const char *kernel_filename = args->kernel_filename;
1710 const char *kernel_cmdline = args->kernel_cmdline;
1711 const char *initrd_filename = args->initrd_filename;
1712 const char *boot_device = args->boot_device;
1713 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1714 kernel_cmdline, initrd_filename, cpu_model);
1715 }
1716
1717 static QEMUMachine ss1000_machine = {
1718 .name = "SS-1000",
1719 .desc = "Sun4d platform, SPARCserver 1000",
1720 .init = ss1000_init,
1721 .block_default_type = IF_SCSI,
1722 .max_cpus = 8,
1723 DEFAULT_MACHINE_OPTIONS,
1724 };
1725
1726 static QEMUMachine ss2000_machine = {
1727 .name = "SS-2000",
1728 .desc = "Sun4d platform, SPARCcenter 2000",
1729 .init = ss2000_init,
1730 .block_default_type = IF_SCSI,
1731 .max_cpus = 20,
1732 DEFAULT_MACHINE_OPTIONS,
1733 };
1734
1735 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1736 /* SS-2 */
1737 {
1738 .iommu_base = 0xf8000000,
1739 .tcx_base = 0xfe000000,
1740 .slavio_base = 0xf6000000,
1741 .intctl_base = 0xf5000000,
1742 .counter_base = 0xf3000000,
1743 .ms_kb_base = 0xf0000000,
1744 .serial_base = 0xf1000000,
1745 .nvram_base = 0xf2000000,
1746 .fd_base = 0xf7200000,
1747 .dma_base = 0xf8400000,
1748 .esp_base = 0xf8800000,
1749 .le_base = 0xf8c00000,
1750 .aux1_base = 0xf7400003,
1751 .nvram_machine_id = 0x55,
1752 .machine_id = ss2_id,
1753 .max_mem = 0x10000000,
1754 .default_cpu_model = "Cypress CY7C601",
1755 },
1756 };
1757
1758 static DeviceState *sun4c_intctl_init(hwaddr addr,
1759 qemu_irq *parent_irq)
1760 {
1761 DeviceState *dev;
1762 SysBusDevice *s;
1763 unsigned int i;
1764
1765 dev = qdev_create(NULL, "sun4c_intctl");
1766 qdev_init_nofail(dev);
1767
1768 s = sysbus_from_qdev(dev);
1769
1770 for (i = 0; i < MAX_PILS; i++) {
1771 sysbus_connect_irq(s, i, parent_irq[i]);
1772 }
1773 sysbus_mmio_map(s, 0, addr);
1774
1775 return dev;
1776 }
1777
1778 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1779 const char *boot_device,
1780 const char *kernel_filename,
1781 const char *kernel_cmdline,
1782 const char *initrd_filename, const char *cpu_model)
1783 {
1784 void *iommu, *espdma, *ledma, *nvram;
1785 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1786 qemu_irq esp_reset, dma_enable;
1787 qemu_irq fdc_tc;
1788 unsigned long kernel_size;
1789 DriveInfo *fd[MAX_FD];
1790 void *fw_cfg;
1791 DeviceState *dev;
1792 unsigned int i;
1793
1794 /* init CPU */
1795 if (!cpu_model)
1796 cpu_model = hwdef->default_cpu_model;
1797
1798 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1799
1800 /* set up devices */
1801 ram_init(0, RAM_size, hwdef->max_mem);
1802
1803 prom_init(hwdef->slavio_base, bios_name);
1804
1805 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1806
1807 for (i = 0; i < 8; i++) {
1808 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1809 }
1810
1811 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1812 slavio_irq[1]);
1813
1814 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1815 iommu, &espdma_irq, 0);
1816
1817 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1818 slavio_irq[3], iommu, &ledma_irq, 1);
1819
1820 if (graphic_depth != 8 && graphic_depth != 24) {
1821 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1822 exit (1);
1823 }
1824 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1825 graphic_depth);
1826
1827 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1828
1829 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1830
1831 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1832 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1833 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1834 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1835 escc_init(hwdef->serial_base, slavio_irq[1],
1836 slavio_irq[1], serial_hds[0], serial_hds[1],
1837 ESCC_CLOCK, 1);
1838
1839 if (hwdef->fd_base != (hwaddr)-1) {
1840 /* there is zero or one floppy drive */
1841 memset(fd, 0, sizeof(fd));
1842 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1843 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1844 &fdc_tc);
1845 } else {
1846 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1847 }
1848
1849 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1850
1851 if (drive_get_max_bus(IF_SCSI) > 0) {
1852 fprintf(stderr, "qemu: too many SCSI bus\n");
1853 exit(1);
1854 }
1855
1856 esp_init(hwdef->esp_base, 2,
1857 espdma_memory_read, espdma_memory_write,
1858 espdma, espdma_irq, &esp_reset, &dma_enable);
1859
1860 qdev_connect_gpio_out(espdma, 0, esp_reset);
1861 qdev_connect_gpio_out(espdma, 1, dma_enable);
1862
1863 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1864 RAM_size);
1865
1866 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1867 boot_device, RAM_size, kernel_size, graphic_width,
1868 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1869 "Sun4c");
1870
1871 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1872 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1873 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1874 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1875 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1876 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1877 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1878 if (kernel_cmdline) {
1879 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1880 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1881 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1882 (uint8_t*)strdup(kernel_cmdline),
1883 strlen(kernel_cmdline) + 1);
1884 } else {
1885 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1886 }
1887 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1888 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1889 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1890 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1891 }
1892
1893 /* SPARCstation 2 hardware initialisation */
1894 static void ss2_init(QEMUMachineInitArgs *args)
1895 {
1896 ram_addr_t RAM_size = args->ram_size;
1897 const char *cpu_model = args->cpu_model;
1898 const char *kernel_filename = args->kernel_filename;
1899 const char *kernel_cmdline = args->kernel_cmdline;
1900 const char *initrd_filename = args->initrd_filename;
1901 const char *boot_device = args->boot_device;
1902 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1903 kernel_cmdline, initrd_filename, cpu_model);
1904 }
1905
1906 static QEMUMachine ss2_machine = {
1907 .name = "SS-2",
1908 .desc = "Sun4c platform, SPARCstation 2",
1909 .init = ss2_init,
1910 .block_default_type = IF_SCSI,
1911 DEFAULT_MACHINE_OPTIONS,
1912 };
1913
1914 static void sun4m_register_types(void)
1915 {
1916 type_register_static(&idreg_info);
1917 type_register_static(&afx_info);
1918 type_register_static(&prom_info);
1919 type_register_static(&ram_info);
1920 }
1921
1922 static void ss2_machine_init(void)
1923 {
1924 qemu_register_machine(&ss5_machine);
1925 qemu_register_machine(&ss10_machine);
1926 qemu_register_machine(&ss600mp_machine);
1927 qemu_register_machine(&ss20_machine);
1928 qemu_register_machine(&voyager_machine);
1929 qemu_register_machine(&ss_lx_machine);
1930 qemu_register_machine(&ss4_machine);
1931 qemu_register_machine(&scls_machine);
1932 qemu_register_machine(&sbook_machine);
1933 qemu_register_machine(&ss1000_machine);
1934 qemu_register_machine(&ss2000_machine);
1935 qemu_register_machine(&ss2_machine);
1936 }
1937
1938 type_init(sun4m_register_types)
1939 machine_init(ss2_machine_init);
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