hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "loader.h"
  26 #include "ui/console.h"
  27 #include "pci/pci.h"
  28
  29 #undef VERBOSE
  30 #define HW_RECT_ACCEL
  31 #define HW_FILL_ACCEL
  32 #define HW_MOUSE_ACCEL
  33
  34 #include "vga_int.h"
  35
  36 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
  37
  38 struct vmsvga_state_s {
  39     VGACommonState vga;
  40
  41     int invalidated;
  42     int depth;
  43     int bypp;
  44     int enable;
  45     int config;
  46     struct {
  47         int id;
  48         int x;
  49         int y;
  50         int on;
  51     } cursor;
  52
  53     int index;
  54     int scratch_size;
  55     uint32_t *scratch;
  56     int new_width;
  57     int new_height;
  58     uint32_t guest;
  59     uint32_t svgaid;
  60     uint32_t wred;
  61     uint32_t wgreen;
  62     uint32_t wblue;
  63     int syncing;
  64
  65     MemoryRegion fifo_ram;
  66     uint8_t *fifo_ptr;
  67     unsigned int fifo_size;
  68
  69     union {
  70         uint32_t *fifo;
  71         struct QEMU_PACKED {
  72             uint32_t min;
  73             uint32_t max;
  74             uint32_t next_cmd;
  75             uint32_t stop;
  76             /* Add registers here when adding capabilities.  */
  77             uint32_t fifo[0];
  78         } *cmd;
  79     };
  80
  81 #define REDRAW_FIFO_LEN  512
  82     struct vmsvga_rect_s {
  83         int x, y, w, h;
  84     } redraw_fifo[REDRAW_FIFO_LEN];
  85     int redraw_fifo_first, redraw_fifo_last;
  86 };
  87
  88 struct pci_vmsvga_state_s {
  89     PCIDevice card;
  90     struct vmsvga_state_s chip;
  91     MemoryRegion io_bar;
  92 };
  93
  94 #define SVGA_MAGIC              0x900000UL
  95 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
  96 #define SVGA_ID_0               SVGA_MAKE_ID(0)
  97 #define SVGA_ID_1               SVGA_MAKE_ID(1)
  98 #define SVGA_ID_2               SVGA_MAKE_ID(2)
  99
 100 #define SVGA_LEGACY_BASE_PORT   0x4560
 101 #define SVGA_INDEX_PORT         0x0
 102 #define SVGA_VALUE_PORT         0x1
 103 #define SVGA_BIOS_PORT          0x2
 104
 105 #define SVGA_VERSION_2
 106
 107 #ifdef SVGA_VERSION_2
 108 # define SVGA_ID                SVGA_ID_2
 109 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 110 # define SVGA_IO_MUL            1
 111 # define SVGA_FIFO_SIZE         0x10000
 112 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 113 #else
 114 # define SVGA_ID                SVGA_ID_1
 115 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 116 # define SVGA_IO_MUL            4
 117 # define SVGA_FIFO_SIZE         0x10000
 118 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 119 #endif
 120
 121 enum {
 122     /* ID 0, 1 and 2 registers */
 123     SVGA_REG_ID = 0,
 124     SVGA_REG_ENABLE = 1,
 125     SVGA_REG_WIDTH = 2,
 126     SVGA_REG_HEIGHT = 3,
 127     SVGA_REG_MAX_WIDTH = 4,
 128     SVGA_REG_MAX_HEIGHT = 5,
 129     SVGA_REG_DEPTH = 6,
 130     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 131     SVGA_REG_PSEUDOCOLOR = 8,
 132     SVGA_REG_RED_MASK = 9,
 133     SVGA_REG_GREEN_MASK = 10,
 134     SVGA_REG_BLUE_MASK = 11,
 135     SVGA_REG_BYTES_PER_LINE = 12,
 136     SVGA_REG_FB_START = 13,
 137     SVGA_REG_FB_OFFSET = 14,
 138     SVGA_REG_VRAM_SIZE = 15,
 139     SVGA_REG_FB_SIZE = 16,
 140
 141     /* ID 1 and 2 registers */
 142     SVGA_REG_CAPABILITIES = 17,
 143     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 144     SVGA_REG_MEM_SIZE = 19,
 145     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 146     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 147     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 148     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 149     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 150     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 151     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 152     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 153     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 154     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 155     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 156     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 157     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 158
 159     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 160     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 161     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 162 };
 163
 164 #define SVGA_CAP_NONE                   0
 165 #define SVGA_CAP_RECT_FILL              (1 << 0)
 166 #define SVGA_CAP_RECT_COPY              (1 << 1)
 167 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 168 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 169 #define SVGA_CAP_RASTER_OP              (1 << 4)
 170 #define SVGA_CAP_CURSOR                 (1 << 5)
 171 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 172 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 173 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 174 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 175 #define SVGA_CAP_GLYPH                  (1 << 10)
 176 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 177 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 178 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 179 #define SVGA_CAP_3D                     (1 << 14)
 180 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 181 #define SVGA_CAP_MULTIMON               (1 << 16)
 182 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 183
 184 /*
 185  * FIFO offsets (seen as an array of 32-bit words)
 186  */
 187 enum {
 188     /*
 189      * The original defined FIFO offsets
 190      */
 191     SVGA_FIFO_MIN = 0,
 192     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 193     SVGA_FIFO_NEXT_CMD,
 194     SVGA_FIFO_STOP,
 195
 196     /*
 197      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 198      */
 199     SVGA_FIFO_CAPABILITIES = 4,
 200     SVGA_FIFO_FLAGS,
 201     SVGA_FIFO_FENCE,
 202     SVGA_FIFO_3D_HWVERSION,
 203     SVGA_FIFO_PITCHLOCK,
 204 };
 205
 206 #define SVGA_FIFO_CAP_NONE              0
 207 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 208 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 209 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 210
 211 #define SVGA_FIFO_FLAG_NONE             0
 212 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 213
 214 /* These values can probably be changed arbitrarily.  */
 215 #define SVGA_SCRATCH_SIZE               0x8000
 216 #define SVGA_MAX_WIDTH                  2360
 217 #define SVGA_MAX_HEIGHT                 1770
 218
 219 #ifdef VERBOSE
 220 # define GUEST_OS_BASE          0x5001
 221 static const char *vmsvga_guest_id[] = {
 222     [0x00] = "Dos",
 223     [0x01] = "Windows 3.1",
 224     [0x02] = "Windows 95",
 225     [0x03] = "Windows 98",
 226     [0x04] = "Windows ME",
 227     [0x05] = "Windows NT",
 228     [0x06] = "Windows 2000",
 229     [0x07] = "Linux",
 230     [0x08] = "OS/2",
 231     [0x09] = "an unknown OS",
 232     [0x0a] = "BSD",
 233     [0x0b] = "Whistler",
 234     [0x0c] = "an unknown OS",
 235     [0x0d] = "an unknown OS",
 236     [0x0e] = "an unknown OS",
 237     [0x0f] = "an unknown OS",
 238     [0x10] = "an unknown OS",
 239     [0x11] = "an unknown OS",
 240     [0x12] = "an unknown OS",
 241     [0x13] = "an unknown OS",
 242     [0x14] = "an unknown OS",
 243     [0x15] = "Windows 2003",
 244 };
 245 #endif
 246
 247 enum {
 248     SVGA_CMD_INVALID_CMD = 0,
 249     SVGA_CMD_UPDATE = 1,
 250     SVGA_CMD_RECT_FILL = 2,
 251     SVGA_CMD_RECT_COPY = 3,
 252     SVGA_CMD_DEFINE_BITMAP = 4,
 253     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 254     SVGA_CMD_DEFINE_PIXMAP = 6,
 255     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 256     SVGA_CMD_RECT_BITMAP_FILL = 8,
 257     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 258     SVGA_CMD_RECT_BITMAP_COPY = 10,
 259     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 260     SVGA_CMD_FREE_OBJECT = 12,
 261     SVGA_CMD_RECT_ROP_FILL = 13,
 262     SVGA_CMD_RECT_ROP_COPY = 14,
 263     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 264     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 265     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 266     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 267     SVGA_CMD_DEFINE_CURSOR = 19,
 268     SVGA_CMD_DISPLAY_CURSOR = 20,
 269     SVGA_CMD_MOVE_CURSOR = 21,
 270     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 271     SVGA_CMD_DRAW_GLYPH = 23,
 272     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 273     SVGA_CMD_UPDATE_VERBOSE = 25,
 274     SVGA_CMD_SURFACE_FILL = 26,
 275     SVGA_CMD_SURFACE_COPY = 27,
 276     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 277     SVGA_CMD_FRONT_ROP_FILL = 29,
 278     SVGA_CMD_FENCE = 30,
 279 };
 280
 281 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 282 enum {
 283     SVGA_CURSOR_ON_HIDE = 0,
 284     SVGA_CURSOR_ON_SHOW = 1,
 285     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 286     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 287 };
 288
 289 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 290                 int x, int y, int w, int h)
 291 {
 292     int line;
 293     int bypl;
 294     int width;
 295     int start;
 296     uint8_t *src;
 297     uint8_t *dst;
 298
 299     if (x + w > ds_get_width(s->vga.ds)) {
 300         fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
 301                 __func__, x, w);
 302         x = MIN(x, ds_get_width(s->vga.ds));
 303         w = ds_get_width(s->vga.ds) - x;
 304     }
 305
 306     if (y + h > ds_get_height(s->vga.ds)) {
 307         fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
 308                 __func__, y, h);
 309         y = MIN(y, ds_get_height(s->vga.ds));
 310         h = ds_get_height(s->vga.ds) - y;
 311     }
 312
 313     bypl = ds_get_linesize(s->vga.ds);
 314     width = ds_get_bytes_per_pixel(s->vga.ds) * w;
 315     start = ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y;
 316     src = s->vga.vram_ptr + start;
 317     dst = ds_get_data(s->vga.ds) + start;
 318
 319     for (line = h; line > 0; line--, src += bypl, dst += bypl) {
 320         memcpy(dst, src, width);
 321     }
 322     dpy_gfx_update(s->vga.ds, x, y, w, h);
 323 }
 324
 325 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 326                 int x, int y, int w, int h)
 327 {
 328     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
 329
 330     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 331     rect->x = x;
 332     rect->y = y;
 333     rect->w = w;
 334     rect->h = h;
 335 }
 336
 337 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 338 {
 339     struct vmsvga_rect_s *rect;
 340
 341     if (s->invalidated) {
 342         s->redraw_fifo_first = s->redraw_fifo_last;
 343         return;
 344     }
 345     /* Overlapping region updates can be optimised out here - if someone
 346      * knows a smart algorithm to do that, please share.  */
 347     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 348         rect = &s->redraw_fifo[s->redraw_fifo_first++];
 349         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 350         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 351     }
 352 }
 353
 354 #ifdef HW_RECT_ACCEL
 355 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 356                 int x0, int y0, int x1, int y1, int w, int h)
 357 {
 358     uint8_t *vram = s->vga.vram_ptr;
 359     int bypl = ds_get_linesize(s->vga.ds);
 360     int bypp = ds_get_bytes_per_pixel(s->vga.ds);
 361     int width = bypp * w;
 362     int line = h;
 363     uint8_t *ptr[2];
 364
 365     if (y1 > y0) {
 366         ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
 367         ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
 368         for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
 369             memmove(ptr[1], ptr[0], width);
 370         }
 371     } else {
 372         ptr[0] = vram + bypp * x0 + bypl * y0;
 373         ptr[1] = vram + bypp * x1 + bypl * y1;
 374         for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
 375             memmove(ptr[1], ptr[0], width);
 376         }
 377     }
 378
 379     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 380 }
 381 #endif
 382
 383 #ifdef HW_FILL_ACCEL
 384 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 385                 uint32_t c, int x, int y, int w, int h)
 386 {
 387     int bypl = ds_get_linesize(s->vga.ds);
 388     int width = ds_get_bytes_per_pixel(s->vga.ds) * w;
 389     int line = h;
 390     int column;
 391     uint8_t *fst;
 392     uint8_t *dst;
 393     uint8_t *src;
 394     uint8_t col[4];
 395
 396     col[0] = c;
 397     col[1] = c >> 8;
 398     col[2] = c >> 16;
 399     col[3] = c >> 24;
 400
 401     fst = s->vga.vram_ptr + ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y;
 402
 403     if (line--) {
 404         dst = fst;
 405         src = col;
 406         for (column = width; column > 0; column--) {
 407             *(dst++) = *(src++);
 408             if (src - col == ds_get_bytes_per_pixel(s->vga.ds)) {
 409                 src = col;
 410             }
 411         }
 412         dst = fst;
 413         for (; line > 0; line--) {
 414             dst += bypl;
 415             memcpy(dst, fst, width);
 416         }
 417     }
 418
 419     vmsvga_update_rect_delayed(s, x, y, w, h);
 420 }
 421 #endif
 422
 423 struct vmsvga_cursor_definition_s {
 424     int width;
 425     int height;
 426     int id;
 427     int bpp;
 428     int hot_x;
 429     int hot_y;
 430     uint32_t mask[1024];
 431     uint32_t image[4096];
 432 };
 433
 434 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 435 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 436
 437 #ifdef HW_MOUSE_ACCEL
 438 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 439                 struct vmsvga_cursor_definition_s *c)
 440 {
 441     QEMUCursor *qc;
 442     int i, pixels;
 443
 444     qc = cursor_alloc(c->width, c->height);
 445     qc->hot_x = c->hot_x;
 446     qc->hot_y = c->hot_y;
 447     switch (c->bpp) {
 448     case 1:
 449         cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
 450                         1, (void *)c->mask);
 451 #ifdef DEBUG
 452         cursor_print_ascii_art(qc, "vmware/mono");
 453 #endif
 454         break;
 455     case 32:
 456         /* fill alpha channel from mask, set color to zero */
 457         cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
 458                         1, (void *)c->mask);
 459         /* add in rgb values */
 460         pixels = c->width * c->height;
 461         for (i = 0; i < pixels; i++) {
 462             qc->data[i] |= c->image[i] & 0xffffff;
 463         }
 464 #ifdef DEBUG
 465         cursor_print_ascii_art(qc, "vmware/32bit");
 466 #endif
 467         break;
 468     default:
 469         fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
 470                 __func__, c->bpp);
 471         cursor_put(qc);
 472         qc = cursor_builtin_left_ptr();
 473     }
 474
 475     dpy_cursor_define(s->vga.ds, qc);
 476     cursor_put(qc);
 477 }
 478 #endif
 479
 480 #define CMD(f)  le32_to_cpu(s->cmd->f)
 481
 482 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
 483 {
 484     int num;
 485
 486     if (!s->config || !s->enable) {
 487         return 0;
 488     }
 489     num = CMD(next_cmd) - CMD(stop);
 490     if (num < 0) {
 491         num += CMD(max) - CMD(min);
 492     }
 493     return num >> 2;
 494 }
 495
 496 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
 497 {
 498     uint32_t cmd = s->fifo[CMD(stop) >> 2];
 499
 500     s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
 501     if (CMD(stop) >= CMD(max)) {
 502         s->cmd->stop = s->cmd->min;
 503     }
 504     return cmd;
 505 }
 506
 507 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 508 {
 509     return le32_to_cpu(vmsvga_fifo_read_raw(s));
 510 }
 511
 512 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 513 {
 514     uint32_t cmd, colour;
 515     int args, len;
 516     int x, y, dx, dy, width, height;
 517     struct vmsvga_cursor_definition_s cursor;
 518     uint32_t cmd_start;
 519
 520     len = vmsvga_fifo_length(s);
 521     while (len > 0) {
 522         /* May need to go back to the start of the command if incomplete */
 523         cmd_start = s->cmd->stop;
 524
 525         switch (cmd = vmsvga_fifo_read(s)) {
 526         case SVGA_CMD_UPDATE:
 527         case SVGA_CMD_UPDATE_VERBOSE:
 528             len -= 5;
 529             if (len < 0) {
 530                 goto rewind;
 531             }
 532
 533             x = vmsvga_fifo_read(s);
 534             y = vmsvga_fifo_read(s);
 535             width = vmsvga_fifo_read(s);
 536             height = vmsvga_fifo_read(s);
 537             vmsvga_update_rect_delayed(s, x, y, width, height);
 538             break;
 539
 540         case SVGA_CMD_RECT_FILL:
 541             len -= 6;
 542             if (len < 0) {
 543                 goto rewind;
 544             }
 545
 546             colour = vmsvga_fifo_read(s);
 547             x = vmsvga_fifo_read(s);
 548             y = vmsvga_fifo_read(s);
 549             width = vmsvga_fifo_read(s);
 550             height = vmsvga_fifo_read(s);
 551 #ifdef HW_FILL_ACCEL
 552             vmsvga_fill_rect(s, colour, x, y, width, height);
 553             break;
 554 #else
 555             args = 0;
 556             goto badcmd;
 557 #endif
 558
 559         case SVGA_CMD_RECT_COPY:
 560             len -= 7;
 561             if (len < 0) {
 562                 goto rewind;
 563             }
 564
 565             x = vmsvga_fifo_read(s);
 566             y = vmsvga_fifo_read(s);
 567             dx = vmsvga_fifo_read(s);
 568             dy = vmsvga_fifo_read(s);
 569             width = vmsvga_fifo_read(s);
 570             height = vmsvga_fifo_read(s);
 571 #ifdef HW_RECT_ACCEL
 572             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 573             break;
 574 #else
 575             args = 0;
 576             goto badcmd;
 577 #endif
 578
 579         case SVGA_CMD_DEFINE_CURSOR:
 580             len -= 8;
 581             if (len < 0) {
 582                 goto rewind;
 583             }
 584
 585             cursor.id = vmsvga_fifo_read(s);
 586             cursor.hot_x = vmsvga_fifo_read(s);
 587             cursor.hot_y = vmsvga_fifo_read(s);
 588             cursor.width = x = vmsvga_fifo_read(s);
 589             cursor.height = y = vmsvga_fifo_read(s);
 590             vmsvga_fifo_read(s);
 591             cursor.bpp = vmsvga_fifo_read(s);
 592
 593             args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
 594             if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
 595                 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
 596                     goto badcmd;
 597             }
 598
 599             len -= args;
 600             if (len < 0) {
 601                 goto rewind;
 602             }
 603
 604             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
 605                 cursor.mask[args] = vmsvga_fifo_read_raw(s);
 606             }
 607             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
 608                 cursor.image[args] = vmsvga_fifo_read_raw(s);
 609             }
 610 #ifdef HW_MOUSE_ACCEL
 611             vmsvga_cursor_define(s, &cursor);
 612             break;
 613 #else
 614             args = 0;
 615             goto badcmd;
 616 #endif
 617
 618         /*
 619          * Other commands that we at least know the number of arguments
 620          * for so we can avoid FIFO desync if driver uses them illegally.
 621          */
 622         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 623             len -= 6;
 624             if (len < 0) {
 625                 goto rewind;
 626             }
 627             vmsvga_fifo_read(s);
 628             vmsvga_fifo_read(s);
 629             vmsvga_fifo_read(s);
 630             x = vmsvga_fifo_read(s);
 631             y = vmsvga_fifo_read(s);
 632             args = x * y;
 633             goto badcmd;
 634         case SVGA_CMD_RECT_ROP_FILL:
 635             args = 6;
 636             goto badcmd;
 637         case SVGA_CMD_RECT_ROP_COPY:
 638             args = 7;
 639             goto badcmd;
 640         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 641             len -= 4;
 642             if (len < 0) {
 643                 goto rewind;
 644             }
 645             vmsvga_fifo_read(s);
 646             vmsvga_fifo_read(s);
 647             args = 7 + (vmsvga_fifo_read(s) >> 2);
 648             goto badcmd;
 649         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 650             args = 12;
 651             goto badcmd;
 652
 653         /*
 654          * Other commands that are not listed as depending on any
 655          * CAPABILITIES bits, but are not described in the README either.
 656          */
 657         case SVGA_CMD_SURFACE_FILL:
 658         case SVGA_CMD_SURFACE_COPY:
 659         case SVGA_CMD_FRONT_ROP_FILL:
 660         case SVGA_CMD_FENCE:
 661         case SVGA_CMD_INVALID_CMD:
 662             break; /* Nop */
 663
 664         default:
 665             args = 0;
 666         badcmd:
 667             len -= args;
 668             if (len < 0) {
 669                 goto rewind;
 670             }
 671             while (args--) {
 672                 vmsvga_fifo_read(s);
 673             }
 674             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 675                    __func__, cmd);
 676             break;
 677
 678         rewind:
 679             s->cmd->stop = cmd_start;
 680             break;
 681         }
 682     }
 683
 684     s->syncing = 0;
 685 }
 686
 687 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 688 {
 689     struct vmsvga_state_s *s = opaque;
 690
 691     return s->index;
 692 }
 693
 694 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 695 {
 696     struct vmsvga_state_s *s = opaque;
 697
 698     s->index = index;
 699 }
 700
 701 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 702 {
 703     uint32_t caps;
 704     struct vmsvga_state_s *s = opaque;
 705
 706     switch (s->index) {
 707     case SVGA_REG_ID:
 708         return s->svgaid;
 709
 710     case SVGA_REG_ENABLE:
 711         return s->enable;
 712
 713     case SVGA_REG_WIDTH:
 714         return ds_get_width(s->vga.ds);
 715
 716     case SVGA_REG_HEIGHT:
 717         return ds_get_height(s->vga.ds);
 718
 719     case SVGA_REG_MAX_WIDTH:
 720         return SVGA_MAX_WIDTH;
 721
 722     case SVGA_REG_MAX_HEIGHT:
 723         return SVGA_MAX_HEIGHT;
 724
 725     case SVGA_REG_DEPTH:
 726         return s->depth;
 727
 728     case SVGA_REG_BITS_PER_PIXEL:
 729         return (s->depth + 7) & ~7;
 730
 731     case SVGA_REG_PSEUDOCOLOR:
 732         return 0x0;
 733
 734     case SVGA_REG_RED_MASK:
 735         return s->wred;
 736
 737     case SVGA_REG_GREEN_MASK:
 738         return s->wgreen;
 739
 740     case SVGA_REG_BLUE_MASK:
 741         return s->wblue;
 742
 743     case SVGA_REG_BYTES_PER_LINE:
 744         return s->bypp * s->new_width;
 745
 746     case SVGA_REG_FB_START: {
 747         struct pci_vmsvga_state_s *pci_vmsvga
 748             = container_of(s, struct pci_vmsvga_state_s, chip);
 749         return pci_get_bar_addr(&pci_vmsvga->card, 1);
 750     }
 751
 752     case SVGA_REG_FB_OFFSET:
 753         return 0x0;
 754
 755     case SVGA_REG_VRAM_SIZE:
 756         return s->vga.vram_size; /* No physical VRAM besides the framebuffer */
 757
 758     case SVGA_REG_FB_SIZE:
 759         return s->vga.vram_size;
 760
 761     case SVGA_REG_CAPABILITIES:
 762         caps = SVGA_CAP_NONE;
 763 #ifdef HW_RECT_ACCEL
 764         caps |= SVGA_CAP_RECT_COPY;
 765 #endif
 766 #ifdef HW_FILL_ACCEL
 767         caps |= SVGA_CAP_RECT_FILL;
 768 #endif
 769 #ifdef HW_MOUSE_ACCEL
 770         if (dpy_cursor_define_supported(s->vga.ds)) {
 771             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 772                     SVGA_CAP_CURSOR_BYPASS;
 773         }
 774 #endif
 775         return caps;
 776
 777     case SVGA_REG_MEM_START: {
 778         struct pci_vmsvga_state_s *pci_vmsvga
 779             = container_of(s, struct pci_vmsvga_state_s, chip);
 780         return pci_get_bar_addr(&pci_vmsvga->card, 2);
 781     }
 782
 783     case SVGA_REG_MEM_SIZE:
 784         return s->fifo_size;
 785
 786     case SVGA_REG_CONFIG_DONE:
 787         return s->config;
 788
 789     case SVGA_REG_SYNC:
 790     case SVGA_REG_BUSY:
 791         return s->syncing;
 792
 793     case SVGA_REG_GUEST_ID:
 794         return s->guest;
 795
 796     case SVGA_REG_CURSOR_ID:
 797         return s->cursor.id;
 798
 799     case SVGA_REG_CURSOR_X:
 800         return s->cursor.x;
 801
 802     case SVGA_REG_CURSOR_Y:
 803         return s->cursor.x;
 804
 805     case SVGA_REG_CURSOR_ON:
 806         return s->cursor.on;
 807
 808     case SVGA_REG_HOST_BITS_PER_PIXEL:
 809         return (s->depth + 7) & ~7;
 810
 811     case SVGA_REG_SCRATCH_SIZE:
 812         return s->scratch_size;
 813
 814     case SVGA_REG_MEM_REGS:
 815     case SVGA_REG_NUM_DISPLAYS:
 816     case SVGA_REG_PITCHLOCK:
 817     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 818         return 0;
 819
 820     default:
 821         if (s->index >= SVGA_SCRATCH_BASE &&
 822             s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 823             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 824         }
 825         printf("%s: Bad register %02x\n", __func__, s->index);
 826     }
 827
 828     return 0;
 829 }
 830
 831 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 832 {
 833     struct vmsvga_state_s *s = opaque;
 834
 835     switch (s->index) {
 836     case SVGA_REG_ID:
 837         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
 838             s->svgaid = value;
 839         }
 840         break;
 841
 842     case SVGA_REG_ENABLE:
 843         s->enable = !!value;
 844         s->invalidated = 1;
 845         s->vga.invalidate(&s->vga);
 846         if (s->enable && s->config) {
 847             vga_dirty_log_stop(&s->vga);
 848         } else {
 849             vga_dirty_log_start(&s->vga);
 850         }
 851         break;
 852
 853     case SVGA_REG_WIDTH:
 854         if (value <= SVGA_MAX_WIDTH) {
 855             s->new_width = value;
 856             s->invalidated = 1;
 857         } else {
 858             printf("%s: Bad width: %i\n", __func__, value);
 859         }
 860         break;
 861
 862     case SVGA_REG_HEIGHT:
 863         if (value <= SVGA_MAX_HEIGHT) {
 864             s->new_height = value;
 865             s->invalidated = 1;
 866         } else {
 867             printf("%s: Bad height: %i\n", __func__, value);
 868         }
 869         break;
 870
 871     case SVGA_REG_BITS_PER_PIXEL:
 872         if (value != s->depth) {
 873             printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
 874             s->config = 0;
 875         }
 876         break;
 877
 878     case SVGA_REG_CONFIG_DONE:
 879         if (value) {
 880             s->fifo = (uint32_t *) s->fifo_ptr;
 881             /* Check range and alignment.  */
 882             if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
 883                 break;
 884             }
 885             if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
 886                 break;
 887             }
 888             if (CMD(max) > SVGA_FIFO_SIZE) {
 889                 break;
 890             }
 891             if (CMD(max) < CMD(min) + 10 * 1024) {
 892                 break;
 893             }
 894             vga_dirty_log_stop(&s->vga);
 895         }
 896         s->config = !!value;
 897         break;
 898
 899     case SVGA_REG_SYNC:
 900         s->syncing = 1;
 901         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 902         break;
 903
 904     case SVGA_REG_GUEST_ID:
 905         s->guest = value;
 906 #ifdef VERBOSE
 907         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 908             ARRAY_SIZE(vmsvga_guest_id)) {
 909             printf("%s: guest runs %s.\n", __func__,
 910                    vmsvga_guest_id[value - GUEST_OS_BASE]);
 911         }
 912 #endif
 913         break;
 914
 915     case SVGA_REG_CURSOR_ID:
 916         s->cursor.id = value;
 917         break;
 918
 919     case SVGA_REG_CURSOR_X:
 920         s->cursor.x = value;
 921         break;
 922
 923     case SVGA_REG_CURSOR_Y:
 924         s->cursor.y = value;
 925         break;
 926
 927     case SVGA_REG_CURSOR_ON:
 928         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 929         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 930 #ifdef HW_MOUSE_ACCEL
 931         if (value <= SVGA_CURSOR_ON_SHOW) {
 932             dpy_mouse_set(s->vga.ds, s->cursor.x, s->cursor.y, s->cursor.on);
 933         }
 934 #endif
 935         break;
 936
 937     case SVGA_REG_DEPTH:
 938     case SVGA_REG_MEM_REGS:
 939     case SVGA_REG_NUM_DISPLAYS:
 940     case SVGA_REG_PITCHLOCK:
 941     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 942         break;
 943
 944     default:
 945         if (s->index >= SVGA_SCRATCH_BASE &&
 946                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 947             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 948             break;
 949         }
 950         printf("%s: Bad register %02x\n", __func__, s->index);
 951     }
 952 }
 953
 954 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 955 {
 956     printf("%s: what are we supposed to return?\n", __func__);
 957     return 0xcafe;
 958 }
 959
 960 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 961 {
 962     printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
 963 }
 964
 965 static inline void vmsvga_check_size(struct vmsvga_state_s *s)
 966 {
 967     if (s->new_width != ds_get_width(s->vga.ds) ||
 968         s->new_height != ds_get_height(s->vga.ds)) {
 969         qemu_console_resize(s->vga.ds, s->new_width, s->new_height);
 970         s->invalidated = 1;
 971     }
 972 }
 973
 974 static void vmsvga_update_display(void *opaque)
 975 {
 976     struct vmsvga_state_s *s = opaque;
 977     bool dirty = false;
 978
 979     if (!s->enable) {
 980         s->vga.update(&s->vga);
 981         return;
 982     }
 983
 984     vmsvga_check_size(s);
 985
 986     vmsvga_fifo_run(s);
 987     vmsvga_update_rect_flush(s);
 988
 989     /*
 990      * Is it more efficient to look at vram VGA-dirty bits or wait
 991      * for the driver to issue SVGA_CMD_UPDATE?
 992      */
 993     if (memory_region_is_logging(&s->vga.vram)) {
 994         vga_sync_dirty_bitmap(&s->vga);
 995         dirty = memory_region_get_dirty(&s->vga.vram, 0,
 996             ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds),
 997             DIRTY_MEMORY_VGA);
 998     }
 999     if (s->invalidated || dirty) {
1000         s->invalidated = 0;
1001         memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
1002                ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds));
1003         dpy_gfx_update(s->vga.ds, 0, 0,
1004                    ds_get_width(s->vga.ds), ds_get_height(s->vga.ds));
1005     }
1006     if (dirty) {
1007         memory_region_reset_dirty(&s->vga.vram, 0,
1008             ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds),
1009             DIRTY_MEMORY_VGA);
1010     }
1011 }
1012
1013 static void vmsvga_reset(DeviceState *dev)
1014 {
1015     struct pci_vmsvga_state_s *pci =
1016         DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
1017     struct vmsvga_state_s *s = &pci->chip;
1018
1019     s->index = 0;
1020     s->enable = 0;
1021     s->config = 0;
1022     s->svgaid = SVGA_ID;
1023     s->cursor.on = 0;
1024     s->redraw_fifo_first = 0;
1025     s->redraw_fifo_last = 0;
1026     s->syncing = 0;
1027
1028     vga_dirty_log_start(&s->vga);
1029 }
1030
1031 static void vmsvga_invalidate_display(void *opaque)
1032 {
1033     struct vmsvga_state_s *s = opaque;
1034     if (!s->enable) {
1035         s->vga.invalidate(&s->vga);
1036         return;
1037     }
1038
1039     s->invalidated = 1;
1040 }
1041
1042 /* save the vga display in a PPM image even if no display is
1043    available */
1044 static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch,
1045                                Error **errp)
1046 {
1047     struct vmsvga_state_s *s = opaque;
1048     if (!s->enable) {
1049         s->vga.screen_dump(&s->vga, filename, cswitch, errp);
1050         return;
1051     }
1052
1053     if (ds_get_bits_per_pixel(s->vga.ds) == 32) {
1054         DisplaySurface *ds = qemu_create_displaysurface_from(
1055                                  ds_get_width(s->vga.ds),
1056                                  ds_get_height(s->vga.ds),
1057                                  32,
1058                                  ds_get_linesize(s->vga.ds),
1059                                  s->vga.vram_ptr);
1060         ppm_save(filename, ds, errp);
1061         g_free(ds);
1062     }
1063 }
1064
1065 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1066 {
1067     struct vmsvga_state_s *s = opaque;
1068
1069     if (s->vga.text_update) {
1070         s->vga.text_update(&s->vga, chardata);
1071     }
1072 }
1073
1074 static int vmsvga_post_load(void *opaque, int version_id)
1075 {
1076     struct vmsvga_state_s *s = opaque;
1077
1078     s->invalidated = 1;
1079     if (s->config) {
1080         s->fifo = (uint32_t *) s->fifo_ptr;
1081     }
1082     return 0;
1083 }
1084
1085 static const VMStateDescription vmstate_vmware_vga_internal = {
1086     .name = "vmware_vga_internal",
1087     .version_id = 0,
1088     .minimum_version_id = 0,
1089     .minimum_version_id_old = 0,
1090     .post_load = vmsvga_post_load,
1091     .fields      = (VMStateField[]) {
1092         VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1093         VMSTATE_INT32(enable, struct vmsvga_state_s),
1094         VMSTATE_INT32(config, struct vmsvga_state_s),
1095         VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1096         VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1097         VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1098         VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1099         VMSTATE_INT32(index, struct vmsvga_state_s),
1100         VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1101                              scratch_size, 0, vmstate_info_uint32, uint32_t),
1102         VMSTATE_INT32(new_width, struct vmsvga_state_s),
1103         VMSTATE_INT32(new_height, struct vmsvga_state_s),
1104         VMSTATE_UINT32(guest, struct vmsvga_state_s),
1105         VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1106         VMSTATE_INT32(syncing, struct vmsvga_state_s),
1107         VMSTATE_UNUSED(4), /* was fb_size */
1108         VMSTATE_END_OF_LIST()
1109     }
1110 };
1111
1112 static const VMStateDescription vmstate_vmware_vga = {
1113     .name = "vmware_vga",
1114     .version_id = 0,
1115     .minimum_version_id = 0,
1116     .minimum_version_id_old = 0,
1117     .fields      = (VMStateField[]) {
1118         VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1119         VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1120                        vmstate_vmware_vga_internal, struct vmsvga_state_s),
1121         VMSTATE_END_OF_LIST()
1122     }
1123 };
1124
1125 static void vmsvga_init(struct vmsvga_state_s *s,
1126                         MemoryRegion *address_space, MemoryRegion *io)
1127 {
1128     s->scratch_size = SVGA_SCRATCH_SIZE;
1129     s->scratch = g_malloc(s->scratch_size * 4);
1130
1131     s->vga.ds = graphic_console_init(vmsvga_update_display,
1132                                      vmsvga_invalidate_display,
1133                                      vmsvga_screen_dump,
1134                                      vmsvga_text_update, s);
1135
1136
1137     s->fifo_size = SVGA_FIFO_SIZE;
1138     memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
1139     vmstate_register_ram_global(&s->fifo_ram);
1140     s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1141
1142     vga_common_init(&s->vga);
1143     vga_init(&s->vga, address_space, io, true);
1144     vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1145     /* Save some values here in case they are changed later.
1146      * This is suspicious and needs more though why it is needed. */
1147     s->depth = ds_get_bits_per_pixel(s->vga.ds);
1148     s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
1149     s->wred = ds_get_rmask(s->vga.ds);
1150     s->wgreen = ds_get_gmask(s->vga.ds);
1151     s->wblue = ds_get_bmask(s->vga.ds);
1152 }
1153
1154 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
1155 {
1156     struct vmsvga_state_s *s = opaque;
1157
1158     switch (addr) {
1159     case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1160     case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1161     case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1162     default: return -1u;
1163     }
1164 }
1165
1166 static void vmsvga_io_write(void *opaque, hwaddr addr,
1167                             uint64_t data, unsigned size)
1168 {
1169     struct vmsvga_state_s *s = opaque;
1170
1171     switch (addr) {
1172     case SVGA_IO_MUL * SVGA_INDEX_PORT:
1173         vmsvga_index_write(s, addr, data);
1174         break;
1175     case SVGA_IO_MUL * SVGA_VALUE_PORT:
1176         vmsvga_value_write(s, addr, data);
1177         break;
1178     case SVGA_IO_MUL * SVGA_BIOS_PORT:
1179         vmsvga_bios_write(s, addr, data);
1180         break;
1181     }
1182 }
1183
1184 static const MemoryRegionOps vmsvga_io_ops = {
1185     .read = vmsvga_io_read,
1186     .write = vmsvga_io_write,
1187     .endianness = DEVICE_LITTLE_ENDIAN,
1188     .valid = {
1189         .min_access_size = 4,
1190         .max_access_size = 4,
1191     },
1192 };
1193
1194 static int pci_vmsvga_initfn(PCIDevice *dev)
1195 {
1196     struct pci_vmsvga_state_s *s =
1197         DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1198
1199     s->card.config[PCI_CACHE_LINE_SIZE] = 0x08;         /* Cache line size */
1200     s->card.config[PCI_LATENCY_TIMER] = 0x40;           /* Latency timer */
1201     s->card.config[PCI_INTERRUPT_LINE] = 0xff;          /* End */
1202
1203     memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
1204                           "vmsvga-io", 0x10);
1205     memory_region_set_flush_coalesced(&s->io_bar);
1206     pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1207
1208     vmsvga_init(&s->chip, pci_address_space(dev), pci_address_space_io(dev));
1209
1210     pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
1211                      &s->chip.vga.vram);
1212     pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1213                      &s->chip.fifo_ram);
1214
1215     if (!dev->rom_bar) {
1216         /* compatibility with pc-0.13 and older */
1217         vga_init_vbe(&s->chip.vga, pci_address_space(dev));
1218     }
1219
1220     return 0;
1221 }
1222
1223 static Property vga_vmware_properties[] = {
1224     DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1225                        chip.vga.vram_size_mb, 16),
1226     DEFINE_PROP_END_OF_LIST(),
1227 };
1228
1229 static void vmsvga_class_init(ObjectClass *klass, void *data)
1230 {
1231     DeviceClass *dc = DEVICE_CLASS(klass);
1232     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1233
1234     k->no_hotplug = 1;
1235     k->init = pci_vmsvga_initfn;
1236     k->romfile = "vgabios-vmware.bin";
1237     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1238     k->device_id = SVGA_PCI_DEVICE_ID;
1239     k->class_id = PCI_CLASS_DISPLAY_VGA;
1240     k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1241     k->subsystem_id = SVGA_PCI_DEVICE_ID;
1242     dc->reset = vmsvga_reset;
1243     dc->vmsd = &vmstate_vmware_vga;
1244     dc->props = vga_vmware_properties;
1245 }
1246
1247 static const TypeInfo vmsvga_info = {
1248     .name          = "vmware-svga",
1249     .parent        = TYPE_PCI_DEVICE,
1250     .instance_size = sizeof(struct pci_vmsvga_state_s),
1251     .class_init    = vmsvga_class_init,
1252 };
1253
1254 static void vmsvga_register_types(void)
1255 {
1256     type_register_static(&vmsvga_info);
1257 }
1258
1259 type_init(vmsvga_register_types)