?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PPC: Fix missing TRACE exception
[qemu/agraf.git] / target-i386 / cpu.c
blob64c34910a0f0dfcb1000a6e59cecf224e3e2171a
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 #include "sysemu.h"
41 #ifndef CONFIG_USER_ONLY
42 #include "hw/xen.h"
43 #include "hw/sysbus.h"
44 #include "hw/apic_internal.h"
45 #endif
46
47 /* feature flags taken from "Intel Processor Identification and the CPUID
48 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
49 * between feature naming conventions, aliases may be added.
50 */
51 static const char *feature_name[] = {
52 "fpu", "vme", "de", "pse",
53 "tsc", "msr", "pae", "mce",
54 "cx8", "apic", NULL, "sep",
55 "mtrr", "pge", "mca", "cmov",
56 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
57 NULL, "ds" /* Intel dts */, "acpi", "mmx",
58 "fxsr", "sse", "sse2", "ss",
59 "ht" /* Intel htt */, "tm", "ia64", "pbe",
60 };
61 static const char *ext_feature_name[] = {
62 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
63 "ds_cpl", "vmx", "smx", "est",
64 "tm2", "ssse3", "cid", NULL,
65 "fma", "cx16", "xtpr", "pdcm",
66 NULL, "pcid", "dca", "sse4.1|sse4_1",
67 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
68 "tsc-deadline", "aes", "xsave", "osxsave",
69 "avx", "f16c", "rdrand", "hypervisor",
70 };
71 /* Feature names that are already defined on feature_name[] but are set on
72 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
73 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
74 * if and only if CPU vendor is AMD.
75 */
76 static const char *ext2_feature_name[] = {
77 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
78 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
79 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
80 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
81 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
82 "nx|xd", NULL, "mmxext", NULL /* mmx */,
83 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
84 NULL, "lm|i64", "3dnowext", "3dnow",
85 };
86 static const char *ext3_feature_name[] = {
87 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
88 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
89 "3dnowprefetch", "osvw", "ibs", "xop",
90 "skinit", "wdt", NULL, "lwp",
91 "fma4", "tce", NULL, "nodeid_msr",
92 NULL, "tbm", "topoext", "perfctr_core",
93 "perfctr_nb", NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95 };
96
97 static const char *kvm_feature_name[] = {
98 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
99 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
100 NULL, NULL, NULL, NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 };
107
108 static const char *svm_feature_name[] = {
109 "npt", "lbrv", "svm_lock", "nrip_save",
110 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
111 NULL, NULL, "pause_filter", NULL,
112 "pfthreshold", NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 };
118
119 static const char *cpuid_7_0_ebx_feature_name[] = {
120 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
121 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
122 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
123 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
124 };
125
126 /* collects per-function cpuid data
127 */
128 typedef struct model_features_t {
129 uint32_t *guest_feat;
130 uint32_t *host_feat;
131 uint32_t check_feat;
132 const char **flag_names;
133 uint32_t cpuid;
134 } model_features_t;
135
136 int check_cpuid = 0;
137 int enforce_cpuid = 0;
138
139 #if defined(CONFIG_KVM)
140 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
141 (1 << KVM_FEATURE_NOP_IO_DELAY) |
142 (1 << KVM_FEATURE_MMU_OP) |
143 (1 << KVM_FEATURE_CLOCKSOURCE2) |
144 (1 << KVM_FEATURE_ASYNC_PF) |
145 (1 << KVM_FEATURE_STEAL_TIME) |
146 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
147 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
148 #else
149 static uint32_t kvm_default_features = 0;
150 static const uint32_t kvm_pv_eoi_features = 0;
151 #endif
152
153 void enable_kvm_pv_eoi(void)
154 {
155 kvm_default_features |= kvm_pv_eoi_features;
156 }
157
158 void host_cpuid(uint32_t function, uint32_t count,
159 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
160 {
161 #if defined(CONFIG_KVM)
162 uint32_t vec[4];
163
164 #ifdef __x86_64__
165 asm volatile("cpuid"
166 : "=a"(vec[0]), "=b"(vec[1]),
167 "=c"(vec[2]), "=d"(vec[3])
168 : "0"(function), "c"(count) : "cc");
169 #else
170 asm volatile("pusha \n\t"
171 "cpuid \n\t"
172 "mov %%eax, 0(%2) \n\t"
173 "mov %%ebx, 4(%2) \n\t"
174 "mov %%ecx, 8(%2) \n\t"
175 "mov %%edx, 12(%2) \n\t"
176 "popa"
177 : : "a"(function), "c"(count), "S"(vec)
178 : "memory", "cc");
179 #endif
180
181 if (eax)
182 *eax = vec[0];
183 if (ebx)
184 *ebx = vec[1];
185 if (ecx)
186 *ecx = vec[2];
187 if (edx)
188 *edx = vec[3];
189 #endif
190 }
191
192 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
193
194 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
195 * a substring. ex if !NULL points to the first char after a substring,
196 * otherwise the string is assumed to sized by a terminating nul.
197 * Return lexical ordering of *s1:*s2.
198 */
199 static int sstrcmp(const char *s1, const char *e1, const char *s2,
200 const char *e2)
201 {
202 for (;;) {
203 if (!*s1 || !*s2 || *s1 != *s2)
204 return (*s1 - *s2);
205 ++s1, ++s2;
206 if (s1 == e1 && s2 == e2)
207 return (0);
208 else if (s1 == e1)
209 return (*s2);
210 else if (s2 == e2)
211 return (*s1);
212 }
213 }
214
215 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
216 * '|' delimited (possibly empty) strings in which case search for a match
217 * within the alternatives proceeds left to right. Return 0 for success,
218 * non-zero otherwise.
219 */
220 static int altcmp(const char *s, const char *e, const char *altstr)
221 {
222 const char *p, *q;
223
224 for (q = p = altstr; ; ) {
225 while (*p && *p != '|')
226 ++p;
227 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
228 return (0);
229 if (!*p)
230 return (1);
231 else
232 q = ++p;
233 }
234 }
235
236 /* search featureset for flag *[s..e), if found set corresponding bit in
237 * *pval and return true, otherwise return false
238 */
239 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
240 const char **featureset)
241 {
242 uint32_t mask;
243 const char **ppc;
244 bool found = false;
245
246 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
247 if (*ppc && !altcmp(s, e, *ppc)) {
248 *pval |= mask;
249 found = true;
250 }
251 }
252 return found;
253 }
254
255 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
256 uint32_t *ext_features,
257 uint32_t *ext2_features,
258 uint32_t *ext3_features,
259 uint32_t *kvm_features,
260 uint32_t *svm_features,
261 uint32_t *cpuid_7_0_ebx_features)
262 {
263 if (!lookup_feature(features, flagname, NULL, feature_name) &&
264 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
265 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
266 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
267 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
268 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
269 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
270 cpuid_7_0_ebx_feature_name))
271 fprintf(stderr, "CPU feature %s not found\n", flagname);
272 }
273
274 typedef struct x86_def_t {
275 struct x86_def_t *next;
276 const char *name;
277 uint32_t level;
278 uint32_t vendor1, vendor2, vendor3;
279 int family;
280 int model;
281 int stepping;
282 int tsc_khz;
283 uint32_t features, ext_features, ext2_features, ext3_features;
284 uint32_t kvm_features, svm_features;
285 uint32_t xlevel;
286 char model_id[48];
287 int vendor_override;
288 /* Store the results of Centaur's CPUID instructions */
289 uint32_t ext4_features;
290 uint32_t xlevel2;
291 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
292 uint32_t cpuid_7_0_ebx_features;
293 } x86_def_t;
294
295 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
296 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
297 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
298 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
299 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
300 CPUID_PSE36 | CPUID_FXSR)
301 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
302 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
303 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
304 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
305 CPUID_PAE | CPUID_SEP | CPUID_APIC)
306
307 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
308 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
309 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
310 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
311 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
312 /* partly implemented:
313 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
314 CPUID_PSE36 (needed for Solaris) */
315 /* missing:
316 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
317 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
318 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
319 CPUID_EXT_HYPERVISOR)
320 /* missing:
321 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
322 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
323 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
324 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
325 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
326 /* missing:
327 CPUID_EXT2_PDPE1GB */
328 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
329 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
330 #define TCG_SVM_FEATURES 0
331 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
332
333 /* maintains list of cpu model definitions
334 */
335 static x86_def_t *x86_defs = {NULL};
336
337 /* built-in cpu model definitions (deprecated)
338 */
339 static x86_def_t builtin_x86_defs[] = {
340 {
341 .name = "qemu64",
342 .level = 4,
343 .vendor1 = CPUID_VENDOR_AMD_1,
344 .vendor2 = CPUID_VENDOR_AMD_2,
345 .vendor3 = CPUID_VENDOR_AMD_3,
346 .family = 6,
347 .model = 2,
348 .stepping = 3,
349 .features = PPRO_FEATURES |
350 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
351 CPUID_PSE36,
352 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
353 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
354 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
355 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
356 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
357 .xlevel = 0x8000000A,
358 },
359 {
360 .name = "phenom",
361 .level = 5,
362 .vendor1 = CPUID_VENDOR_AMD_1,
363 .vendor2 = CPUID_VENDOR_AMD_2,
364 .vendor3 = CPUID_VENDOR_AMD_3,
365 .family = 16,
366 .model = 2,
367 .stepping = 3,
368 .features = PPRO_FEATURES |
369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
370 CPUID_PSE36 | CPUID_VME | CPUID_HT,
371 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
372 CPUID_EXT_POPCNT,
373 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
374 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
375 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
376 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
377 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
378 CPUID_EXT3_CR8LEG,
379 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
380 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
381 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
382 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
383 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
384 .xlevel = 0x8000001A,
385 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
386 },
387 {
388 .name = "core2duo",
389 .level = 10,
390 .family = 6,
391 .model = 15,
392 .stepping = 11,
393 .features = PPRO_FEATURES |
394 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
395 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
396 CPUID_HT | CPUID_TM | CPUID_PBE,
397 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
398 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
399 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
400 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
401 .ext3_features = CPUID_EXT3_LAHF_LM,
402 .xlevel = 0x80000008,
403 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
404 },
405 {
406 .name = "kvm64",
407 .level = 5,
408 .vendor1 = CPUID_VENDOR_INTEL_1,
409 .vendor2 = CPUID_VENDOR_INTEL_2,
410 .vendor3 = CPUID_VENDOR_INTEL_3,
411 .family = 15,
412 .model = 6,
413 .stepping = 1,
414 /* Missing: CPUID_VME, CPUID_HT */
415 .features = PPRO_FEATURES |
416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
417 CPUID_PSE36,
418 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
420 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
421 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
422 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
423 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
424 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
425 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
426 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
427 .ext3_features = 0,
428 .xlevel = 0x80000008,
429 .model_id = "Common KVM processor"
430 },
431 {
432 .name = "qemu32",
433 .level = 4,
434 .family = 6,
435 .model = 3,
436 .stepping = 3,
437 .features = PPRO_FEATURES,
438 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
439 .xlevel = 0x80000004,
440 },
441 {
442 .name = "kvm32",
443 .level = 5,
444 .family = 15,
445 .model = 6,
446 .stepping = 1,
447 .features = PPRO_FEATURES |
448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
449 .ext_features = CPUID_EXT_SSE3,
450 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
451 .ext3_features = 0,
452 .xlevel = 0x80000008,
453 .model_id = "Common 32-bit KVM processor"
454 },
455 {
456 .name = "coreduo",
457 .level = 10,
458 .family = 6,
459 .model = 14,
460 .stepping = 8,
461 .features = PPRO_FEATURES | CPUID_VME |
462 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
463 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
464 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
465 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_NX,
467 .xlevel = 0x80000008,
468 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
469 },
470 {
471 .name = "486",
472 .level = 1,
473 .family = 4,
474 .model = 0,
475 .stepping = 0,
476 .features = I486_FEATURES,
477 .xlevel = 0,
478 },
479 {
480 .name = "pentium",
481 .level = 1,
482 .family = 5,
483 .model = 4,
484 .stepping = 3,
485 .features = PENTIUM_FEATURES,
486 .xlevel = 0,
487 },
488 {
489 .name = "pentium2",
490 .level = 2,
491 .family = 6,
492 .model = 5,
493 .stepping = 2,
494 .features = PENTIUM2_FEATURES,
495 .xlevel = 0,
496 },
497 {
498 .name = "pentium3",
499 .level = 2,
500 .family = 6,
501 .model = 7,
502 .stepping = 3,
503 .features = PENTIUM3_FEATURES,
504 .xlevel = 0,
505 },
506 {
507 .name = "athlon",
508 .level = 2,
509 .vendor1 = CPUID_VENDOR_AMD_1,
510 .vendor2 = CPUID_VENDOR_AMD_2,
511 .vendor3 = CPUID_VENDOR_AMD_3,
512 .family = 6,
513 .model = 2,
514 .stepping = 3,
515 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
516 CPUID_MCA,
517 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
518 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
519 .xlevel = 0x80000008,
520 },
521 {
522 .name = "n270",
523 /* original is on level 10 */
524 .level = 5,
525 .family = 6,
526 .model = 28,
527 .stepping = 2,
528 .features = PPRO_FEATURES |
529 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
530 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
531 /* Some CPUs got no CPUID_SEP */
532 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
533 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
534 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
535 CPUID_EXT2_NX,
536 .ext3_features = CPUID_EXT3_LAHF_LM,
537 .xlevel = 0x8000000A,
538 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
539 },
540 {
541 .name = "Conroe",
542 .level = 2,
543 .vendor1 = CPUID_VENDOR_INTEL_1,
544 .vendor2 = CPUID_VENDOR_INTEL_2,
545 .vendor3 = CPUID_VENDOR_INTEL_3,
546 .family = 6,
547 .model = 2,
548 .stepping = 3,
549 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
550 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
551 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
552 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
553 CPUID_DE | CPUID_FP87,
554 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
555 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
556 .ext3_features = CPUID_EXT3_LAHF_LM,
557 .xlevel = 0x8000000A,
558 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
559 },
560 {
561 .name = "Penryn",
562 .level = 2,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 6,
567 .model = 2,
568 .stepping = 3,
569 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
570 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
571 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
572 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
573 CPUID_DE | CPUID_FP87,
574 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
575 CPUID_EXT_SSE3,
576 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
577 .ext3_features = CPUID_EXT3_LAHF_LM,
578 .xlevel = 0x8000000A,
579 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
580 },
581 {
582 .name = "Nehalem",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_INTEL_1,
585 .vendor2 = CPUID_VENDOR_INTEL_2,
586 .vendor3 = CPUID_VENDOR_INTEL_3,
587 .family = 6,
588 .model = 2,
589 .stepping = 3,
590 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
594 CPUID_DE | CPUID_FP87,
595 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
596 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
597 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
598 .ext3_features = CPUID_EXT3_LAHF_LM,
599 .xlevel = 0x8000000A,
600 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
601 },
602 {
603 .name = "Westmere",
604 .level = 11,
605 .vendor1 = CPUID_VENDOR_INTEL_1,
606 .vendor2 = CPUID_VENDOR_INTEL_2,
607 .vendor3 = CPUID_VENDOR_INTEL_3,
608 .family = 6,
609 .model = 44,
610 .stepping = 1,
611 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
612 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
613 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
614 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
615 CPUID_DE | CPUID_FP87,
616 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
617 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
618 CPUID_EXT_SSE3,
619 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
620 .ext3_features = CPUID_EXT3_LAHF_LM,
621 .xlevel = 0x8000000A,
622 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
623 },
624 {
625 .name = "SandyBridge",
626 .level = 0xd,
627 .vendor1 = CPUID_VENDOR_INTEL_1,
628 .vendor2 = CPUID_VENDOR_INTEL_2,
629 .vendor3 = CPUID_VENDOR_INTEL_3,
630 .family = 6,
631 .model = 42,
632 .stepping = 1,
633 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
634 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
635 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
636 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
637 CPUID_DE | CPUID_FP87,
638 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
639 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
640 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
641 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
642 CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
644 CPUID_EXT2_SYSCALL,
645 .ext3_features = CPUID_EXT3_LAHF_LM,
646 .xlevel = 0x8000000A,
647 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
648 },
649 {
650 .name = "Haswell",
651 .level = 0xd,
652 .vendor1 = CPUID_VENDOR_INTEL_1,
653 .vendor2 = CPUID_VENDOR_INTEL_2,
654 .vendor3 = CPUID_VENDOR_INTEL_3,
655 .family = 6,
656 .model = 60,
657 .stepping = 1,
658 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
660 CPUID_PGE | CPUID_MTRR | CPUID_APIC | CPUID_CX8 |
661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
662 CPUID_DE | CPUID_FP87,
663 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
664 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
665 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
666 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
667 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
668 CPUID_EXT_PCID,
669 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
670 .ext3_features = CPUID_EXT3_LAHF_LM,
671 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
672 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
673 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
674 CPUID_7_0_EBX_RTM,
675 .xlevel = 0x8000000A,
676 .model_id = "Intel Core Processor (Haswell)",
677 },
678 {
679 .name = "Opteron_G1",
680 .level = 5,
681 .vendor1 = CPUID_VENDOR_AMD_1,
682 .vendor2 = CPUID_VENDOR_AMD_2,
683 .vendor3 = CPUID_VENDOR_AMD_3,
684 .family = 15,
685 .model = 6,
686 .stepping = 1,
687 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
688 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
689 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
690 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
691 CPUID_DE | CPUID_FP87,
692 .ext_features = CPUID_EXT_SSE3,
693 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
694 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
695 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
696 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
697 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
698 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
699 .xlevel = 0x80000008,
700 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
701 },
702 {
703 .name = "Opteron_G2",
704 .level = 5,
705 .vendor1 = CPUID_VENDOR_AMD_1,
706 .vendor2 = CPUID_VENDOR_AMD_2,
707 .vendor3 = CPUID_VENDOR_AMD_3,
708 .family = 15,
709 .model = 6,
710 .stepping = 1,
711 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
712 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
713 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
714 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
715 CPUID_DE | CPUID_FP87,
716 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
717 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
718 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
719 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
720 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
721 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
722 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
723 CPUID_EXT2_DE | CPUID_EXT2_FPU,
724 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
725 .xlevel = 0x80000008,
726 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
727 },
728 {
729 .name = "Opteron_G3",
730 .level = 5,
731 .vendor1 = CPUID_VENDOR_AMD_1,
732 .vendor2 = CPUID_VENDOR_AMD_2,
733 .vendor3 = CPUID_VENDOR_AMD_3,
734 .family = 15,
735 .model = 6,
736 .stepping = 1,
737 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
738 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
739 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
740 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
741 CPUID_DE | CPUID_FP87,
742 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
743 CPUID_EXT_SSE3,
744 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
745 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
746 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
747 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
748 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
749 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
750 CPUID_EXT2_DE | CPUID_EXT2_FPU,
751 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
752 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
753 .xlevel = 0x80000008,
754 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
755 },
756 {
757 .name = "Opteron_G4",
758 .level = 0xd,
759 .vendor1 = CPUID_VENDOR_AMD_1,
760 .vendor2 = CPUID_VENDOR_AMD_2,
761 .vendor3 = CPUID_VENDOR_AMD_3,
762 .family = 21,
763 .model = 1,
764 .stepping = 2,
765 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
766 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
767 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
768 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
769 CPUID_DE | CPUID_FP87,
770 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
771 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
772 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
773 CPUID_EXT_SSE3,
774 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
775 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
776 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
777 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
778 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
779 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
780 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
781 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
782 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
783 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
784 CPUID_EXT3_LAHF_LM,
785 .xlevel = 0x8000001A,
786 .model_id = "AMD Opteron 62xx class CPU",
787 },
788 {
789 .name = "Opteron_G5",
790 .level = 0xd,
791 .vendor1 = CPUID_VENDOR_AMD_1,
792 .vendor2 = CPUID_VENDOR_AMD_2,
793 .vendor3 = CPUID_VENDOR_AMD_3,
794 .family = 21,
795 .model = 2,
796 .stepping = 0,
797 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
801 CPUID_DE | CPUID_FP87,
802 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
803 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
804 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
805 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
806 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
807 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
808 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
809 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
810 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
811 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
812 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
813 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
814 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
815 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
816 CPUID_EXT3_LAHF_LM,
817 .xlevel = 0x8000001A,
818 .model_id = "AMD Opteron 63xx class CPU",
819 },
820 };
821
822 #ifdef CONFIG_KVM
823 static int cpu_x86_fill_model_id(char *str)
824 {
825 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
826 int i;
827
828 for (i = 0; i < 3; i++) {
829 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
830 memcpy(str + i * 16 + 0, &eax, 4);
831 memcpy(str + i * 16 + 4, &ebx, 4);
832 memcpy(str + i * 16 + 8, &ecx, 4);
833 memcpy(str + i * 16 + 12, &edx, 4);
834 }
835 return 0;
836 }
837 #endif
838
839 /* Fill a x86_def_t struct with information about the host CPU, and
840 * the CPU features supported by the host hardware + host kernel
841 *
842 * This function may be called only if KVM is enabled.
843 */
844 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
845 {
846 #ifdef CONFIG_KVM
847 KVMState *s = kvm_state;
848 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
849
850 assert(kvm_enabled());
851
852 x86_cpu_def->name = "host";
853 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
854 x86_cpu_def->vendor1 = ebx;
855 x86_cpu_def->vendor2 = edx;
856 x86_cpu_def->vendor3 = ecx;
857
858 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
859 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
860 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
861 x86_cpu_def->stepping = eax & 0x0F;
862
863 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
864 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
865 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
866
867 if (x86_cpu_def->level >= 7) {
868 x86_cpu_def->cpuid_7_0_ebx_features =
869 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
870 } else {
871 x86_cpu_def->cpuid_7_0_ebx_features = 0;
872 }
873
874 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
875 x86_cpu_def->ext2_features =
876 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
877 x86_cpu_def->ext3_features =
878 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
879
880 cpu_x86_fill_model_id(x86_cpu_def->model_id);
881 x86_cpu_def->vendor_override = 0;
882
883 /* Call Centaur's CPUID instruction. */
884 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
885 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
886 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
887 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
888 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
889 if (eax >= 0xC0000001) {
890 /* Support VIA max extended level */
891 x86_cpu_def->xlevel2 = eax;
892 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
893 x86_cpu_def->ext4_features =
894 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
895 }
896 }
897
898 /*
899 * Every SVM feature requires emulation support in KVM - so we can't just
900 * read the host features here. KVM might even support SVM features not
901 * available on the host hardware. Just set all bits and mask out the
902 * unsupported ones later.
903 */
904 x86_cpu_def->svm_features = -1;
905 #endif /* CONFIG_KVM */
906 }
907
908 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
909 {
910 int i;
911
912 for (i = 0; i < 32; ++i)
913 if (1 << i & mask) {
914 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
915 " flag '%s' [0x%08x]\n",
916 f->cpuid >> 16, f->cpuid & 0xffff,
917 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
918 break;
919 }
920 return 0;
921 }
922
923 /* best effort attempt to inform user requested cpu flags aren't making
924 * their way to the guest. Note: ft[].check_feat ideally should be
925 * specified via a guest_def field to suppress report of extraneous flags.
926 *
927 * This function may be called only if KVM is enabled.
928 */
929 static int kvm_check_features_against_host(x86_def_t *guest_def)
930 {
931 x86_def_t host_def;
932 uint32_t mask;
933 int rv, i;
934 struct model_features_t ft[] = {
935 {&guest_def->features, &host_def.features,
936 ~0, feature_name, 0x00000000},
937 {&guest_def->ext_features, &host_def.ext_features,
938 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
939 {&guest_def->ext2_features, &host_def.ext2_features,
940 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
941 {&guest_def->ext3_features, &host_def.ext3_features,
942 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
943
944 assert(kvm_enabled());
945
946 kvm_cpu_fill_host(&host_def);
947 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
948 for (mask = 1; mask; mask <<= 1)
949 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
950 !(*ft[i].host_feat & mask)) {
951 unavailable_host_feature(&ft[i], mask);
952 rv = 1;
953 }
954 return rv;
955 }
956
957 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
958 const char *name, Error **errp)
959 {
960 X86CPU *cpu = X86_CPU(obj);
961 CPUX86State *env = &cpu->env;
962 int64_t value;
963
964 value = (env->cpuid_version >> 8) & 0xf;
965 if (value == 0xf) {
966 value += (env->cpuid_version >> 20) & 0xff;
967 }
968 visit_type_int(v, &value, name, errp);
969 }
970
971 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
972 const char *name, Error **errp)
973 {
974 X86CPU *cpu = X86_CPU(obj);
975 CPUX86State *env = &cpu->env;
976 const int64_t min = 0;
977 const int64_t max = 0xff + 0xf;
978 int64_t value;
979
980 visit_type_int(v, &value, name, errp);
981 if (error_is_set(errp)) {
982 return;
983 }
984 if (value < min || value > max) {
985 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
986 name ? name : "null", value, min, max);
987 return;
988 }
989
990 env->cpuid_version &= ~0xff00f00;
991 if (value > 0x0f) {
992 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
993 } else {
994 env->cpuid_version |= value << 8;
995 }
996 }
997
998 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
999 const char *name, Error **errp)
1000 {
1001 X86CPU *cpu = X86_CPU(obj);
1002 CPUX86State *env = &cpu->env;
1003 int64_t value;
1004
1005 value = (env->cpuid_version >> 4) & 0xf;
1006 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1007 visit_type_int(v, &value, name, errp);
1008 }
1009
1010 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1011 const char *name, Error **errp)
1012 {
1013 X86CPU *cpu = X86_CPU(obj);
1014 CPUX86State *env = &cpu->env;
1015 const int64_t min = 0;
1016 const int64_t max = 0xff;
1017 int64_t value;
1018
1019 visit_type_int(v, &value, name, errp);
1020 if (error_is_set(errp)) {
1021 return;
1022 }
1023 if (value < min || value > max) {
1024 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1025 name ? name : "null", value, min, max);
1026 return;
1027 }
1028
1029 env->cpuid_version &= ~0xf00f0;
1030 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1031 }
1032
1033 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1034 void *opaque, const char *name,
1035 Error **errp)
1036 {
1037 X86CPU *cpu = X86_CPU(obj);
1038 CPUX86State *env = &cpu->env;
1039 int64_t value;
1040
1041 value = env->cpuid_version & 0xf;
1042 visit_type_int(v, &value, name, errp);
1043 }
1044
1045 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1046 void *opaque, const char *name,
1047 Error **errp)
1048 {
1049 X86CPU *cpu = X86_CPU(obj);
1050 CPUX86State *env = &cpu->env;
1051 const int64_t min = 0;
1052 const int64_t max = 0xf;
1053 int64_t value;
1054
1055 visit_type_int(v, &value, name, errp);
1056 if (error_is_set(errp)) {
1057 return;
1058 }
1059 if (value < min || value > max) {
1060 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1061 name ? name : "null", value, min, max);
1062 return;
1063 }
1064
1065 env->cpuid_version &= ~0xf;
1066 env->cpuid_version |= value & 0xf;
1067 }
1068
1069 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1070 const char *name, Error **errp)
1071 {
1072 X86CPU *cpu = X86_CPU(obj);
1073
1074 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1075 }
1076
1077 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1078 const char *name, Error **errp)
1079 {
1080 X86CPU *cpu = X86_CPU(obj);
1081
1082 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1083 }
1084
1085 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1086 const char *name, Error **errp)
1087 {
1088 X86CPU *cpu = X86_CPU(obj);
1089
1090 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1091 }
1092
1093 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1094 const char *name, Error **errp)
1095 {
1096 X86CPU *cpu = X86_CPU(obj);
1097
1098 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1099 }
1100
1101 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1102 {
1103 X86CPU *cpu = X86_CPU(obj);
1104 CPUX86State *env = &cpu->env;
1105 char *value;
1106 int i;
1107
1108 value = (char *)g_malloc(12 + 1);
1109 for (i = 0; i < 4; i++) {
1110 value[i ] = env->cpuid_vendor1 >> (8 * i);
1111 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1112 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1113 }
1114 value[12] = '\0';
1115 return value;
1116 }
1117
1118 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1119 Error **errp)
1120 {
1121 X86CPU *cpu = X86_CPU(obj);
1122 CPUX86State *env = &cpu->env;
1123 int i;
1124
1125 if (strlen(value) != 12) {
1126 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1127 "vendor", value);
1128 return;
1129 }
1130
1131 env->cpuid_vendor1 = 0;
1132 env->cpuid_vendor2 = 0;
1133 env->cpuid_vendor3 = 0;
1134 for (i = 0; i < 4; i++) {
1135 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1136 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1137 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1138 }
1139 env->cpuid_vendor_override = 1;
1140 }
1141
1142 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1143 {
1144 X86CPU *cpu = X86_CPU(obj);
1145 CPUX86State *env = &cpu->env;
1146 char *value;
1147 int i;
1148
1149 value = g_malloc(48 + 1);
1150 for (i = 0; i < 48; i++) {
1151 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1152 }
1153 value[48] = '\0';
1154 return value;
1155 }
1156
1157 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1158 Error **errp)
1159 {
1160 X86CPU *cpu = X86_CPU(obj);
1161 CPUX86State *env = &cpu->env;
1162 int c, len, i;
1163
1164 if (model_id == NULL) {
1165 model_id = "";
1166 }
1167 len = strlen(model_id);
1168 memset(env->cpuid_model, 0, 48);
1169 for (i = 0; i < 48; i++) {
1170 if (i >= len) {
1171 c = '\0';
1172 } else {
1173 c = (uint8_t)model_id[i];
1174 }
1175 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1176 }
1177 }
1178
1179 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1180 const char *name, Error **errp)
1181 {
1182 X86CPU *cpu = X86_CPU(obj);
1183 int64_t value;
1184
1185 value = cpu->env.tsc_khz * 1000;
1186 visit_type_int(v, &value, name, errp);
1187 }
1188
1189 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1190 const char *name, Error **errp)
1191 {
1192 X86CPU *cpu = X86_CPU(obj);
1193 const int64_t min = 0;
1194 const int64_t max = INT64_MAX;
1195 int64_t value;
1196
1197 visit_type_int(v, &value, name, errp);
1198 if (error_is_set(errp)) {
1199 return;
1200 }
1201 if (value < min || value > max) {
1202 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1203 name ? name : "null", value, min, max);
1204 return;
1205 }
1206
1207 cpu->env.tsc_khz = value / 1000;
1208 }
1209
1210 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1211 {
1212 unsigned int i;
1213 x86_def_t *def;
1214
1215 char *s = g_strdup(cpu_model);
1216 char *featurestr, *name = strtok(s, ",");
1217 /* Features to be added*/
1218 uint32_t plus_features = 0, plus_ext_features = 0;
1219 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1220 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1221 uint32_t plus_7_0_ebx_features = 0;
1222 /* Features to be removed */
1223 uint32_t minus_features = 0, minus_ext_features = 0;
1224 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1225 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1226 uint32_t minus_7_0_ebx_features = 0;
1227 uint32_t numvalue;
1228
1229 for (def = x86_defs; def; def = def->next)
1230 if (name && !strcmp(name, def->name))
1231 break;
1232 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1233 kvm_cpu_fill_host(x86_cpu_def);
1234 } else if (!def) {
1235 goto error;
1236 } else {
1237 memcpy(x86_cpu_def, def, sizeof(*def));
1238 }
1239
1240 add_flagname_to_bitmaps("hypervisor", &plus_features,
1241 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1242 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1243
1244 featurestr = strtok(NULL, ",");
1245
1246 while (featurestr) {
1247 char *val;
1248 if (featurestr[0] == '+') {
1249 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1250 &plus_ext_features, &plus_ext2_features,
1251 &plus_ext3_features, &plus_kvm_features,
1252 &plus_svm_features, &plus_7_0_ebx_features);
1253 } else if (featurestr[0] == '-') {
1254 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1255 &minus_ext_features, &minus_ext2_features,
1256 &minus_ext3_features, &minus_kvm_features,
1257 &minus_svm_features, &minus_7_0_ebx_features);
1258 } else if ((val = strchr(featurestr, '='))) {
1259 *val = 0; val++;
1260 if (!strcmp(featurestr, "family")) {
1261 char *err;
1262 numvalue = strtoul(val, &err, 0);
1263 if (!*val || *err || numvalue > 0xff + 0xf) {
1264 fprintf(stderr, "bad numerical value %s\n", val);
1265 goto error;
1266 }
1267 x86_cpu_def->family = numvalue;
1268 } else if (!strcmp(featurestr, "model")) {
1269 char *err;
1270 numvalue = strtoul(val, &err, 0);
1271 if (!*val || *err || numvalue > 0xff) {
1272 fprintf(stderr, "bad numerical value %s\n", val);
1273 goto error;
1274 }
1275 x86_cpu_def->model = numvalue;
1276 } else if (!strcmp(featurestr, "stepping")) {
1277 char *err;
1278 numvalue = strtoul(val, &err, 0);
1279 if (!*val || *err || numvalue > 0xf) {
1280 fprintf(stderr, "bad numerical value %s\n", val);
1281 goto error;
1282 }
1283 x86_cpu_def->stepping = numvalue ;
1284 } else if (!strcmp(featurestr, "level")) {
1285 char *err;
1286 numvalue = strtoul(val, &err, 0);
1287 if (!*val || *err) {
1288 fprintf(stderr, "bad numerical value %s\n", val);
1289 goto error;
1290 }
1291 x86_cpu_def->level = numvalue;
1292 } else if (!strcmp(featurestr, "xlevel")) {
1293 char *err;
1294 numvalue = strtoul(val, &err, 0);
1295 if (!*val || *err) {
1296 fprintf(stderr, "bad numerical value %s\n", val);
1297 goto error;
1298 }
1299 if (numvalue < 0x80000000) {
1300 numvalue += 0x80000000;
1301 }
1302 x86_cpu_def->xlevel = numvalue;
1303 } else if (!strcmp(featurestr, "vendor")) {
1304 if (strlen(val) != 12) {
1305 fprintf(stderr, "vendor string must be 12 chars long\n");
1306 goto error;
1307 }
1308 x86_cpu_def->vendor1 = 0;
1309 x86_cpu_def->vendor2 = 0;
1310 x86_cpu_def->vendor3 = 0;
1311 for(i = 0; i < 4; i++) {
1312 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1313 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1314 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1315 }
1316 x86_cpu_def->vendor_override = 1;
1317 } else if (!strcmp(featurestr, "model_id")) {
1318 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1319 val);
1320 } else if (!strcmp(featurestr, "tsc_freq")) {
1321 int64_t tsc_freq;
1322 char *err;
1323
1324 tsc_freq = strtosz_suffix_unit(val, &err,
1325 STRTOSZ_DEFSUFFIX_B, 1000);
1326 if (tsc_freq < 0 || *err) {
1327 fprintf(stderr, "bad numerical value %s\n", val);
1328 goto error;
1329 }
1330 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1331 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1332 char *err;
1333 numvalue = strtoul(val, &err, 0);
1334 if (!*val || *err) {
1335 fprintf(stderr, "bad numerical value %s\n", val);
1336 goto error;
1337 }
1338 hyperv_set_spinlock_retries(numvalue);
1339 } else {
1340 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1341 goto error;
1342 }
1343 } else if (!strcmp(featurestr, "check")) {
1344 check_cpuid = 1;
1345 } else if (!strcmp(featurestr, "enforce")) {
1346 check_cpuid = enforce_cpuid = 1;
1347 } else if (!strcmp(featurestr, "hv_relaxed")) {
1348 hyperv_enable_relaxed_timing(true);
1349 } else if (!strcmp(featurestr, "hv_vapic")) {
1350 hyperv_enable_vapic_recommended(true);
1351 } else {
1352 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1353 goto error;
1354 }
1355 featurestr = strtok(NULL, ",");
1356 }
1357 x86_cpu_def->features |= plus_features;
1358 x86_cpu_def->ext_features |= plus_ext_features;
1359 x86_cpu_def->ext2_features |= plus_ext2_features;
1360 x86_cpu_def->ext3_features |= plus_ext3_features;
1361 x86_cpu_def->kvm_features |= plus_kvm_features;
1362 x86_cpu_def->svm_features |= plus_svm_features;
1363 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1364 x86_cpu_def->features &= ~minus_features;
1365 x86_cpu_def->ext_features &= ~minus_ext_features;
1366 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1367 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1368 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1369 x86_cpu_def->svm_features &= ~minus_svm_features;
1370 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1371 if (check_cpuid && kvm_enabled()) {
1372 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1373 goto error;
1374 }
1375 if (x86_cpu_def->cpuid_7_0_ebx_features && x86_cpu_def->level < 7) {
1376 x86_cpu_def->level = 7;
1377 }
1378 g_free(s);
1379 return 0;
1380
1381 error:
1382 g_free(s);
1383 return -1;
1384 }
1385
1386 /* generate a composite string into buf of all cpuid names in featureset
1387 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1388 * if flags, suppress names undefined in featureset.
1389 */
1390 static void listflags(char *buf, int bufsize, uint32_t fbits,
1391 const char **featureset, uint32_t flags)
1392 {
1393 const char **p = &featureset[31];
1394 char *q, *b, bit;
1395 int nc;
1396
1397 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1398 *buf = '\0';
1399 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1400 if (fbits & 1 << bit && (*p || !flags)) {
1401 if (*p)
1402 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1403 else
1404 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1405 if (bufsize <= nc) {
1406 if (b) {
1407 memcpy(b, "...", sizeof("..."));
1408 }
1409 return;
1410 }
1411 q += nc;
1412 bufsize -= nc;
1413 }
1414 }
1415
1416 /* generate CPU information. */
1417 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1418 {
1419 x86_def_t *def;
1420 char buf[256];
1421
1422 for (def = x86_defs; def; def = def->next) {
1423 snprintf(buf, sizeof(buf), "%s", def->name);
1424 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1425 }
1426 if (kvm_enabled()) {
1427 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1428 }
1429 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1430 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1431 (*cpu_fprintf)(f, " %s\n", buf);
1432 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1433 (*cpu_fprintf)(f, " %s\n", buf);
1434 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1435 (*cpu_fprintf)(f, " %s\n", buf);
1436 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1437 (*cpu_fprintf)(f, " %s\n", buf);
1438 }
1439
1440 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1441 {
1442 CpuDefinitionInfoList *cpu_list = NULL;
1443 x86_def_t *def;
1444
1445 for (def = x86_defs; def; def = def->next) {
1446 CpuDefinitionInfoList *entry;
1447 CpuDefinitionInfo *info;
1448
1449 info = g_malloc0(sizeof(*info));
1450 info->name = g_strdup(def->name);
1451
1452 entry = g_malloc0(sizeof(*entry));
1453 entry->value = info;
1454 entry->next = cpu_list;
1455 cpu_list = entry;
1456 }
1457
1458 return cpu_list;
1459 }
1460
1461 #ifdef CONFIG_KVM
1462 static void filter_features_for_kvm(X86CPU *cpu)
1463 {
1464 CPUX86State *env = &cpu->env;
1465 KVMState *s = kvm_state;
1466
1467 env->cpuid_features &=
1468 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1469 env->cpuid_ext_features &=
1470 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1471 env->cpuid_ext2_features &=
1472 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1473 env->cpuid_ext3_features &=
1474 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1475 env->cpuid_svm_features &=
1476 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1477 env->cpuid_7_0_ebx_features &=
1478 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1479 env->cpuid_kvm_features &=
1480 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1481 env->cpuid_ext4_features &=
1482 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1483
1484 }
1485 #endif
1486
1487 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1488 {
1489 CPUX86State *env = &cpu->env;
1490 x86_def_t def1, *def = &def1;
1491 Error *error = NULL;
1492
1493 memset(def, 0, sizeof(*def));
1494
1495 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1496 return -1;
1497 if (def->vendor1) {
1498 env->cpuid_vendor1 = def->vendor1;
1499 env->cpuid_vendor2 = def->vendor2;
1500 env->cpuid_vendor3 = def->vendor3;
1501 } else {
1502 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1503 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1504 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1505 }
1506 env->cpuid_vendor_override = def->vendor_override;
1507 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1508 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1509 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1510 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1511 env->cpuid_features = def->features;
1512 env->cpuid_ext_features = def->ext_features;
1513 env->cpuid_ext2_features = def->ext2_features;
1514 env->cpuid_ext3_features = def->ext3_features;
1515 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1516 env->cpuid_kvm_features = def->kvm_features;
1517 env->cpuid_svm_features = def->svm_features;
1518 env->cpuid_ext4_features = def->ext4_features;
1519 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1520 env->cpuid_xlevel2 = def->xlevel2;
1521 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1522 "tsc-frequency", &error);
1523
1524 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1525 * CPUID[1].EDX.
1526 */
1527 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1528 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1529 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1530 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1531 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1532 }
1533
1534 if (!kvm_enabled()) {
1535 env->cpuid_features &= TCG_FEATURES;
1536 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1537 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1538 #ifdef TARGET_X86_64
1539 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1540 #endif
1541 );
1542 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1543 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1544 } else {
1545 #ifdef CONFIG_KVM
1546 filter_features_for_kvm(cpu);
1547 #endif
1548 }
1549 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1550 if (error) {
1551 fprintf(stderr, "%s\n", error_get_pretty(error));
1552 error_free(error);
1553 return -1;
1554 }
1555 return 0;
1556 }
1557
1558 #if !defined(CONFIG_USER_ONLY)
1559
1560 void cpu_clear_apic_feature(CPUX86State *env)
1561 {
1562 env->cpuid_features &= ~CPUID_APIC;
1563 }
1564
1565 #endif /* !CONFIG_USER_ONLY */
1566
1567 /* Initialize list of CPU models, filling some non-static fields if necessary
1568 */
1569 void x86_cpudef_setup(void)
1570 {
1571 int i, j;
1572 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1573
1574 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1575 x86_def_t *def = &builtin_x86_defs[i];
1576 def->next = x86_defs;
1577
1578 /* Look for specific "cpudef" models that */
1579 /* have the QEMU version in .model_id */
1580 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1581 if (strcmp(model_with_versions[j], def->name) == 0) {
1582 pstrcpy(def->model_id, sizeof(def->model_id),
1583 "QEMU Virtual CPU version ");
1584 pstrcat(def->model_id, sizeof(def->model_id),
1585 qemu_get_version());
1586 break;
1587 }
1588 }
1589
1590 x86_defs = def;
1591 }
1592 }
1593
1594 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1595 uint32_t *ecx, uint32_t *edx)
1596 {
1597 *ebx = env->cpuid_vendor1;
1598 *edx = env->cpuid_vendor2;
1599 *ecx = env->cpuid_vendor3;
1600
1601 /* sysenter isn't supported on compatibility mode on AMD, syscall
1602 * isn't supported in compatibility mode on Intel.
1603 * Normally we advertise the actual cpu vendor, but you can override
1604 * this if you want to use KVM's sysenter/syscall emulation
1605 * in compatibility mode and when doing cross vendor migration
1606 */
1607 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1608 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1609 }
1610 }
1611
1612 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1613 uint32_t *eax, uint32_t *ebx,
1614 uint32_t *ecx, uint32_t *edx)
1615 {
1616 /* test if maximum index reached */
1617 if (index & 0x80000000) {
1618 if (index > env->cpuid_xlevel) {
1619 if (env->cpuid_xlevel2 > 0) {
1620 /* Handle the Centaur's CPUID instruction. */
1621 if (index > env->cpuid_xlevel2) {
1622 index = env->cpuid_xlevel2;
1623 } else if (index < 0xC0000000) {
1624 index = env->cpuid_xlevel;
1625 }
1626 } else {
1627 index = env->cpuid_xlevel;
1628 }
1629 }
1630 } else {
1631 if (index > env->cpuid_level)
1632 index = env->cpuid_level;
1633 }
1634
1635 switch(index) {
1636 case 0:
1637 *eax = env->cpuid_level;
1638 get_cpuid_vendor(env, ebx, ecx, edx);
1639 break;
1640 case 1:
1641 *eax = env->cpuid_version;
1642 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1643 *ecx = env->cpuid_ext_features;
1644 *edx = env->cpuid_features;
1645 if (env->nr_cores * env->nr_threads > 1) {
1646 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1647 *edx |= 1 << 28; /* HTT bit */
1648 }
1649 break;
1650 case 2:
1651 /* cache info: needed for Pentium Pro compatibility */
1652 *eax = 1;
1653 *ebx = 0;
1654 *ecx = 0;
1655 *edx = 0x2c307d;
1656 break;
1657 case 4:
1658 /* cache info: needed for Core compatibility */
1659 if (env->nr_cores > 1) {
1660 *eax = (env->nr_cores - 1) << 26;
1661 } else {
1662 *eax = 0;
1663 }
1664 switch (count) {
1665 case 0: /* L1 dcache info */
1666 *eax |= 0x0000121;
1667 *ebx = 0x1c0003f;
1668 *ecx = 0x000003f;
1669 *edx = 0x0000001;
1670 break;
1671 case 1: /* L1 icache info */
1672 *eax |= 0x0000122;
1673 *ebx = 0x1c0003f;
1674 *ecx = 0x000003f;
1675 *edx = 0x0000001;
1676 break;
1677 case 2: /* L2 cache info */
1678 *eax |= 0x0000143;
1679 if (env->nr_threads > 1) {
1680 *eax |= (env->nr_threads - 1) << 14;
1681 }
1682 *ebx = 0x3c0003f;
1683 *ecx = 0x0000fff;
1684 *edx = 0x0000001;
1685 break;
1686 default: /* end of info */
1687 *eax = 0;
1688 *ebx = 0;
1689 *ecx = 0;
1690 *edx = 0;
1691 break;
1692 }
1693 break;
1694 case 5:
1695 /* mwait info: needed for Core compatibility */
1696 *eax = 0; /* Smallest monitor-line size in bytes */
1697 *ebx = 0; /* Largest monitor-line size in bytes */
1698 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1699 *edx = 0;
1700 break;
1701 case 6:
1702 /* Thermal and Power Leaf */
1703 *eax = 0;
1704 *ebx = 0;
1705 *ecx = 0;
1706 *edx = 0;
1707 break;
1708 case 7:
1709 /* Structured Extended Feature Flags Enumeration Leaf */
1710 if (count == 0) {
1711 *eax = 0; /* Maximum ECX value for sub-leaves */
1712 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1713 *ecx = 0; /* Reserved */
1714 *edx = 0; /* Reserved */
1715 } else {
1716 *eax = 0;
1717 *ebx = 0;
1718 *ecx = 0;
1719 *edx = 0;
1720 }
1721 break;
1722 case 9:
1723 /* Direct Cache Access Information Leaf */
1724 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1725 *ebx = 0;
1726 *ecx = 0;
1727 *edx = 0;
1728 break;
1729 case 0xA:
1730 /* Architectural Performance Monitoring Leaf */
1731 if (kvm_enabled()) {
1732 KVMState *s = env->kvm_state;
1733
1734 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1735 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1736 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1737 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1738 } else {
1739 *eax = 0;
1740 *ebx = 0;
1741 *ecx = 0;
1742 *edx = 0;
1743 }
1744 break;
1745 case 0xD:
1746 /* Processor Extended State */
1747 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1748 *eax = 0;
1749 *ebx = 0;
1750 *ecx = 0;
1751 *edx = 0;
1752 break;
1753 }
1754 if (kvm_enabled()) {
1755 KVMState *s = env->kvm_state;
1756
1757 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1758 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1759 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1760 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1761 } else {
1762 *eax = 0;
1763 *ebx = 0;
1764 *ecx = 0;
1765 *edx = 0;
1766 }
1767 break;
1768 case 0x80000000:
1769 *eax = env->cpuid_xlevel;
1770 *ebx = env->cpuid_vendor1;
1771 *edx = env->cpuid_vendor2;
1772 *ecx = env->cpuid_vendor3;
1773 break;
1774 case 0x80000001:
1775 *eax = env->cpuid_version;
1776 *ebx = 0;
1777 *ecx = env->cpuid_ext3_features;
1778 *edx = env->cpuid_ext2_features;
1779
1780 /* The Linux kernel checks for the CMPLegacy bit and
1781 * discards multiple thread information if it is set.
1782 * So dont set it here for Intel to make Linux guests happy.
1783 */
1784 if (env->nr_cores * env->nr_threads > 1) {
1785 uint32_t tebx, tecx, tedx;
1786 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1787 if (tebx != CPUID_VENDOR_INTEL_1 ||
1788 tedx != CPUID_VENDOR_INTEL_2 ||
1789 tecx != CPUID_VENDOR_INTEL_3) {
1790 *ecx |= 1 << 1; /* CmpLegacy bit */
1791 }
1792 }
1793 break;
1794 case 0x80000002:
1795 case 0x80000003:
1796 case 0x80000004:
1797 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1798 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1799 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1800 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1801 break;
1802 case 0x80000005:
1803 /* cache info (L1 cache) */
1804 *eax = 0x01ff01ff;
1805 *ebx = 0x01ff01ff;
1806 *ecx = 0x40020140;
1807 *edx = 0x40020140;
1808 break;
1809 case 0x80000006:
1810 /* cache info (L2 cache) */
1811 *eax = 0;
1812 *ebx = 0x42004200;
1813 *ecx = 0x02008140;
1814 *edx = 0;
1815 break;
1816 case 0x80000008:
1817 /* virtual & phys address size in low 2 bytes. */
1818 /* XXX: This value must match the one used in the MMU code. */
1819 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1820 /* 64 bit processor */
1821 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1822 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1823 } else {
1824 if (env->cpuid_features & CPUID_PSE36)
1825 *eax = 0x00000024; /* 36 bits physical */
1826 else
1827 *eax = 0x00000020; /* 32 bits physical */
1828 }
1829 *ebx = 0;
1830 *ecx = 0;
1831 *edx = 0;
1832 if (env->nr_cores * env->nr_threads > 1) {
1833 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1834 }
1835 break;
1836 case 0x8000000A:
1837 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1838 *eax = 0x00000001; /* SVM Revision */
1839 *ebx = 0x00000010; /* nr of ASIDs */
1840 *ecx = 0;
1841 *edx = env->cpuid_svm_features; /* optional features */
1842 } else {
1843 *eax = 0;
1844 *ebx = 0;
1845 *ecx = 0;
1846 *edx = 0;
1847 }
1848 break;
1849 case 0xC0000000:
1850 *eax = env->cpuid_xlevel2;
1851 *ebx = 0;
1852 *ecx = 0;
1853 *edx = 0;
1854 break;
1855 case 0xC0000001:
1856 /* Support for VIA CPU's CPUID instruction */
1857 *eax = env->cpuid_version;
1858 *ebx = 0;
1859 *ecx = 0;
1860 *edx = env->cpuid_ext4_features;
1861 break;
1862 case 0xC0000002:
1863 case 0xC0000003:
1864 case 0xC0000004:
1865 /* Reserved for the future, and now filled with zero */
1866 *eax = 0;
1867 *ebx = 0;
1868 *ecx = 0;
1869 *edx = 0;
1870 break;
1871 default:
1872 /* reserved values: zero */
1873 *eax = 0;
1874 *ebx = 0;
1875 *ecx = 0;
1876 *edx = 0;
1877 break;
1878 }
1879 }
1880
1881 /* CPUClass::reset() */
1882 static void x86_cpu_reset(CPUState *s)
1883 {
1884 X86CPU *cpu = X86_CPU(s);
1885 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1886 CPUX86State *env = &cpu->env;
1887 int i;
1888
1889 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1890 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1891 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1892 }
1893
1894 xcc->parent_reset(s);
1895
1896
1897 memset(env, 0, offsetof(CPUX86State, breakpoints));
1898
1899 tlb_flush(env, 1);
1900
1901 env->old_exception = -1;
1902
1903 /* init to reset state */
1904
1905 #ifdef CONFIG_SOFTMMU
1906 env->hflags |= HF_SOFTMMU_MASK;
1907 #endif
1908 env->hflags2 |= HF2_GIF_MASK;
1909
1910 cpu_x86_update_cr0(env, 0x60000010);
1911 env->a20_mask = ~0x0;
1912 env->smbase = 0x30000;
1913
1914 env->idt.limit = 0xffff;
1915 env->gdt.limit = 0xffff;
1916 env->ldt.limit = 0xffff;
1917 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1918 env->tr.limit = 0xffff;
1919 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1920
1921 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1922 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1923 DESC_R_MASK | DESC_A_MASK);
1924 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1925 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1926 DESC_A_MASK);
1927 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1928 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1929 DESC_A_MASK);
1930 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1931 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1932 DESC_A_MASK);
1933 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1934 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1935 DESC_A_MASK);
1936 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1937 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1938 DESC_A_MASK);
1939
1940 env->eip = 0xfff0;
1941 env->regs[R_EDX] = env->cpuid_version;
1942
1943 env->eflags = 0x2;
1944
1945 /* FPU init */
1946 for (i = 0; i < 8; i++) {
1947 env->fptags[i] = 1;
1948 }
1949 env->fpuc = 0x37f;
1950
1951 env->mxcsr = 0x1f80;
1952
1953 env->pat = 0x0007040600070406ULL;
1954 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1955
1956 memset(env->dr, 0, sizeof(env->dr));
1957 env->dr[6] = DR6_FIXED_1;
1958 env->dr[7] = DR7_FIXED_1;
1959 cpu_breakpoint_remove_all(env, BP_CPU);
1960 cpu_watchpoint_remove_all(env, BP_CPU);
1961
1962 #if !defined(CONFIG_USER_ONLY)
1963 /* We hard-wire the BSP to the first CPU. */
1964 if (env->cpu_index == 0) {
1965 apic_designate_bsp(env->apic_state);
1966 }
1967
1968 env->halted = !cpu_is_bsp(cpu);
1969 #endif
1970 }
1971
1972 #ifndef CONFIG_USER_ONLY
1973 bool cpu_is_bsp(X86CPU *cpu)
1974 {
1975 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1976 }
1977
1978 /* TODO: remove me, when reset over QOM tree is implemented */
1979 static void x86_cpu_machine_reset_cb(void *opaque)
1980 {
1981 X86CPU *cpu = opaque;
1982 cpu_reset(CPU(cpu));
1983 }
1984 #endif
1985
1986 static void mce_init(X86CPU *cpu)
1987 {
1988 CPUX86State *cenv = &cpu->env;
1989 unsigned int bank;
1990
1991 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1992 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1993 (CPUID_MCE | CPUID_MCA)) {
1994 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1995 cenv->mcg_ctl = ~(uint64_t)0;
1996 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1997 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1998 }
1999 }
2000 }
2001
2002 #define MSI_ADDR_BASE 0xfee00000
2003
2004 #ifndef CONFIG_USER_ONLY
2005 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2006 {
2007 static int apic_mapped;
2008 CPUX86State *env = &cpu->env;
2009 APICCommonState *apic;
2010 const char *apic_type = "apic";
2011
2012 if (kvm_irqchip_in_kernel()) {
2013 apic_type = "kvm-apic";
2014 } else if (xen_enabled()) {
2015 apic_type = "xen-apic";
2016 }
2017
2018 env->apic_state = qdev_try_create(NULL, apic_type);
2019 if (env->apic_state == NULL) {
2020 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2021 return;
2022 }
2023
2024 object_property_add_child(OBJECT(cpu), "apic",
2025 OBJECT(env->apic_state), NULL);
2026 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2027 /* TODO: convert to link<> */
2028 apic = APIC_COMMON(env->apic_state);
2029 apic->cpu = cpu;
2030
2031 if (qdev_init(env->apic_state)) {
2032 error_setg(errp, "APIC device '%s' could not be initialized",
2033 object_get_typename(OBJECT(env->apic_state)));
2034 return;
2035 }
2036
2037 /* XXX: mapping more APICs at the same memory location */
2038 if (apic_mapped == 0) {
2039 /* NOTE: the APIC is directly connected to the CPU - it is not
2040 on the global memory bus. */
2041 /* XXX: what if the base changes? */
2042 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2043 apic_mapped = 1;
2044 }
2045 }
2046 #endif
2047
2048 void x86_cpu_realize(Object *obj, Error **errp)
2049 {
2050 X86CPU *cpu = X86_CPU(obj);
2051
2052 #ifndef CONFIG_USER_ONLY
2053 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2054
2055 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2056 x86_cpu_apic_init(cpu, errp);
2057 if (error_is_set(errp)) {
2058 return;
2059 }
2060 }
2061 #endif
2062
2063 mce_init(cpu);
2064 qemu_init_vcpu(&cpu->env);
2065 cpu_reset(CPU(cpu));
2066 }
2067
2068 static void x86_cpu_initfn(Object *obj)
2069 {
2070 X86CPU *cpu = X86_CPU(obj);
2071 CPUX86State *env = &cpu->env;
2072 static int inited;
2073
2074 cpu_exec_init(env);
2075
2076 object_property_add(obj, "family", "int",
2077 x86_cpuid_version_get_family,
2078 x86_cpuid_version_set_family, NULL, NULL, NULL);
2079 object_property_add(obj, "model", "int",
2080 x86_cpuid_version_get_model,
2081 x86_cpuid_version_set_model, NULL, NULL, NULL);
2082 object_property_add(obj, "stepping", "int",
2083 x86_cpuid_version_get_stepping,
2084 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2085 object_property_add(obj, "level", "int",
2086 x86_cpuid_get_level,
2087 x86_cpuid_set_level, NULL, NULL, NULL);
2088 object_property_add(obj, "xlevel", "int",
2089 x86_cpuid_get_xlevel,
2090 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2091 object_property_add_str(obj, "vendor",
2092 x86_cpuid_get_vendor,
2093 x86_cpuid_set_vendor, NULL);
2094 object_property_add_str(obj, "model-id",
2095 x86_cpuid_get_model_id,
2096 x86_cpuid_set_model_id, NULL);
2097 object_property_add(obj, "tsc-frequency", "int",
2098 x86_cpuid_get_tsc_freq,
2099 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2100
2101 env->cpuid_apic_id = env->cpu_index;
2102
2103 /* init various static tables used in TCG mode */
2104 if (tcg_enabled() && !inited) {
2105 inited = 1;
2106 optimize_flags_init();
2107 #ifndef CONFIG_USER_ONLY
2108 cpu_set_debug_excp_handler(breakpoint_handler);
2109 #endif
2110 }
2111 }
2112
2113 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2114 {
2115 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2116 CPUClass *cc = CPU_CLASS(oc);
2117
2118 xcc->parent_reset = cc->reset;
2119 cc->reset = x86_cpu_reset;
2120 }
2121
2122 static const TypeInfo x86_cpu_type_info = {
2123 .name = TYPE_X86_CPU,
2124 .parent = TYPE_CPU,
2125 .instance_size = sizeof(X86CPU),
2126 .instance_init = x86_cpu_initfn,
2127 .abstract = false,
2128 .class_size = sizeof(X86CPUClass),
2129 .class_init = x86_cpu_common_class_init,
2130 };
2131
2132 static void x86_cpu_register_types(void)
2133 {
2134 type_register_static(&x86_cpu_type_info);
2135 }
2136
2137 type_init(x86_cpu_register_types)
Qemu with PowerPC KVM improvements