hw/spapr_pci.c

   1 /*
   2  * QEMU sPAPR PCI host originated from Uninorth PCI host
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
   5  * Copyright (C) 2011 David Gibson, IBM Corporation.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "hw/spapr.h"
  29 #include "hw/spapr_pci.h"
  30 #include "exec-memory.h"
  31 #include <libfdt.h>
  32
  33 #include "hw/pci_internals.h"
  34
  35 static const uint32_t bars[] = {
  36     PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
  37     PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
  38     PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
  39     /*, PCI_ROM_ADDRESS*/
  40 };
  41
  42 static PCIDevice *find_dev(sPAPREnvironment *spapr,
  43                            uint64_t buid, uint32_t config_addr)
  44 {
  45     DeviceState *qdev;
  46     int devfn = (config_addr >> 8) & 0xFF;
  47     sPAPRPHBState *phb;
  48
  49     QLIST_FOREACH(phb, &spapr->phbs, list) {
  50         if (phb->buid != buid) {
  51             continue;
  52         }
  53
  54         QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
  55             PCIDevice *dev = (PCIDevice *)qdev;
  56             if (dev->devfn == devfn) {
  57                 return dev;
  58             }
  59         }
  60     }
  61
  62     return NULL;
  63 }
  64
  65 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
  66 {
  67     return ((arg >> 20) & 0xf00) | (arg & 0xff);
  68 }
  69
  70 static uint32_t rtas_read_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
  71                                         uint32_t limit, uint32_t len)
  72 {
  73     if ((addr + len) <= limit) {
  74         return pci_host_config_read_common(pci_dev, addr, limit, len);
  75     } else {
  76         return ~0x0;
  77     }
  78 }
  79
  80 static void rtas_write_pci_config_do(PCIDevice *pci_dev, uint32_t addr,
  81                                      uint32_t limit, uint32_t val,
  82                                      uint32_t len)
  83 {
  84     if ((addr + len) <= limit) {
  85         pci_host_config_write_common(pci_dev, addr, limit, val, len);
  86     }
  87 }
  88
  89 static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
  90                                      uint32_t token, uint32_t nargs,
  91                                      target_ulong args,
  92                                      uint32_t nret, target_ulong rets)
  93 {
  94     uint32_t val, size, addr;
  95     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
  96     PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
  97
  98     if (!dev) {
  99         rtas_st(rets, 0, -1);
 100         return;
 101     }
 102     size = rtas_ld(args, 3);
 103     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
 104     val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
 105     rtas_st(rets, 0, 0);
 106     rtas_st(rets, 1, val);
 107 }
 108
 109 static void rtas_read_pci_config(sPAPREnvironment *spapr,
 110                                  uint32_t token, uint32_t nargs,
 111                                  target_ulong args,
 112                                  uint32_t nret, target_ulong rets)
 113 {
 114     uint32_t val, size, addr;
 115     PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
 116
 117     if (!dev) {
 118         rtas_st(rets, 0, -1);
 119         return;
 120     }
 121     size = rtas_ld(args, 1);
 122     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
 123     val = rtas_read_pci_config_do(dev, addr, pci_config_size(dev), size);
 124     rtas_st(rets, 0, 0);
 125     rtas_st(rets, 1, val);
 126 }
 127
 128 static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
 129                                       uint32_t token, uint32_t nargs,
 130                                       target_ulong args,
 131                                       uint32_t nret, target_ulong rets)
 132 {
 133     uint32_t val, size, addr;
 134     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 135     PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
 136
 137     if (!dev) {
 138         rtas_st(rets, 0, -1);
 139         return;
 140     }
 141     val = rtas_ld(args, 4);
 142     size = rtas_ld(args, 3);
 143     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
 144     rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
 145     rtas_st(rets, 0, 0);
 146 }
 147
 148 static void rtas_write_pci_config(sPAPREnvironment *spapr,
 149                                   uint32_t token, uint32_t nargs,
 150                                   target_ulong args,
 151                                   uint32_t nret, target_ulong rets)
 152 {
 153     uint32_t val, size, addr;
 154     PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
 155
 156     if (!dev) {
 157         rtas_st(rets, 0, -1);
 158         return;
 159     }
 160     val = rtas_ld(args, 2);
 161     size = rtas_ld(args, 1);
 162     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
 163     rtas_write_pci_config_do(dev, addr, pci_config_size(dev), val, size);
 164     rtas_st(rets, 0, 0);
 165 }
 166
 167 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
 168 {
 169     /*
 170      * Here we need to convert pci_dev + irq_num to some unique value
 171      * which is less than number of IRQs on the specific bus (now it
 172      * is 16).  At the moment irq_num == device_id (number of the
 173      * slot?)
 174      * FIXME: we should swizzle in fn and irq_num
 175      */
 176     return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
 177 }
 178
 179 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
 180 {
 181     /*
 182      * Here we use the number returned by pci_spapr_map_irq to find a
 183      * corresponding qemu_irq.
 184      */
 185     sPAPRPHBState *phb = opaque;
 186
 187     qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
 188 }
 189
 190 static int spapr_phb_init(SysBusDevice *s)
 191 {
 192     sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
 193     int i;
 194
 195     /* Initialize the LSI table */
 196     for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
 197         qemu_irq qirq;
 198         uint32_t num;
 199
 200         qirq = spapr_allocate_irq(0, &num);
 201         if (!qirq) {
 202             return -1;
 203         }
 204
 205         phb->lsi_table[i].dt_irq = num;
 206         phb->lsi_table[i].qirq = qirq;
 207     }
 208
 209     return 0;
 210 }
 211
 212 static int spapr_main_pci_host_init(PCIDevice *d)
 213 {
 214     return 0;
 215 }
 216
 217 static void spapr_main_pci_host_class_init(ObjectClass *klass, void *data)
 218 {
 219     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 220
 221     k->init = spapr_main_pci_host_init;
 222 }
 223
 224 static DeviceInfo spapr_main_pci_host_info = {
 225     .name = "spapr-pci-host-bridge-pci",
 226     .size = sizeof(PCIDevice),
 227     .class_init = spapr_main_pci_host_class_init,
 228 };
 229
 230 static void spapr_phb_class_init(ObjectClass *klass, void *data)
 231 {
 232     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 233
 234     sdc->init = spapr_phb_init;
 235 }
 236
 237 static DeviceInfo spapr_phb_info = {
 238     .name = "spapr-pci-host-bridge",
 239     .size = sizeof(sPAPRPHBState),
 240     .class_init = spapr_phb_class_init,
 241 };
 242
 243 static void spapr_register_devices(void)
 244 {
 245     sysbus_qdev_register(&spapr_phb_info);
 246     pci_qdev_register(&spapr_main_pci_host_info);
 247 }
 248
 249 device_init(spapr_register_devices)
 250
 251 static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
 252                               unsigned size)
 253 {
 254     switch (size) {
 255     case 1:
 256         return cpu_inb(addr);
 257     case 2:
 258         return cpu_inw(addr);
 259     case 4:
 260         return cpu_inl(addr);
 261     }
 262     assert(0);
 263 }
 264
 265 static void spapr_io_write(void *opaque, target_phys_addr_t addr,
 266                            uint64_t data, unsigned size)
 267 {
 268     switch (size) {
 269     case 1:
 270         cpu_outb(addr, data);
 271         return;
 272     case 2:
 273         cpu_outw(addr, data);
 274         return;
 275     case 4:
 276         cpu_outl(addr, data);
 277         return;
 278     }
 279     assert(0);
 280 }
 281
 282 static MemoryRegionOps spapr_io_ops = {
 283     .endianness = DEVICE_LITTLE_ENDIAN,
 284     .read = spapr_io_read,
 285     .write = spapr_io_write
 286 };
 287
 288 void spapr_create_phb(sPAPREnvironment *spapr,
 289                       const char *busname, uint64_t buid,
 290                       uint64_t mem_win_addr, uint64_t mem_win_size,
 291                       uint64_t io_win_addr)
 292 {
 293     DeviceState *dev;
 294     SysBusDevice *s;
 295     sPAPRPHBState *phb;
 296     PCIBus *bus;
 297     char namebuf[strlen(busname)+11];
 298
 299     dev = qdev_create(NULL, "spapr-pci-host-bridge");
 300     qdev_init_nofail(dev);
 301     s = sysbus_from_qdev(dev);
 302     phb = FROM_SYSBUS(sPAPRPHBState, s);
 303
 304     phb->mem_win_addr = mem_win_addr;
 305
 306     sprintf(namebuf, "%s-mem", busname);
 307     memory_region_init(&phb->memspace, namebuf, INT64_MAX);
 308
 309     sprintf(namebuf, "%s-memwindow", busname);
 310     memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
 311                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
 312     memory_region_add_subregion(get_system_memory(), mem_win_addr,
 313                                 &phb->memwindow);
 314
 315     phb->io_win_addr = io_win_addr;
 316
 317     /* On ppc, we only have MMIO no specific IO space from the CPU
 318      * perspective.  In theory we ought to be able to embed the PCI IO
 319      * memory region direction in the system memory space.  However,
 320      * if any of the IO BAR subregions use the old_portio mechanism,
 321      * that won't be processed properly unless accessed from the
 322      * system io address space.  This hack to bounce things via
 323      * system_io works around the problem until all the users of
 324      * old_portion are updated */
 325     sprintf(namebuf, "%s-io", busname);
 326     memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
 327     /* FIXME: fix to support multiple PHBs */
 328     memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
 329
 330     sprintf(namebuf, "%s-iowindow", busname);
 331     memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
 332                           namebuf, SPAPR_PCI_IO_WIN_SIZE);
 333     memory_region_add_subregion(get_system_memory(), io_win_addr,
 334                                 &phb->iowindow);
 335
 336     phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
 337                                                  pci_spapr_set_irq,
 338                                                  pci_spapr_map_irq,
 339                                                  phb,
 340                                                  &phb->memspace, &phb->iospace,
 341                                                  PCI_DEVFN(0, 0),
 342                                                  SPAPR_PCI_NUM_LSI);
 343
 344     spapr_rtas_register("read-pci-config", rtas_read_pci_config);
 345     spapr_rtas_register("write-pci-config", rtas_write_pci_config);
 346     spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
 347     spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
 348
 349     QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
 350
 351     /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
 352 }
 353
 354 /* Macros to operate with address in OF binding to PCI */
 355 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
 356 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
 357 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
 358 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
 359 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
 360 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
 361 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
 362 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
 363 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
 364
 365 int spapr_populate_pci_devices(sPAPRPHBState *phb,
 366                                uint32_t xics_phandle,
 367                                void *fdt)
 368 {
 369     PCIBus *bus = phb->host_state.bus;
 370     int bus_off, i;
 371     char nodename[256];
 372     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
 373     struct {
 374         uint32_t hi;
 375         uint64_t child;
 376         uint64_t parent;
 377         uint64_t size;
 378     } __attribute__((packed)) ranges[] = {
 379         {
 380             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
 381             cpu_to_be64(phb->io_win_addr),
 382             cpu_to_be64(memory_region_size(&phb->iospace)),
 383         },
 384         {
 385             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
 386             cpu_to_be64(phb->mem_win_addr),
 387             cpu_to_be64(memory_region_size(&phb->memwindow)),
 388         },
 389     };
 390     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
 391     uint32_t interrupt_map_mask[] = {
 392         cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, 0x0};
 393     uint32_t interrupt_map[bus->nirq][7];
 394
 395     /* Start populating the FDT */
 396     sprintf(nodename, "pci@%" PRIx64, phb->buid);
 397     bus_off = fdt_add_subnode(fdt, 0, nodename);
 398     if (bus_off < 0) {
 399         return bus_off;
 400     }
 401
 402 #define _FDT(exp) \
 403     do { \
 404         int ret = (exp);                                           \
 405         if (ret < 0) {                                             \
 406             return ret;                                            \
 407         }                                                          \
 408     } while (0)
 409
 410     /* Write PHB properties */
 411     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
 412     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
 413     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
 414     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
 415     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
 416     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
 417     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
 418     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
 419     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
 420     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
 421
 422     /* Build the interrupt-map, this must matches what is done
 423      * in pci_spapr_map_irq
 424      */
 425     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
 426                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
 427     for (i = 0; i < 7; i++) {
 428         uint32_t *irqmap = interrupt_map[i];
 429         irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
 430         irqmap[1] = 0;
 431         irqmap[2] = 0;
 432         irqmap[3] = 0;
 433         irqmap[4] = cpu_to_be32(xics_phandle);
 434         irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq);
 435         irqmap[6] = cpu_to_be32(0x8);
 436     }
 437     /* Write interrupt map */
 438     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
 439                      7 * sizeof(interrupt_map[0])));
 440
 441     return 0;
 442 }