hw/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "sysbus.h"
  25 #include "arm-misc.h"
  26 #include "primecell.h"
  27 #include "devices.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "exec-memory.h"
  32
  33 #define SMP_BOOT_ADDR 0xe0000000
  34 #define SMP_BOOTREG_ADDR 0x10000030
  35
  36 #define VEXPRESS_BOARD_ID 0x8e0
  37
  38 static struct arm_boot_info vexpress_binfo = {
  39     .smp_loader_start = SMP_BOOT_ADDR,
  40     .smp_bootreg_addr = SMP_BOOTREG_ADDR,
  41 };
  42
  43 static void vexpress_a9_init(ram_addr_t ram_size,
  44                      const char *boot_device,
  45                      const char *kernel_filename, const char *kernel_cmdline,
  46                      const char *initrd_filename, const char *cpu_model)
  47 {
  48     CPUState *env = NULL;
  49     MemoryRegion *sysmem = get_system_memory();
  50     MemoryRegion *ram = g_new(MemoryRegion, 1);
  51     MemoryRegion *lowram = g_new(MemoryRegion, 1);
  52     MemoryRegion *vram = g_new(MemoryRegion, 1);
  53     MemoryRegion *sram = g_new(MemoryRegion, 1);
  54     MemoryRegion *hackram = g_new(MemoryRegion, 1);
  55     DeviceState *dev, *sysctl, *pl041;
  56     SysBusDevice *busdev;
  57     qemu_irq *irqp;
  58     qemu_irq pic[64];
  59     int n;
  60     qemu_irq cpu_irq[4];
  61     uint32_t proc_id;
  62     uint32_t sys_id;
  63     ram_addr_t low_ram_size, vram_size, sram_size;
  64
  65     if (!cpu_model) {
  66         cpu_model = "cortex-a9";
  67     }
  68
  69     for (n = 0; n < smp_cpus; n++) {
  70         env = cpu_init(cpu_model);
  71         if (!env) {
  72             fprintf(stderr, "Unable to find CPU definition\n");
  73             exit(1);
  74         }
  75         irqp = arm_pic_init_cpu(env);
  76         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
  77     }
  78
  79     if (ram_size > 0x40000000) {
  80         /* 1GB is the maximum the address space permits */
  81         fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n");
  82         exit(1);
  83     }
  84
  85     memory_region_init_ram(ram, "vexpress.highmem", ram_size);
  86     vmstate_register_ram_global(ram);
  87     low_ram_size = ram_size;
  88     if (low_ram_size > 0x4000000) {
  89         low_ram_size = 0x4000000;
  90     }
  91     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
  92      * address space should in theory be remappable to various
  93      * things including ROM or RAM; we always map the RAM there.
  94      */
  95     memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size);
  96     memory_region_add_subregion(sysmem, 0x0, lowram);
  97     memory_region_add_subregion(sysmem, 0x60000000, ram);
  98
  99     /* 0x1e000000 A9MPCore (SCU) private memory region */
 100     dev = qdev_create(NULL, "a9mpcore_priv");
 101     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 102     qdev_init_nofail(dev);
 103     busdev = sysbus_from_qdev(dev);
 104     vexpress_binfo.smp_priv_base = 0x1e000000;
 105     sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base);
 106     for (n = 0; n < smp_cpus; n++) {
 107         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 108     }
 109     /* Interrupts [42:0] are from the motherboard;
 110      * [47:43] are reserved; [63:48] are daughterboard
 111      * peripherals. Note that some documentation numbers
 112      * external interrupts starting from 32 (because the
 113      * A9MP has internal interrupts 0..31).
 114      */
 115     for (n = 0; n < 64; n++) {
 116         pic[n] = qdev_get_gpio_in(dev, n);
 117     }
 118
 119     /* Motherboard peripherals CS7 : 0x10000000 .. 0x10020000 */
 120     sys_id = 0x1190f500;
 121     proc_id = 0x0c000191;
 122
 123     /* 0x10000000 System registers */
 124     sysctl = qdev_create(NULL, "realview_sysctl");
 125     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 126     qdev_init_nofail(sysctl);
 127     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 128     sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
 129
 130     /* 0x10001000 SP810 system control */
 131     /* 0x10002000 serial bus PCI */
 132     /* 0x10004000 PL041 audio */
 133     pl041 = qdev_create(NULL, "pl041");
 134     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 135     qdev_init_nofail(pl041);
 136     sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
 137     sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]);
 138
 139     dev = sysbus_create_varargs("pl181", 0x10005000, pic[9], pic[10], NULL);
 140     /* Wire up MMC card detect and read-only signals */
 141     qdev_connect_gpio_out(dev, 0,
 142                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 143     qdev_connect_gpio_out(dev, 1,
 144                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 145
 146     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[12]);
 147     sysbus_create_simple("pl050_mouse", 0x10007000, pic[13]);
 148
 149     sysbus_create_simple("pl011", 0x10009000, pic[5]);
 150     sysbus_create_simple("pl011", 0x1000a000, pic[6]);
 151     sysbus_create_simple("pl011", 0x1000b000, pic[7]);
 152     sysbus_create_simple("pl011", 0x1000c000, pic[8]);
 153
 154     /* 0x1000f000 SP805 WDT */
 155
 156     sysbus_create_simple("sp804", 0x10011000, pic[2]);
 157     sysbus_create_simple("sp804", 0x10012000, pic[3]);
 158
 159     /* 0x10016000 Serial Bus DVI */
 160
 161     sysbus_create_simple("pl031", 0x10017000, pic[4]); /* RTC */
 162
 163     /* 0x1001a000 Compact Flash */
 164
 165     /* 0x1001f000 PL111 CLCD (motherboard) */
 166
 167     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 168
 169     /* 0x10020000 PL111 CLCD (daughterboard) */
 170     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 171
 172     /* 0x10060000 AXI RAM */
 173     /* 0x100e0000 PL341 Dynamic Memory Controller */
 174     /* 0x100e1000 PL354 Static Memory Controller */
 175     /* 0x100e2000 System Configuration Controller */
 176
 177     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 178     /* 0x100e5000 SP805 Watchdog module */
 179     /* 0x100e6000 BP147 TrustZone Protection Controller */
 180     /* 0x100e9000 PL301 'Fast' AXI matrix */
 181     /* 0x100ea000 PL301 'Slow' AXI matrix */
 182     /* 0x100ec000 TrustZone Address Space Controller */
 183     /* 0x10200000 CoreSight debug APB */
 184     /* 0x1e00a000 PL310 L2 Cache Controller */
 185     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 186
 187     /* CS0: NOR0 flash          : 0x40000000 .. 0x44000000 */
 188     /* CS4: NOR1 flash          : 0x44000000 .. 0x48000000 */
 189     /* CS2: SRAM                : 0x48000000 .. 0x4a000000 */
 190     sram_size = 0x2000000;
 191     memory_region_init_ram(sram, "vexpress.sram", sram_size);
 192     vmstate_register_ram_global(sram);
 193     memory_region_add_subregion(sysmem, 0x48000000, sram);
 194
 195     /* CS3: USB, ethernet, VRAM : 0x4c000000 .. 0x50000000 */
 196
 197     /* 0x4c000000 Video RAM */
 198     vram_size = 0x800000;
 199     memory_region_init_ram(vram, "vexpress.vram", vram_size);
 200     vmstate_register_ram_global(vram);
 201     memory_region_add_subregion(sysmem, 0x4c000000, vram);
 202
 203     /* 0x4e000000 LAN9118 Ethernet */
 204     if (nd_table[0].vlan) {
 205         lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
 206     }
 207
 208     /* 0x4f000000 ISP1761 USB */
 209
 210     /* ??? Hack to map an additional page of ram for the secondary CPU
 211        startup code.  I guess this works on real hardware because the
 212        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 213        until after Linux boots the secondary CPUs.  */
 214     memory_region_init_ram(hackram, "vexpress.hack", 0x1000);
 215     vmstate_register_ram_global(hackram);
 216     memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, hackram);
 217
 218     vexpress_binfo.ram_size = ram_size;
 219     vexpress_binfo.kernel_filename = kernel_filename;
 220     vexpress_binfo.kernel_cmdline = kernel_cmdline;
 221     vexpress_binfo.initrd_filename = initrd_filename;
 222     vexpress_binfo.nb_cpus = smp_cpus;
 223     vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
 224     vexpress_binfo.loader_start = 0x60000000;
 225     arm_load_kernel(first_cpu, &vexpress_binfo);
 226 }
 227
 228
 229 static QEMUMachine vexpress_a9_machine = {
 230     .name = "vexpress-a9",
 231     .desc = "ARM Versatile Express for Cortex-A9",
 232     .init = vexpress_a9_init,
 233     .use_scsi = 1,
 234     .max_cpus = 4,
 235 };
 236
 237 static void vexpress_machine_init(void)
 238 {
 239     qemu_register_machine(&vexpress_a9_machine);
 240 }
 241
 242 machine_init(vexpress_machine_init);