hw/etraxfs_ser.c

   1 /*
   2  * QEMU ETRAX System Emulator
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu-char.h"
  27 #include "qemu-log.h"
  28
  29 #define D(x)
  30
  31 #define RW_TR_CTRL     (0x00 / 4)
  32 #define RW_TR_DMA_EN   (0x04 / 4)
  33 #define RW_REC_CTRL    (0x08 / 4)
  34 #define RW_DOUT        (0x1c / 4)
  35 #define RS_STAT_DIN    (0x20 / 4)
  36 #define R_STAT_DIN     (0x24 / 4)
  37 #define RW_INTR_MASK   (0x2c / 4)
  38 #define RW_ACK_INTR    (0x30 / 4)
  39 #define R_INTR         (0x34 / 4)
  40 #define R_MASKED_INTR  (0x38 / 4)
  41 #define R_MAX          (0x3c / 4)
  42
  43 #define STAT_DAV     16
  44 #define STAT_TR_IDLE 22
  45 #define STAT_TR_RDY  24
  46
  47 struct etrax_serial
  48 {
  49     SysBusDevice busdev;
  50     CharDriverState *chr;
  51     qemu_irq irq;
  52
  53     int pending_tx;
  54
  55     uint8_t rx_fifo[16];
  56     unsigned int rx_fifo_pos;
  57     unsigned int rx_fifo_len;
  58
  59     /* Control registers.  */
  60     uint32_t regs[R_MAX];
  61 };
  62
  63 static void serial_update_handlers(struct etrax_serial *s);
  64
  65 static void ser_update_irq(struct etrax_serial *s)
  66 {
  67
  68     if (s->rx_fifo_len) {
  69         s->regs[R_INTR] |= 8;
  70     } else {
  71         s->regs[R_INTR] &= ~8;
  72     }
  73
  74     s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
  75     qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
  76 }
  77
  78 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
  79 {
  80     struct etrax_serial *s = opaque;
  81     D(CPUState *env = s->env);
  82     uint32_t r = 0;
  83
  84     addr >>= 2;
  85     switch (addr)
  86     {
  87         case R_STAT_DIN:
  88             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  89             if (s->rx_fifo_len) {
  90                 r |= 1 << STAT_DAV;
  91             }
  92             r |= 1 << STAT_TR_RDY;
  93             r |= 1 << STAT_TR_IDLE;
  94             break;
  95         case RS_STAT_DIN:
  96             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  97             if (s->rx_fifo_len) {
  98                 r |= 1 << STAT_DAV;
  99                 s->rx_fifo_len--;
 100                 serial_update_handlers(s);
 101             }
 102             r |= 1 << STAT_TR_RDY;
 103             r |= 1 << STAT_TR_IDLE;
 104             break;
 105         default:
 106             r = s->regs[addr];
 107             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
 108             break;
 109     }
 110     return r;
 111 }
 112
 113 static void
 114 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 115 {
 116     struct etrax_serial *s = opaque;
 117     unsigned char ch = value;
 118     D(CPUState *env = s->env);
 119
 120     D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));
 121     addr >>= 2;
 122     switch (addr)
 123     {
 124         case RW_DOUT:
 125             qemu_chr_fe_write(s->chr, &ch, 1);
 126             s->regs[R_INTR] |= 3;
 127             s->pending_tx = 1;
 128             s->regs[addr] = value;
 129             break;
 130         case RW_ACK_INTR:
 131             if (s->pending_tx) {
 132                 value &= ~1;
 133                 s->pending_tx = 0;
 134                 D(qemu_log("fixedup value=%x r_intr=%x\n",
 135                            value, s->regs[R_INTR]));
 136             }
 137             s->regs[addr] = value;
 138             s->regs[R_INTR] &= ~value;
 139             D(printf("r_intr=%x\n", s->regs[R_INTR]));
 140             break;
 141         default:
 142             s->regs[addr] = value;
 143             serial_update_handlers(s);
 144             break;
 145     }
 146     ser_update_irq(s);
 147 }
 148
 149 static CPUReadMemoryFunc * const ser_read[] = {
 150     NULL, NULL,
 151     &ser_readl,
 152 };
 153
 154 static CPUWriteMemoryFunc * const ser_write[] = {
 155     NULL, NULL,
 156     &ser_writel,
 157 };
 158
 159 static void serial_receive(struct etrax_serial *s, const uint8_t *buf, int size)
 160 {
 161     int i;
 162
 163     /* Got a byte.  */
 164     if (s->rx_fifo_len >= 16) {
 165         qemu_log("WARNING: UART dropped char.\n");
 166         return;
 167     }
 168
 169     for (i = 0; i < size; i++) {
 170         s->rx_fifo[s->rx_fifo_pos] = buf[i];
 171         s->rx_fifo_pos++;
 172         s->rx_fifo_pos &= 15;
 173         s->rx_fifo_len++;
 174     }
 175
 176     serial_update_handlers(s);
 177     ser_update_irq(s);
 178 }
 179
 180 static int serial_can_receive(struct etrax_serial *s)
 181 {
 182     int r;
 183
 184     /* Is the receiver enabled?  */
 185     if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
 186         return 0;
 187     }
 188
 189     r = sizeof(s->rx_fifo) - s->rx_fifo_len;
 190     return r;
 191 }
 192
 193 static void serial_receive_handler(void *opaque)
 194 {
 195     struct etrax_serial *s = opaque;
 196     uint8_t buf[32];
 197     int size;
 198
 199     size = serial_can_receive(s);
 200     size = MIN(size, sizeof(buf));
 201     size = qemu_chr_fe_read(s->chr, buf, size);
 202
 203     serial_receive(s, buf, size);
 204 }
 205
 206 static void serial_update_handlers(struct etrax_serial *s)
 207 {
 208     if (serial_can_receive(s) > 0) {
 209         qemu_chr_fe_set_handlers(s->chr, serial_receive_handler,
 210                                  NULL, NULL, s);
 211     } else {
 212         qemu_chr_fe_set_handlers(s->chr, NULL, NULL, NULL, s);
 213     }
 214 }
 215
 216 static void etraxfs_ser_reset(DeviceState *d)
 217 {
 218     struct etrax_serial *s = container_of(d, typeof(*s), busdev.qdev);
 219
 220     /* transmitter begins ready and idle.  */
 221     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
 222     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
 223
 224     s->regs[RW_REC_CTRL] = 0x10000;
 225     serial_update_handlers(s);
 226
 227 }
 228
 229 static int etraxfs_ser_init(SysBusDevice *dev)
 230 {
 231     struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
 232     int ser_regs;
 233
 234     sysbus_init_irq(dev, &s->irq);
 235     ser_regs = cpu_register_io_memory(ser_read, ser_write, s,
 236                                       DEVICE_NATIVE_ENDIAN);
 237     sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
 238     s->chr = qdev_init_chardev(&dev->qdev);
 239     if (s->chr) {
 240         qemu_chr_fe_open(s->chr);
 241         serial_update_handlers(s);
 242     }
 243     return 0;
 244 }
 245
 246 static SysBusDeviceInfo etraxfs_ser_info = {
 247     .init = etraxfs_ser_init,
 248     .qdev.name  = "etraxfs,serial",
 249     .qdev.size  = sizeof(struct etrax_serial),
 250     .qdev.reset = etraxfs_ser_reset,
 251 };
 252
 253 static void etraxfs_serial_register(void)
 254 {
 255     sysbus_register_withprop(&etraxfs_ser_info);
 256 }
 257
 258 device_init(etraxfs_serial_register)