hw/lm32_timer.c

   1 /*
   2  *  QEMU model of the LatticeMico32 timer block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32timer.pdf
  22  */
  23
  24 #include "hw.h"
  25 #include "sysbus.h"
  26 #include "trace.h"
  27 #include "qemu-timer.h"
  28 #include "qemu-error.h"
  29
  30 #define DEFAULT_FREQUENCY (50*1000000)
  31
  32 enum {
  33     R_SR = 0,
  34     R_CR,
  35     R_PERIOD,
  36     R_SNAPSHOT,
  37     R_MAX
  38 };
  39
  40 enum {
  41     SR_TO    = (1 << 0),
  42     SR_RUN   = (1 << 1),
  43 };
  44
  45 enum {
  46     CR_ITO   = (1 << 0),
  47     CR_CONT  = (1 << 1),
  48     CR_START = (1 << 2),
  49     CR_STOP  = (1 << 3),
  50 };
  51
  52 struct LM32TimerState {
  53     SysBusDevice busdev;
  54
  55     QEMUBH *bh;
  56     ptimer_state *ptimer;
  57
  58     qemu_irq irq;
  59     uint32_t freq_hz;
  60
  61     uint32_t regs[R_MAX];
  62 };
  63 typedef struct LM32TimerState LM32TimerState;
  64
  65 static void timer_update_irq(LM32TimerState *s)
  66 {
  67     int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
  68
  69     trace_lm32_timer_irq_state(state);
  70     qemu_set_irq(s->irq, state);
  71 }
  72
  73 static uint32_t timer_read(void *opaque, target_phys_addr_t addr)
  74 {
  75     LM32TimerState *s = opaque;
  76     uint32_t r = 0;
  77
  78     addr >>= 2;
  79     switch (addr) {
  80     case R_SR:
  81     case R_CR:
  82     case R_PERIOD:
  83         r = s->regs[addr];
  84         break;
  85     case R_SNAPSHOT:
  86         r = (uint32_t)ptimer_get_count(s->ptimer);
  87         break;
  88     default:
  89         error_report("lm32_timer: read access to unknown register 0x"
  90                 TARGET_FMT_plx, addr << 2);
  91         break;
  92     }
  93
  94     trace_lm32_timer_memory_read(addr << 2, r);
  95     return r;
  96 }
  97
  98 static void timer_write(void *opaque, target_phys_addr_t addr, uint32_t value)
  99 {
 100     LM32TimerState *s = opaque;
 101
 102     trace_lm32_timer_memory_write(addr, value);
 103
 104     addr >>= 2;
 105     switch (addr) {
 106     case R_SR:
 107         s->regs[R_SR] &= ~SR_TO;
 108         break;
 109     case R_CR:
 110         s->regs[R_CR] = value;
 111         if (s->regs[R_CR] & CR_START) {
 112             ptimer_run(s->ptimer, 1);
 113         }
 114         if (s->regs[R_CR] & CR_STOP) {
 115             ptimer_stop(s->ptimer);
 116         }
 117         break;
 118     case R_PERIOD:
 119         s->regs[R_PERIOD] = value;
 120         ptimer_set_count(s->ptimer, value);
 121         break;
 122     case R_SNAPSHOT:
 123         error_report("lm32_timer: write access to read only register 0x"
 124                 TARGET_FMT_plx, addr << 2);
 125         break;
 126     default:
 127         error_report("lm32_timer: write access to unknown register 0x"
 128                 TARGET_FMT_plx, addr << 2);
 129         break;
 130     }
 131     timer_update_irq(s);
 132 }
 133
 134 static CPUReadMemoryFunc * const timer_read_fn[] = {
 135     NULL,
 136     NULL,
 137     &timer_read,
 138 };
 139
 140 static CPUWriteMemoryFunc * const timer_write_fn[] = {
 141     NULL,
 142     NULL,
 143     &timer_write,
 144 };
 145
 146 static void timer_hit(void *opaque)
 147 {
 148     LM32TimerState *s = opaque;
 149
 150     trace_lm32_timer_hit();
 151
 152     s->regs[R_SR] |= SR_TO;
 153
 154     if (s->regs[R_CR] & CR_CONT) {
 155         ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
 156         ptimer_run(s->ptimer, 1);
 157     }
 158     timer_update_irq(s);
 159 }
 160
 161 static void timer_reset(DeviceState *d)
 162 {
 163     LM32TimerState *s = container_of(d, LM32TimerState, busdev.qdev);
 164     int i;
 165
 166     for (i = 0; i < R_MAX; i++) {
 167         s->regs[i] = 0;
 168     }
 169     ptimer_stop(s->ptimer);
 170 }
 171
 172 static int lm32_timer_init(SysBusDevice *dev)
 173 {
 174     LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
 175     int timer_regs;
 176
 177     sysbus_init_irq(dev, &s->irq);
 178
 179     s->bh = qemu_bh_new(timer_hit, s);
 180     s->ptimer = ptimer_init(s->bh);
 181     ptimer_set_freq(s->ptimer, s->freq_hz);
 182
 183     timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s,
 184             DEVICE_NATIVE_ENDIAN);
 185     sysbus_init_mmio(dev, R_MAX * 4, timer_regs);
 186
 187     return 0;
 188 }
 189
 190 static const VMStateDescription vmstate_lm32_timer = {
 191     .name = "lm32-timer",
 192     .version_id = 1,
 193     .minimum_version_id = 1,
 194     .minimum_version_id_old = 1,
 195     .fields      = (VMStateField[]) {
 196         VMSTATE_PTIMER(ptimer, LM32TimerState),
 197         VMSTATE_UINT32(freq_hz, LM32TimerState),
 198         VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
 199         VMSTATE_END_OF_LIST()
 200     }
 201 };
 202
 203 static SysBusDeviceInfo lm32_timer_info = {
 204     .init = lm32_timer_init,
 205     .qdev.name  = "lm32-timer",
 206     .qdev.size  = sizeof(LM32TimerState),
 207     .qdev.vmsd  = &vmstate_lm32_timer,
 208     .qdev.reset = timer_reset,
 209     .qdev.props = (Property[]) {
 210         DEFINE_PROP_UINT32(
 211                 "frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY
 212         ),
 213         DEFINE_PROP_END_OF_LIST(),
 214     }
 215 };
 216
 217 static void lm32_timer_register(void)
 218 {
 219     sysbus_register_withprop(&lm32_timer_info);
 220 }
 221
 222 device_init(lm32_timer_register)