hw/nand.c

   1 /*
   2  * Flash NAND memory emulation.  Based on "16M x 8 Bit NAND Flash
   3  * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
   4  * Samsung Electronic.
   5  *
   6  * Copyright (c) 2006 Openedhand Ltd.
   7  * Written by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * Support for additional features based on "MT29F2G16ABCWP 2Gx16"
  10  * datasheet from Micron Technology and "NAND02G-B2C" datasheet
  11  * from ST Microelectronics.
  12  *
  13  * This code is licensed under the GNU GPL v2.
  14  */
  15
  16 #ifndef NAND_IO
  17
  18 # include "hw.h"
  19 # include "flash.h"
  20 # include "blockdev.h"
  21 # include "sysbus.h"
  22
  23 # define NAND_CMD_READ0         0x00
  24 # define NAND_CMD_READ1         0x01
  25 # define NAND_CMD_READ2         0x50
  26 # define NAND_CMD_LPREAD2       0x30
  27 # define NAND_CMD_NOSERIALREAD2 0x35
  28 # define NAND_CMD_RANDOMREAD1   0x05
  29 # define NAND_CMD_RANDOMREAD2   0xe0
  30 # define NAND_CMD_READID        0x90
  31 # define NAND_CMD_RESET         0xff
  32 # define NAND_CMD_PAGEPROGRAM1  0x80
  33 # define NAND_CMD_PAGEPROGRAM2  0x10
  34 # define NAND_CMD_CACHEPROGRAM2 0x15
  35 # define NAND_CMD_BLOCKERASE1   0x60
  36 # define NAND_CMD_BLOCKERASE2   0xd0
  37 # define NAND_CMD_READSTATUS    0x70
  38 # define NAND_CMD_COPYBACKPRG1  0x85
  39
  40 # define NAND_IOSTATUS_ERROR    (1 << 0)
  41 # define NAND_IOSTATUS_PLANE0   (1 << 1)
  42 # define NAND_IOSTATUS_PLANE1   (1 << 2)
  43 # define NAND_IOSTATUS_PLANE2   (1 << 3)
  44 # define NAND_IOSTATUS_PLANE3   (1 << 4)
  45 # define NAND_IOSTATUS_BUSY     (1 << 6)
  46 # define NAND_IOSTATUS_UNPROTCT (1 << 7)
  47
  48 # define MAX_PAGE               0x800
  49 # define MAX_OOB                0x40
  50
  51 typedef struct NANDFlashState NANDFlashState;
  52 struct NANDFlashState {
  53     SysBusDevice busdev;
  54     uint8_t manf_id, chip_id;
  55     uint8_t buswidth; /* in BYTES */
  56     int size, pages;
  57     int page_shift, oob_shift, erase_shift, addr_shift;
  58     uint8_t *storage;
  59     BlockDriverState *bdrv;
  60     int mem_oob;
  61
  62     uint8_t cle, ale, ce, wp, gnd;
  63
  64     uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
  65     uint8_t *ioaddr;
  66     int iolen;
  67
  68     uint32_t cmd;
  69     uint64_t addr;
  70     int addrlen;
  71     int status;
  72     int offset;
  73
  74     void (*blk_write)(NANDFlashState *s);
  75     void (*blk_erase)(NANDFlashState *s);
  76     void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
  77
  78     uint32_t ioaddr_vmstate;
  79 };
  80
  81 static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
  82 {
  83     /* Like memcpy() but we logical-AND the data into the destination */
  84     int i;
  85     for (i = 0; i < n; i++) {
  86         dest[i] &= src[i];
  87     }
  88 }
  89
  90 # define NAND_NO_AUTOINCR       0x00000001
  91 # define NAND_BUSWIDTH_16       0x00000002
  92 # define NAND_NO_PADDING        0x00000004
  93 # define NAND_CACHEPRG          0x00000008
  94 # define NAND_COPYBACK          0x00000010
  95 # define NAND_IS_AND            0x00000020
  96 # define NAND_4PAGE_ARRAY       0x00000040
  97 # define NAND_NO_READRDY        0x00000100
  98 # define NAND_SAMSUNG_LP        (NAND_NO_PADDING | NAND_COPYBACK)
  99
 100 # define NAND_IO
 101
 102 # define PAGE(addr)             ((addr) >> ADDR_SHIFT)
 103 # define PAGE_START(page)       (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
 104 # define PAGE_MASK              ((1 << ADDR_SHIFT) - 1)
 105 # define OOB_SHIFT              (PAGE_SHIFT - 5)
 106 # define OOB_SIZE               (1 << OOB_SHIFT)
 107 # define SECTOR(addr)           ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
 108 # define SECTOR_OFFSET(addr)    ((addr) & ((511 >> PAGE_SHIFT) << 8))
 109
 110 # define PAGE_SIZE              256
 111 # define PAGE_SHIFT             8
 112 # define PAGE_SECTORS           1
 113 # define ADDR_SHIFT             8
 114 # include "nand.c"
 115 # define PAGE_SIZE              512
 116 # define PAGE_SHIFT             9
 117 # define PAGE_SECTORS           1
 118 # define ADDR_SHIFT             8
 119 # include "nand.c"
 120 # define PAGE_SIZE              2048
 121 # define PAGE_SHIFT             11
 122 # define PAGE_SECTORS           4
 123 # define ADDR_SHIFT             16
 124 # include "nand.c"
 125
 126 /* Information based on Linux drivers/mtd/nand/nand_ids.c */
 127 static const struct {
 128     int size;
 129     int width;
 130     int page_shift;
 131     int erase_shift;
 132     uint32_t options;
 133 } nand_flash_ids[0x100] = {
 134     [0 ... 0xff] = { 0 },
 135
 136     [0x6e] = { 1,       8,      8, 4, 0 },
 137     [0x64] = { 2,       8,      8, 4, 0 },
 138     [0x6b] = { 4,       8,      9, 4, 0 },
 139     [0xe8] = { 1,       8,      8, 4, 0 },
 140     [0xec] = { 1,       8,      8, 4, 0 },
 141     [0xea] = { 2,       8,      8, 4, 0 },
 142     [0xd5] = { 4,       8,      9, 4, 0 },
 143     [0xe3] = { 4,       8,      9, 4, 0 },
 144     [0xe5] = { 4,       8,      9, 4, 0 },
 145     [0xd6] = { 8,       8,      9, 4, 0 },
 146
 147     [0x39] = { 8,       8,      9, 4, 0 },
 148     [0xe6] = { 8,       8,      9, 4, 0 },
 149     [0x49] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 150     [0x59] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 151
 152     [0x33] = { 16,      8,      9, 5, 0 },
 153     [0x73] = { 16,      8,      9, 5, 0 },
 154     [0x43] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 155     [0x53] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 156
 157     [0x35] = { 32,      8,      9, 5, 0 },
 158     [0x75] = { 32,      8,      9, 5, 0 },
 159     [0x45] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 160     [0x55] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 161
 162     [0x36] = { 64,      8,      9, 5, 0 },
 163     [0x76] = { 64,      8,      9, 5, 0 },
 164     [0x46] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 165     [0x56] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 166
 167     [0x78] = { 128,     8,      9, 5, 0 },
 168     [0x39] = { 128,     8,      9, 5, 0 },
 169     [0x79] = { 128,     8,      9, 5, 0 },
 170     [0x72] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 171     [0x49] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 172     [0x74] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 173     [0x59] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 174
 175     [0x71] = { 256,     8,      9, 5, 0 },
 176
 177     /*
 178      * These are the new chips with large page size. The pagesize and the
 179      * erasesize is determined from the extended id bytes
 180      */
 181 # define LP_OPTIONS     (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
 182 # define LP_OPTIONS16   (LP_OPTIONS | NAND_BUSWIDTH_16)
 183
 184     /* 512 Megabit */
 185     [0xa2] = { 64,      8,      0, 0, LP_OPTIONS },
 186     [0xf2] = { 64,      8,      0, 0, LP_OPTIONS },
 187     [0xb2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 188     [0xc2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 189
 190     /* 1 Gigabit */
 191     [0xa1] = { 128,     8,      0, 0, LP_OPTIONS },
 192     [0xf1] = { 128,     8,      0, 0, LP_OPTIONS },
 193     [0xb1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 194     [0xc1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 195
 196     /* 2 Gigabit */
 197     [0xaa] = { 256,     8,      0, 0, LP_OPTIONS },
 198     [0xda] = { 256,     8,      0, 0, LP_OPTIONS },
 199     [0xba] = { 256,     16,     0, 0, LP_OPTIONS16 },
 200     [0xca] = { 256,     16,     0, 0, LP_OPTIONS16 },
 201
 202     /* 4 Gigabit */
 203     [0xac] = { 512,     8,      0, 0, LP_OPTIONS },
 204     [0xdc] = { 512,     8,      0, 0, LP_OPTIONS },
 205     [0xbc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 206     [0xcc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 207
 208     /* 8 Gigabit */
 209     [0xa3] = { 1024,    8,      0, 0, LP_OPTIONS },
 210     [0xd3] = { 1024,    8,      0, 0, LP_OPTIONS },
 211     [0xb3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 212     [0xc3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 213
 214     /* 16 Gigabit */
 215     [0xa5] = { 2048,    8,      0, 0, LP_OPTIONS },
 216     [0xd5] = { 2048,    8,      0, 0, LP_OPTIONS },
 217     [0xb5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 218     [0xc5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 219 };
 220
 221 static void nand_reset(DeviceState *dev)
 222 {
 223     NANDFlashState *s = FROM_SYSBUS(NANDFlashState, sysbus_from_qdev(dev));
 224     s->cmd = NAND_CMD_READ0;
 225     s->addr = 0;
 226     s->addrlen = 0;
 227     s->iolen = 0;
 228     s->offset = 0;
 229     s->status &= NAND_IOSTATUS_UNPROTCT;
 230 }
 231
 232 static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
 233 {
 234     s->ioaddr[s->iolen++] = value;
 235     for (value = s->buswidth; --value;) {
 236         s->ioaddr[s->iolen++] = 0;
 237     }
 238 }
 239
 240 static void nand_command(NANDFlashState *s)
 241 {
 242     unsigned int offset;
 243     switch (s->cmd) {
 244     case NAND_CMD_READ0:
 245         s->iolen = 0;
 246         break;
 247
 248     case NAND_CMD_READID:
 249         s->ioaddr = s->io;
 250         s->iolen = 0;
 251         nand_pushio_byte(s, s->manf_id);
 252         nand_pushio_byte(s, s->chip_id);
 253         nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
 254         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 255             /* Page Size, Block Size, Spare Size; bit 6 indicates
 256              * 8 vs 16 bit width NAND.
 257              */
 258             nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
 259         } else {
 260             nand_pushio_byte(s, 0xc0); /* Multi-plane */
 261         }
 262         break;
 263
 264     case NAND_CMD_RANDOMREAD2:
 265     case NAND_CMD_NOSERIALREAD2:
 266         if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
 267             break;
 268         offset = s->addr & ((1 << s->addr_shift) - 1);
 269         s->blk_load(s, s->addr, offset);
 270         if (s->gnd)
 271             s->iolen = (1 << s->page_shift) - offset;
 272         else
 273             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 274         break;
 275
 276     case NAND_CMD_RESET:
 277         nand_reset(&s->busdev.qdev);
 278         break;
 279
 280     case NAND_CMD_PAGEPROGRAM1:
 281         s->ioaddr = s->io;
 282         s->iolen = 0;
 283         break;
 284
 285     case NAND_CMD_PAGEPROGRAM2:
 286         if (s->wp) {
 287             s->blk_write(s);
 288         }
 289         break;
 290
 291     case NAND_CMD_BLOCKERASE1:
 292         break;
 293
 294     case NAND_CMD_BLOCKERASE2:
 295         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)
 296             s->addr <<= 16;
 297         else
 298             s->addr <<= 8;
 299
 300         if (s->wp) {
 301             s->blk_erase(s);
 302         }
 303         break;
 304
 305     case NAND_CMD_READSTATUS:
 306         s->ioaddr = s->io;
 307         s->iolen = 0;
 308         nand_pushio_byte(s, s->status);
 309         break;
 310
 311     default:
 312         printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
 313     }
 314 }
 315
 316 static void nand_pre_save(void *opaque)
 317 {
 318     NANDFlashState *s = opaque;
 319
 320     s->ioaddr_vmstate = s->ioaddr - s->io;
 321 }
 322
 323 static int nand_post_load(void *opaque, int version_id)
 324 {
 325     NANDFlashState *s = opaque;
 326
 327     if (s->ioaddr_vmstate > sizeof(s->io)) {
 328         return -EINVAL;
 329     }
 330     s->ioaddr = s->io + s->ioaddr_vmstate;
 331
 332     return 0;
 333 }
 334
 335 static const VMStateDescription vmstate_nand = {
 336     .name = "nand",
 337     .version_id = 1,
 338     .minimum_version_id = 1,
 339     .minimum_version_id_old = 1,
 340     .pre_save = nand_pre_save,
 341     .post_load = nand_post_load,
 342     .fields      = (VMStateField[]) {
 343         VMSTATE_UINT8(cle, NANDFlashState),
 344         VMSTATE_UINT8(ale, NANDFlashState),
 345         VMSTATE_UINT8(ce, NANDFlashState),
 346         VMSTATE_UINT8(wp, NANDFlashState),
 347         VMSTATE_UINT8(gnd, NANDFlashState),
 348         VMSTATE_BUFFER(io, NANDFlashState),
 349         VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
 350         VMSTATE_INT32(iolen, NANDFlashState),
 351         VMSTATE_UINT32(cmd, NANDFlashState),
 352         VMSTATE_UINT64(addr, NANDFlashState),
 353         VMSTATE_INT32(addrlen, NANDFlashState),
 354         VMSTATE_INT32(status, NANDFlashState),
 355         VMSTATE_INT32(offset, NANDFlashState),
 356         /* XXX: do we want to save s->storage too? */
 357         VMSTATE_END_OF_LIST()
 358     }
 359 };
 360
 361 static int nand_device_init(SysBusDevice *dev)
 362 {
 363     int pagesize;
 364     NANDFlashState *s = FROM_SYSBUS(NANDFlashState, dev);
 365
 366     s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
 367     s->size = nand_flash_ids[s->chip_id].size << 20;
 368     if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 369         s->page_shift = 11;
 370         s->erase_shift = 6;
 371     } else {
 372         s->page_shift = nand_flash_ids[s->chip_id].page_shift;
 373         s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
 374     }
 375
 376     switch (1 << s->page_shift) {
 377     case 256:
 378         nand_init_256(s);
 379         break;
 380     case 512:
 381         nand_init_512(s);
 382         break;
 383     case 2048:
 384         nand_init_2048(s);
 385         break;
 386     default:
 387         hw_error("%s: Unsupported NAND block size.\n", __func__);
 388     }
 389
 390     pagesize = 1 << s->oob_shift;
 391     s->mem_oob = 1;
 392     if (s->bdrv && bdrv_getlength(s->bdrv) >=
 393             (s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
 394         pagesize = 0;
 395         s->mem_oob = 0;
 396     }
 397
 398     if (!s->bdrv) {
 399         pagesize += 1 << s->page_shift;
 400     }
 401     if (pagesize) {
 402         s->storage = (uint8_t *) memset(qemu_malloc(s->pages * pagesize),
 403                         0xff, s->pages * pagesize);
 404     }
 405     /* Give s->ioaddr a sane value in case we save state before it is used. */
 406     s->ioaddr = s->io;
 407
 408     return 0;
 409 }
 410
 411 static SysBusDeviceInfo nand_info = {
 412     .init = nand_device_init,
 413     .qdev.name = "nand",
 414     .qdev.size = sizeof(NANDFlashState),
 415     .qdev.reset = nand_reset,
 416     .qdev.vmsd = &vmstate_nand,
 417     .qdev.props = (Property[]) {
 418         DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
 419         DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
 420         DEFINE_PROP_DRIVE("drive", NANDFlashState, bdrv),
 421         DEFINE_PROP_END_OF_LIST()
 422     }
 423 };
 424
 425 static void nand_create_device(void)
 426 {
 427     sysbus_register_withprop(&nand_info);
 428 }
 429
 430 /*
 431  * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins.  Chip
 432  * outputs are R/B and eight I/O pins.
 433  *
 434  * CE, WP and R/B are active low.
 435  */
 436 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
 437                   uint8_t ce, uint8_t wp, uint8_t gnd)
 438 {
 439     NANDFlashState *s = (NANDFlashState *) dev;
 440     s->cle = cle;
 441     s->ale = ale;
 442     s->ce = ce;
 443     s->wp = wp;
 444     s->gnd = gnd;
 445     if (wp)
 446         s->status |= NAND_IOSTATUS_UNPROTCT;
 447     else
 448         s->status &= ~NAND_IOSTATUS_UNPROTCT;
 449 }
 450
 451 void nand_getpins(DeviceState *dev, int *rb)
 452 {
 453     *rb = 1;
 454 }
 455
 456 void nand_setio(DeviceState *dev, uint32_t value)
 457 {
 458     int i;
 459     NANDFlashState *s = (NANDFlashState *) dev;
 460     if (!s->ce && s->cle) {
 461         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 462             if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
 463                 return;
 464             if (value == NAND_CMD_RANDOMREAD1) {
 465                 s->addr &= ~((1 << s->addr_shift) - 1);
 466                 s->addrlen = 0;
 467                 return;
 468             }
 469         }
 470         if (value == NAND_CMD_READ0)
 471             s->offset = 0;
 472         else if (value == NAND_CMD_READ1) {
 473             s->offset = 0x100;
 474             value = NAND_CMD_READ0;
 475         }
 476         else if (value == NAND_CMD_READ2) {
 477             s->offset = 1 << s->page_shift;
 478             value = NAND_CMD_READ0;
 479         }
 480
 481         s->cmd = value;
 482
 483         if (s->cmd == NAND_CMD_READSTATUS ||
 484                 s->cmd == NAND_CMD_PAGEPROGRAM2 ||
 485                 s->cmd == NAND_CMD_BLOCKERASE1 ||
 486                 s->cmd == NAND_CMD_BLOCKERASE2 ||
 487                 s->cmd == NAND_CMD_NOSERIALREAD2 ||
 488                 s->cmd == NAND_CMD_RANDOMREAD2 ||
 489                 s->cmd == NAND_CMD_RESET)
 490             nand_command(s);
 491
 492         if (s->cmd != NAND_CMD_RANDOMREAD2) {
 493             s->addrlen = 0;
 494         }
 495     }
 496
 497     if (s->ale) {
 498         unsigned int shift = s->addrlen * 8;
 499         unsigned int mask = ~(0xff << shift);
 500         unsigned int v = value << shift;
 501
 502         s->addr = (s->addr & mask) | v;
 503         s->addrlen ++;
 504
 505         switch (s->addrlen) {
 506         case 1:
 507             if (s->cmd == NAND_CMD_READID) {
 508                 nand_command(s);
 509             }
 510             break;
 511         case 2: /* fix cache address as a byte address */
 512             s->addr <<= (s->buswidth - 1);
 513             break;
 514         case 3:
 515             if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 516                     (s->cmd == NAND_CMD_READ0 ||
 517                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 518                 nand_command(s);
 519             }
 520             break;
 521         case 4:
 522             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 523                     nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
 524                     (s->cmd == NAND_CMD_READ0 ||
 525                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 526                 nand_command(s);
 527             }
 528             break;
 529         case 5:
 530             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 531                     nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
 532                     (s->cmd == NAND_CMD_READ0 ||
 533                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 534                 nand_command(s);
 535             }
 536             break;
 537         default:
 538             break;
 539         }
 540     }
 541
 542     if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
 543         if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
 544             for (i = s->buswidth; i--; value >>= 8) {
 545                 s->io[s->iolen ++] = (uint8_t) (value & 0xff);
 546             }
 547         }
 548     } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
 549         if ((s->addr & ((1 << s->addr_shift) - 1)) <
 550                 (1 << s->page_shift) + (1 << s->oob_shift)) {
 551             for (i = s->buswidth; i--; s->addr++, value >>= 8) {
 552                 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
 553                     (uint8_t) (value & 0xff);
 554             }
 555         }
 556     }
 557 }
 558
 559 uint32_t nand_getio(DeviceState *dev)
 560 {
 561     int offset;
 562     uint32_t x = 0;
 563     NANDFlashState *s = (NANDFlashState *) dev;
 564
 565     /* Allow sequential reading */
 566     if (!s->iolen && s->cmd == NAND_CMD_READ0) {
 567         offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
 568         s->offset = 0;
 569
 570         s->blk_load(s, s->addr, offset);
 571         if (s->gnd)
 572             s->iolen = (1 << s->page_shift) - offset;
 573         else
 574             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 575     }
 576
 577     if (s->ce || s->iolen <= 0)
 578         return 0;
 579
 580     for (offset = s->buswidth; offset--;) {
 581         x |= s->ioaddr[offset] << (offset << 3);
 582     }
 583     /* after receiving READ STATUS command all subsequent reads will
 584      * return the status register value until another command is issued
 585      */
 586     if (s->cmd != NAND_CMD_READSTATUS) {
 587         s->addr   += s->buswidth;
 588         s->ioaddr += s->buswidth;
 589         s->iolen  -= s->buswidth;
 590     }
 591     return x;
 592 }
 593
 594 uint32_t nand_getbuswidth(DeviceState *dev)
 595 {
 596     NANDFlashState *s = (NANDFlashState *) dev;
 597     return s->buswidth << 3;
 598 }
 599
 600 DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id)
 601 {
 602     DeviceState *dev;
 603
 604     if (nand_flash_ids[chip_id].size == 0) {
 605         hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
 606     }
 607     dev = qdev_create(NULL, "nand");
 608     qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
 609     qdev_prop_set_uint8(dev, "chip_id", chip_id);
 610     if (bdrv) {
 611         qdev_prop_set_drive_nofail(dev, "drive", bdrv);
 612     }
 613
 614     qdev_init_nofail(dev);
 615     return dev;
 616 }
 617
 618 device_init(nand_create_device)
 619
 620 #else
 621
 622 /* Program a single page */
 623 static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
 624 {
 625     uint64_t off, page, sector, soff;
 626     uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
 627     if (PAGE(s->addr) >= s->pages)
 628         return;
 629
 630     if (!s->bdrv) {
 631         mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
 632                         s->offset, s->io, s->iolen);
 633     } else if (s->mem_oob) {
 634         sector = SECTOR(s->addr);
 635         off = (s->addr & PAGE_MASK) + s->offset;
 636         soff = SECTOR_OFFSET(s->addr);
 637         if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1) {
 638             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 639             return;
 640         }
 641
 642         mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
 643         if (off + s->iolen > PAGE_SIZE) {
 644             page = PAGE(s->addr);
 645             mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
 646                             MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
 647         }
 648
 649         if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS) == -1)
 650             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 651     } else {
 652         off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
 653         sector = off >> 9;
 654         soff = off & 0x1ff;
 655         if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1) {
 656             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 657             return;
 658         }
 659
 660         mem_and(iobuf + soff, s->io, s->iolen);
 661
 662         if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) == -1)
 663             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 664     }
 665     s->offset = 0;
 666 }
 667
 668 /* Erase a single block */
 669 static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
 670 {
 671     uint64_t i, page, addr;
 672     uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
 673     addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
 674
 675     if (PAGE(addr) >= s->pages)
 676         return;
 677
 678     if (!s->bdrv) {
 679         memset(s->storage + PAGE_START(addr),
 680                         0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
 681     } else if (s->mem_oob) {
 682         memset(s->storage + (PAGE(addr) << OOB_SHIFT),
 683                         0xff, OOB_SIZE << s->erase_shift);
 684         i = SECTOR(addr);
 685         page = SECTOR(addr + (ADDR_SHIFT + s->erase_shift));
 686         for (; i < page; i ++)
 687             if (bdrv_write(s->bdrv, i, iobuf, 1) == -1)
 688                 printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
 689     } else {
 690         addr = PAGE_START(addr);
 691         page = addr >> 9;
 692         if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
 693             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 694         memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
 695         if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
 696             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 697
 698         memset(iobuf, 0xff, 0x200);
 699         i = (addr & ~0x1ff) + 0x200;
 700         for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
 701                         i < addr; i += 0x200)
 702             if (bdrv_write(s->bdrv, i >> 9, iobuf, 1) == -1)
 703                 printf("%s: write error in sector %" PRIu64 "\n",
 704                        __func__, i >> 9);
 705
 706         page = i >> 9;
 707         if (bdrv_read(s->bdrv, page, iobuf, 1) == -1)
 708             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 709         memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
 710         if (bdrv_write(s->bdrv, page, iobuf, 1) == -1)
 711             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 712     }
 713 }
 714
 715 static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
 716                 uint64_t addr, int offset)
 717 {
 718     if (PAGE(addr) >= s->pages)
 719         return;
 720
 721     if (s->bdrv) {
 722         if (s->mem_oob) {
 723             if (bdrv_read(s->bdrv, SECTOR(addr), s->io, PAGE_SECTORS) == -1)
 724                 printf("%s: read error in sector %" PRIu64 "\n",
 725                                 __func__, SECTOR(addr));
 726             memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
 727                             s->storage + (PAGE(s->addr) << OOB_SHIFT),
 728                             OOB_SIZE);
 729             s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
 730         } else {
 731             if (bdrv_read(s->bdrv, PAGE_START(addr) >> 9,
 732                                     s->io, (PAGE_SECTORS + 2)) == -1)
 733                 printf("%s: read error in sector %" PRIu64 "\n",
 734                                 __func__, PAGE_START(addr) >> 9);
 735             s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
 736         }
 737     } else {
 738         memcpy(s->io, s->storage + PAGE_START(s->addr) +
 739                         offset, PAGE_SIZE + OOB_SIZE - offset);
 740         s->ioaddr = s->io;
 741     }
 742 }
 743
 744 static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
 745 {
 746     s->oob_shift = PAGE_SHIFT - 5;
 747     s->pages = s->size >> PAGE_SHIFT;
 748     s->addr_shift = ADDR_SHIFT;
 749
 750     s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
 751     s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
 752     s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
 753 }
 754
 755 # undef PAGE_SIZE
 756 # undef PAGE_SHIFT
 757 # undef PAGE_SECTORS
 758 # undef ADDR_SHIFT
 759 #endif  /* NAND_IO */